CTNF 18/254,848 CTNF 90499 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 10-14, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Obara et al. (U.S. Patent Application Publication No. 2011/0109791) . Regarding to claim 1, Obara teaches semiconductor module, comprising: a substrate (Fig. 2, Fig. 7, element 2 ); a first semiconductor element arranged on the substrate and including a wiring electrically connected to the substrate and a pixel region of an imaging element on an upper surface opposite to a surface facing the substrate (Fig. 2, Fig. 7, element 4 , image sensor 4 arranged on the substrate and including a wiring electrically connected to the substrate, pixel region of the imaging element on its upper surface ); a second semiconductor element arranged at a position different from the pixel region on the upper surface of the first semiconductor element (Fig. 2, Fig. 7, element 8 ; [0017], lines 1-2, lines 4-6); and a cover part that covers the first and second semiconductor elements from the upper surface with respect to at least a part of a region excluding the pixel region (Fig. 2, Fig. 7, element 6b ). Regarding to claim 2, Obara teaches the cover part is a frame having an opening corresponding to the pixel region and is attached to the substrate so as to cover the first and second semiconductor elements from the upper surface (Fig. 2, Fig. 7). Regarding to claim 3, Obara teaches the frame is formed by resin or metal ([0016], line 3). Regarding to claim 10, Obara teaches a sealing glass bonded to an upper surface of the frame via a sealing material (Fig. 2, Fig. 7, element 6a ; [0016], lines 1-2). Regarding to claim 11, Obara teaches the frame includes a recess in a region in contact with the sealing glass in an inner wall facing the pixel region (Fig. 2, Fig. 7). Regarding to claim 12, Obara teaches the cover part is a sealing resin that seals a portion other than an opening corresponding to the pixel region. (Fig. 2, Fig. 7; [0016], line 3). Regarding to claim 13, Obara teaches a sealing glass bonded to an upper surface of the sealing resin via a sealing material ([0016], last 3 lines). Regarding to claim 14, Obara teaches a transparent resin in the opening (Fig. 7, note that the claim does not specify a level of transparency. All resins are transparent at some level at a range of wavelength of light ). Regarding to claim 20, Obara teaches a method for manufacturing a semiconductor module, the method comprising: a procedure of forming a second semiconductor element at a position different from a pixel region of an imaging element on an upper surface of a first semiconductor element including the pixel region (Fig. 7, second semiconductor element 8 at position different from a pixel region of an imaging element on an upper surface of a first semiconductor element 4 including the pixel region ); a procedure of mounting the first semiconductor element on a substrate and forming a wiring electrically connected to the substrate (Fig. 7, mounting the first semiconductor element 4 on substrate 2 and forming a wiring electrically connected to the substrate ); a procedure of forming a cover part that covers the first and second semiconductor elements from the upper surface with respect to at least a part of a region excluding the pixel region (Fig. 7, element 6 ) . 07-15 AIA Claim s 1-9, 12, 15, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Nagamatsu et al. (U.S. Patent No. 8,269,298) . Regarding to claim 1, Nagamatsu teaches semiconductor module, comprising: a substrate (Fig. 7, element 10 ); a first semiconductor element arranged on the substrate and including a wiring electrically connected to the substrate and a pixel region of an imaging element on an upper surface opposite to a surface facing the substrate (Fig. 7, element 11 ; column 3, lines 58-59, image sensor 11 arranged on the substrate and including a wiring electrically connected to the substrate, pixel region of the imaging element on its upper surface ); a second semiconductor element arranged at a position different from the pixel region on the upper surface of the first semiconductor element (Fig. 7, element 23 ; column 7, lines 28-29); and a cover part that covers the first and second semiconductor elements from the upper surface with respect to at least a part of a region excluding the pixel region (Fig. 7, the structure including element 280 and element 20 ). Regarding to claim 2, Nagamatsu teaches the cover part is a frame having an opening corresponding to the pixel region and is attached to the substrate so as to cover the first and second semiconductor elements from the upper surface (Fig. 7). Regarding to claim 3, Nagamatsu teaches the frame is formed by resin or metal (column 7, lines 25-27). Regarding to claim 4, Nagamatsu teaches the frame has a hollow structure with respect to a region including the second semiconductor element and the wiring (Fig. 7). Regarding to claim 5, Nagamatsu teaches a filling portion filled in a sealed manner in a region including the second semiconductor element and the wiring (Fig. 7, element 31 ). Regarding to claim 6, Nagamatsu teaches the filling portion is formed by resin (column 4, line 42). Regarding to claim 7, Nagamatsu teaches the frame is in contact with the upper surface of the second semiconductor element (Fig. 7, portion 280 of the frame is in contact with the upper surface of the second semiconductor element 23 ). Regarding to claim 8, Nagamatsu teaches the frame is embossed on an inner wall facing the pixel region (Fig. 7). Regarding to claim 9, Nagamatsu teaches the frame has a tapered structure in which an inner wall facing the pixel region is inclined toward the pixel region (Fig. 7, portion 20 the frame has a tapered structure in which an inner wall facing the pixel region is inclined toward the pixel region ). Regarding to claim 12, Nagamatsu teaches the cover part is a sealing resin that seals a portion other than an opening corresponding to the pixel region (Fig. 7, element 280 ; column 7, line 26). Regarding to claim 15, Nagamatsu teaches the cover part is a molding resin that covers a back surface and a side surface of the second semiconductor element (Fig. 7, element 280 ; column 7, line 26, cover part 280 is a molding resin that covers a back surface and a side surface of the second semiconductor element 23 ). Regarding to claim 20, Nagamatsu teaches a method for manufacturing a semiconductor module, the method comprising: a procedure of forming a second semiconductor element at a position different from a pixel region of an imaging element on an upper surface of a first semiconductor element including the pixel region (Fig. 7, second semiconductor element 23 at position different from a pixel region of imaging element on an upper surface of first semiconductor element 11 including the pixel region ); a procedure of mounting the first semiconductor element on a substrate and forming a wiring electrically connected to the substrate (Fig. 7, mounting the first semiconductor element 11 on substrate 10 and forming wiring 14 electrically connected to the substrate ); a procedure of forming a cover part that covers the first and second semiconductor elements from the upper surface with respect to at least a part of a region excluding the pixel region (Fig. 7, element 20/280 ) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nagamatsu et al. (U.S. Patent No. 8,269,298), as applied to claim 1 and 15 above, in view of Nakamura (U.S. Patent No. 8,233,064) . Regarding to claim 16, Nagamatsu does not disclose the molding resin contains a filler. Nakamura discloses a molding resin contains a filler (column 7, line 58). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nagamatsu in view of Nakamura to contain a filler in the molding resin in order to increase reliability. Allowable Subject Matter Claims 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding to claim 17, the prior art fails to anticipate or render obvious the claimed limitations including “the second semiconductor element is bonded to the first semiconductor element via an underfill, and a fillet of the underfill is located outside the molding resin” in combination with the limitations recited in claims 1 and 15. Regarding to claim 18, the prior art fails to anticipate or render obvious the claimed limitations including “each of the first and second semiconductor elements is a semiconductor chip and forms a chip-on-chip structure” in combination with the limitations recited in claim 1. Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “the first semiconductor element is a semiconductor wafer, the second semiconductor element is a semiconductor chip, and the first and second semiconductor elements form a chip-on wafer structure” in combination with the limitations recited in claim 1. Pertinent Art For the benefits of the Applicant, US-9996725-B2, US-8890274-B2, US-10998361-B2, US-9966401-B2, US-8796800-B2, US-20130264703-A1, US-6777767-B2, and US-20230309361-A1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The reference fails to disclose the combination of limitations including “a second semiconductor element arranged at a position different from the pixel region on the upper surface of the first semiconductor element; and a cover part that covers the first and second semiconductor elements from the upper surface with respect to at least a part of a region excluding the pixel region.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897 Application/Control Number: 18/254,848 Page 2 Art Unit: 2897 Application/Control Number: 18/254,848 Page 4 Art Unit: 2897 Application/Control Number: 18/254,848 Page 6 Art Unit: 2897 Application/Control Number: 18/254,848 Page 7 Art Unit: 2897 Application/Control Number: 18/254,848 Page 8 Art Unit: 2897 Application/Control Number: 18/254,848 Page 9 Art Unit: 2897
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