DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered.
Election/Restrictions
Applicant’s election of Group I (claims 1-29) in the reply is noted. Applicant elects “with traverse” but only provides the conclusory reasoning that there is not unduly burdensome burden. Since applicant has not provided any substantive reasoning or evidence to support the conclusion, this has been treated as an election without traverse.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites “the pulse-width modulated signals” which lack antecedent basis. The examiner has treated this as dependent on claim 15, but notes that claim 18 doesn’t include “input”.
There are two “claim 8” citations. The Examiner has treated them both and labeled the second one “8.2” below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 8, 8.1, 9, 10, 11, 13, 14, 19, 20, and 23-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2020/0364548).
Regarding claim 1, Chang discloses a system comprising: a transistor array including a plurality of charge-trap transistors (see Figure 1, 34a,a; 34a,n), the charge-trap transistors being operatively coupled with corresponding input nodes (from 18); and a neural integrator (232) including a first integrator node and a second integrator node (Vin Vip) operatively coupled with the transistor array, and generating an output (dim/dip) corresponding to a neuron of a neural network system .
Regarding claim 2, Chang discloses the system of claim 1, the transistor array further comprising: a first charge-trap transistor (34a,a for example) having a first transistor node operatively coupled with a first input node of the input nodes (source/drain to 18), and a second transistor node (connected to 22) operatively coupled with the first integrator node.
Regarding claim 6, Chang discloses the system of claim 1, wherein the input nodes comprise inputs to the neural network system (by definition, is a neural network system).
Regarding claim 8, Chang discloses the system of claim 1, wherein the input nodes are operatively coupled with corresponding drain terminals of the plurality of charge-trap transistors (see Figure 1, inputs from 18 coupled to source/drain).
Regarding claim 8.2, Chang discloses the system of claim 1, the transistor array further comprising: a second plurality (34m,1, 34m,n) of charge-trap transistors operatively coupled with a bias node (column line to 18).
Regarding claim 9, Chang discloses the system of claim 8, wherein the bias node comprises a bias input to the neural network system (is an input and an neural network).
Regarding claim 10, Chang discloses the system of claim 1, further comprising: a switch (see Figure 5, switches in 192) operatively coupled with the transistor array and the neural integrator, the switch operable to electrically isolate the transistor array from the neural integrator based on a signal propagation delay through the transistor array (capacitive propagation delay).
Regarding claim 11, Chang discloses the system of claim 1, wherein the plurality of charge-trap transistors comprises a plurality of pairs (34a’s and 34b’s for example) of charge-trap transistors each operatively coupled with a corresponding ones of the input nodes (columns connected to same input line).
Regarding claim 13, Chang discloses the system of claim 1, wherein the neural integrator further comprises: a first current source (via M1p) operatively coupled with the first integrator node and operable to apply a first current to the first integrator node in accordance with a weight associated with the neuron (ViP).
Regarding claim 14, Chang discloses the system of claim 13, wherein the neural integrator further comprises:a second current source (M1N) operatively coupled with the second integrator node and operable to apply a second current to the second integrator node in accordance with the weight associated with the neuron (VIN).
Regarding claim 19, Chang discloses the system of claim 1, wherein the transistor array and the neural integrator comprise one neuron of a plurality of interconnected neurons in the neural network system (see abstract).
Regarding claim 20, Chang discloses a transistor array device comprising:a first charge-trap transistor having a first transistor node operatively coupled with a first input node of a plurality of input nodes, and a second transistor node operatively coupled with a first integrator node of a neural integrator; and a second charge-trap transistor having a first transistor node operatively coupled with the first input node of the input nodes, a second transistor node operatively coupled with a second integrator node of the neural integrator, and a third transistor node operatively coupled with a third transistor node of the first charge-trap transistor (see rejection of claim 2 above).
Regarding claim 23, Chang discloses the device of claim 20, further comprising: a first switch operatively coupled with the first charge-trap transistor (see rejection of claim 10 above).
Regarding claim 24, Chang discloses the device of claim 23, wherein the first switch is operable to electrically isolate the first charge-trap transistor and the second charge-trap transistor from the first integrator node and the second integrator node based on a signal propagation delay through the first charge-trap transistor and the second charge-trap transistor (see rejection of claim 10 above).
Regarding claim 25, Chang discloses the device of claim 23, further comprising: a second switch operatively coupled with the second charge-trap transistor (see rejection of claim 10 above).
Regarding claim 26, Chang discloses the device of claim 25, wherein the second switch is operable to electrically isolate the first charge-trap transistor and the second charge-trap transistor from the first integrator node and the second integrator node based on a signal propagation delay through the first charge-trap transistor and the second charge-trap transistor (see rejection of claim 10 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7, 15, 16, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2020/0364548) in view of Tran (US 2021/0209458).
Regarding claim 7, Chang discloses the system of claim 1, but fails to teach the input nodes are operatively coupled with corresponding gate terminals of the plurality of charge-trap transistors. However, it was known at the time of filing to provide inputs of such arrays to the gates as an alternative to the source/drain as taught by Chang (see Tran, paragraph 0185 for example). Therefore, it would have been obvious to one having ordinary skill at the time of filing reconfigure the device of Chang such that the input is on the gate node as opposed to the source/drain node since this was a known technique at the time of filing and would yield the predictable result of the input signal effecting the storage/output of the device.
Regarding claim 15, Chang discloses the system of claim 1, but fails to teach the input nodes are operable to receive pulse-width modulated input signals. However, it was known at the time of filing to use PWM signals for the operations of such devices (see Chang, paragraph 0185 for example).
Regarding claims 16 and 17, Chang discloses the system of claim 15 while the combined references are silent with respect to the variability of the pulse amplitudes, the relationship between pulse amplitude and its effect on charge trap transistors was well known to one of ordinary skill at the time of filing. Therefore, it would have been obvious to one having ordinary skill at the time of filing to either vary or keep the amplitude constant depending on the needs and the tradeoffs desired (e.g. current capacity, speed, etc.).
Regarding claim 18, inasmuch as understood Chang discloses the system of claim 15, wherein the pulse-width modulated signals comprise training inputs to the neural network system (the type of data/signals input represents non descriptive functional material and imparts no particular structure to the device).
Claim(s) 3-5, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2020/0364548) in view of Holler (US 4,950,917 or 5,256,911).
Regarding claims 3-5, 21 and 22 Chang discloses a second, third, fourth, etc. charge trap transistors but fails to teach them connected in the same common node connection (i.e. cell-pair) as claimed.
However, this was a known configuration for flash cell based neural networks. For example, Holler (see Figure 3, 4, 7, 8 etc.) teaches two programmable gate transistors paired together and used to store differential weights with the pair providing differential outputs for connection to processing circuitry. Therefore, it would have been obvious to one having ordinary skill at the time of filing to modify the device of Chang to such that two transistors of chang are paired and used to store a differential weight in the manner of Holler to improve multiplication linearity (see column 8, lines 65+).
Claim(s) 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holler (US 5,256,911) in view of Doorenbos (US 2008/0258951).
Regarding claim 27, Holler discloses a neural logic, comprising: a first node (see Figure 8 for example, +input to 15) operatively coupled with a first storage transistor (one of cells in 102) of a transistor array; a second integrator node (-input) operatively coupled with a second storage transistor of the transistor array (other cell in 102), the second charge-trap transistor being operatively coupled with the first charge-trap transistor (sources commoned to ground; gates commonly connected).
Holler fails to teach the storage transistors are charge trap transistors and also fails to teach the integrator comprises a capacitor operatively coupled with the first integrator node and the second integrator node, and operable to generate an output based on a first voltage at the first integrator node and a second voltage at the second integrator node.
However, the use of charge traps as an alternative to the floating gates of Holler is well known in the art and it would have been obvious to one having ordinary skill at the time of filing to provide of a charge trap storage to realize the well-known benefits thereof (e.g. CMOS compatibility, scalability, improved analog storage).
Further, the use of such integrating circuitry in signal processing applications was also known. For example, Doorenbos teaches an integrator comprising a capacitor (see Figure 3a, 430) operatively coupled with a first integrator node (Vin+) and a second integrator node (Vin-), and operable to generate an output based on a first voltage at the first integrator node and a second voltage at the second integrator node (output of 412 or 414).
Therefore, it would have been obvious to one having ordinary skill at the time of filing to implement the integrator of Doorenbos as the integrator of Holler since this was a known configuration for such an integrator and the combination would yield the predictable result of an integrated output.
Regarding claim 28, Chang discloses the neural integrator of claim 27, wherein the output corresponds to a neuron of a neural network system (see Figure 8) .
Regarding claim 29, Chang discloses the neural integrator of claim 27, further comprising: a first analog amplifier (412) having a first output terminal operatively coupled with a first terminal of the capacitor, and a second output terminal operatively coupled with a second terminal of the capacitor (via switches 436, 434, etc).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable Chang in view of Doorenbos (US 2008/0258951).
Regarding claims 12, Chang fails to teach the neural integrator further comprises: a capacitor operable to generate the output corresponding to the neuron based on a first voltage at the first integrator node and a second voltage at the second integrator node; and a first analog amplifier having a first output terminal operatively coupled with a first terminal of the capacitor, and a second output terminal operatively coupled with a second terminal of the capacitor.
However, as noted above, these are known configurations of neural integrators (see rejection of claim 27 above relying on Doorenbos). Therefore, it would have been obvious to one having ordinary skill at the time of filing to implement the integrator of Doorenbos as the integrator of Chang since this was a known configuration for such an integrator and the combination would yield the predictable result of an integrated output
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The cited and attached references teach various embodiments of neural integrator configurations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS KING/Primary Examiner, Art Unit 2824
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