DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hayasaki(USPGPUB DOCUMENT: 2010/0327383, hereinafter Hayasaki) in view of Akiyama-849 (USPGPUB DOCUMENT: 2010/0102454, hereinafter Akiyama-454) and Akiyama-849 (USPGPUB DOCUMENT: 2011/0024849, hereinafter Akiyama-849).
Re claim 1 Hayasaki discloses a semiconductor device, comprising: a through electrode(26B/42)[0034] that penetrates a semiconductor substrate(10) along a direction perpendicular to a front surface of the semiconductor substrate(10);
an insulating film(35) covering the through electrode(26B/42)[0034]; and a wiring layer(29A/28A/26A/24A) that includes at least one gate(24A) disposed an inner periphery(portion of innermost 35) of the insulating film(35) at the front surface.
Hayasaki does not disclose a through electrode(26B/42)[0034] that penetrates a semiconductor substrate(10) along a direction perpendicular to a front surface and a back surface; an insulating film(35) covering the through electrode(26B/42)[0034] from the front surface to the back surface of the semiconductor substrate; a dummy gate; and a wiring layer that includes at least one dummy gate disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery(portion of innermost 35) edge and an outer periphery edge of the insulating film(35) at the front surface of the semiconductor substrate.
Akiyama-454 disclose a through electrode(45) that penetrates a semiconductor substrate(11) along a direction perpendicular to a front surface and a back surface; an insulating film(43) covering the through electrode(45) from the front surface to the back surface of the semiconductor substrate; a wiring layer(wiring within 19/24/30) that includes at least one gate(left13a/right13a) disposed within an annular region defined at the front surface of the semiconductor substrate(11) between an inner periphery(inner periphery of 43) edge and an outer periphery(outer periphery of 43 Akiyama-454) edge of the insulating film(43) at the front surface of the semiconductor substrate(11).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama-454 to the teachings of Hayasaki in order to improve the packaging density of a semiconductor device [0005, Akiyama-454].
Hayasaki and Akiyama-454 do not disclose a dummy gate; and a wiring layer that includes at least one dummy gate disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery(portion of innermost 35) edge and an outer periphery edge of the insulating film(35) at the front surface of the semiconductor substrate.
Akiyama-849 disclose a dummy gate(212 of Akiyama-849)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama-849 to the teachings of Hayasaki in order to prevent an increase in electrical resistance at a connection [0004, Akiyama]. In doing so, a wiring layer that includes at least one dummy gate(212 of Akiyama-849) disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery edge and an outer periphery edge(outer periphery of 43 Akiyama-454) of the insulating film(43 of Akiyama-454) at the front surface of the semiconductor substrate(11 ofAkiyama-454).
Re claim 2 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein the at least one dummy gate(212 of Akiyama) is not disposed inside the inner periphery edge(portion of innermost 35).
Re claim 3 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein the at least one dummy gate(212 of Akiyama) is further disposed outside the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35).
Re claim 4 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 3, wherein the semiconductor substrate(10) includes an element isolation region(22A) formed under the wiring layer(29A/28A/26A/24A), andthe at least one dummy gate(212 of Akiyama) is disposed on an upper portion of the element isolation region(22A).
Re claim 5 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein an area ratio[0037] of the at least one dummy gate(212 of Akiyama) is not less than ten percent.
Re claim 6 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein a predetermined number of wirings are formed in the wiring layer(29A/28A/26A/24A), anda pitch of the wirings inside the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35) is substantially equal to a pitch of the wirings outside the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35).
Re claim 7 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein a gate electrode(51 of Akiyama) is further disposed in the wiring layer(29A/28A/26A/24A), anda material of the at least one dummy gate(212 of Akiyama)[0032] is same as a material of the gate electrode(51 of Akiyama).
Re claim 8 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 7, wherein the material of the at least one dummy gate(212 of Akiyama)[0032] is amorphous silicon.
Re claim 9 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein a gate electrode(51 of Akiyama) is further disposed in the wiring layer(29A/28A/26A/24A), andthe material of the at least one dummy gate(212 of Akiyama)[0032] is different from a material of the gate electrode(51 of Akiyama).
Re claim 10 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 9, wherein a material of the at least one dummy gate(212 of Akiyama)[0032] is silicon nitride.
Re claim 11 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein in the through electrode(26B/42)[0034], a cross-sectional area of an upper end on a front surface si e is smaller than a cross-sectional area of a lower end on a back surface side with respect to the front surface, andthe at least one dummy gate(212 of Akiyama) is disposed between the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) covering the upper end of the front surface and the inner periphery edge(portion of innermost 35) of the insulating film(35) covering the upper end.
Re claim 12 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein in the through electrode(26B/42)[0034], a cross-sectional area of an upper end on a front surface side is larger than a cross-sectional area of a lower end on a back surface side with respect to the front surface, andthe at least one dummy gate(212 of Akiyama) is disposed between the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) covering the lower end of the front surface and the inner periphery edge(portion of innermost 35) of the insulating film(35) covering the lower end.
Re claim 13 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein the semiconductor substrate(10) includes an element isolation region(22A) formed over an entire surface of a region between the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) and the inner periphery edge(portion of innermost 35) of the insulating film(35).
Re claim 14 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein the semiconductor substrate(10) includes an element isolation region(22A) formed in a part of a region between the outer periphery edge(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) and the inner periphery edge(portion of innermost 35) of the insulating film(35), and the at least one dummy gate(212 of Akiyama) is disposed on an upper side of the element isolation region(22A).
Re claim 15 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 1, wherein a gate electrode(51 of Akiyama) of a Fin field-effect transistor (Fin-FET) is further disposed in the wiring layer(29A/28A/26A/24A).
Re claim 17 Hayasaki discloses a semiconductor device, comprising: a through electrode(26B/42)[0034] that penetrates a semiconductor substrate(10) along a direction perpendicular to a front surface of the semiconductor substrate; an insulating film(35) covering the through electrode(26B/42)[0034]; and at least one gate(24A) at the front surface of the semiconductor substrate, wherein the at least one gate(24A) is further disposed outside the outer periphery edge.
Hayasaki does not disclose a semiconductor device, comprising: a through electrode(26B/42)[0034] that penetrates a semiconductor substrate(10) along a direction perpendicular to a front surface and a back surface of the semiconductor substrate; an insulating film(35) covering the through electrode(26B/42)[0034] from the front surface to the back surface of the semiconductor substrate; and at least one dummy gate(24A) disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery edge and an outer periphery edge of the insulating film surrounding the through electrode at the front surface of the semiconductor substrate.
Akiyama-454 disclose a semiconductor device, comprising: a through electrode(45) that penetrates a semiconductor substrate(11) along a direction perpendicular to a front surface and a back surface of the semiconductor substrate; an insulating film(43) covering the through electrode from the front surface to the back surface of the semiconductor substrate; and at least one gate(left13a/right13a) disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery edge(inner periphery of 43) and an outer periphery edge(outer periphery of 43 of Akiyama-454) of the insulating film surrounding the through electrode(45) at the front surface of the semiconductor substrate, wherein the at least one gate(left13a/right13a) is further disposed outside the outer periphery edge.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama-454 to the teachings of Hayasaki in order to improve the packaging density of a semiconductor device [0005, Akiyama-454].
Hayasaki and Akiyama-454 do not disclose a dummy gate; and at least one dummy gate disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery edge(inner periphery of 43 of Akiyama-454) and an outer periphery edge(outer periphery of 43 Akiyama-454) of the insulating film surrounding the through electrode(45 of Akiyama-454) at the front surface of the semiconductor substrate.
Akiyama-849 disclose a dummy gate(212 of Akiyama-849)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama-849 to the teachings of Hayasaki in order to prevent an increase in electrical resistance at a connection [0004, Akiyama]. In doing so, at least one dummy gate(212 of Akiyama-849) disposed within an annular region defined at the front surface of the semiconductor substrate between an inner periphery edge(inner periphery of 43 of Akiyama-454) and an outer periphery edge(outer periphery of 43 Akiyama-454) of the insulating film surrounding the through electrode(45 of Akiyama-454) at the front surface of the semiconductor substrate.
Re claim 18 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 17, wherein the at least one dummy gate(212 of Akiyama-849) is not disposed inside the inner periphery edge.
Re claim 19 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 17, wherein an area ratio of the at least one dummy gate(212 of Akiyama-849) is not less than ten percent.
Re claim 20 Hayasaki, Akiyama-454 and Akiyama-849 disclose the semiconductor device according to claim 17, wherein a material of the at least one dummy gate(212 of Akiyama-849) is amorphous silicon.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15, 17-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights