DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 10/14/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hayasaki(USPGPUB DOCUMENT: 2010/0327383, hereinafter Hayasaki) in view of Akiyama (USPGPUB DOCUMENT: 2011/0024849, hereinafter Akiyama).
Re claim 1 Hayasaki discloses a semiconductor device, comprising: a through electrode(26B)[0034] that penetrates a semiconductor substrate(10) along a direction perpendicular to a predetermined front surface of the semiconductor substrate(10); an insulating film(35) covering the through electrode(26B)[0034]; and a wiring layer(29A/28A/26A/24A) that includes a gate(24A) disposed in a region between an outer periphery(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) and an inner periphery(portion of innermost 35) of the insulating film(35) on the front surface.
Hayasaki does not disclose a dummy gate
Akiyama disclose a dummy gate(212)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama to the teachings of Hayasaki in order to prevent an increase in electrical resistance at a connection [0004, Akiyama].
Re claim 2 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein the dummy gate(212 of Akiyama) is not disposed inside the inner periphery(portion of innermost 35).
Re claim 3 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein the dummy gate(212 of Akiyama) is further disposed outside the outer periphery(portion of 35 that extends from innermost 37 to outermost 35).
Re claim 4 Hayasaki and Akiyama disclose the semiconductor device according to claim 3, wherein the semiconductor substrate(10) includes an element isolation region(22A) formed under the wiring layer(29A/28A/26A/24A), andthe dummy gate(212 of Akiyama) is disposed on an upper portion of the element isolation region(22A).
Re claim 5 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein an area ratio[0037] of the dummy gate(212 of Akiyama) is not less than ten percent.
Re claim 6 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein a predetermined number of wirings are formed in the wiring layer(29A/28A/26A/24A), anda pitch of the wirings inside the outer periphery(portion of 35 that extends from innermost 37 to outermost 35) is substantially equal to a pitch of the wirings outside the outer periphery(portion of 35 that extends from innermost 37 to outermost 35).
Re claim 7 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein a gate electrode(51 of Akiyama) is further disposed in the wiring layer(29A/28A/26A/24A), anda material of the dummy gate(212 of Akiyama)[0032] is same as a material of the gate electrode(51 of Akiyama).
Re claim 8 Hayasaki and Akiyama disclose the semiconductor device according to claim 7, wherein the material of the dummy gate(212 of Akiyama)[0032] is any of polycrystalline silicon, amorphous silicon, tungsten, titanium, tantalum, and aluminum.
Re claim 9 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein a gate electrode(51 of Akiyama) is further disposed in the wiring layer(29A/28A/26A/24A), andthe material of the dummy gate(212 of Akiyama)[0032] is different from a material of the gate electrode(51 of Akiyama).
Re claim 10 Hayasaki and Akiyama disclose the semiconductor device according to claim 9, wherein a material of the dummy gate(212 of Akiyama)[0032] is silicon nitride.
Re claim 11 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein in the through electrode(26B)[0034], a cross-sectional area of an upper end on a front surface si e is smaller than a cross-sectional area of a lower end on a back surface side with respect to the front surface, andthe dummy gate(212 of Akiyama) is disposed between the outer periphery(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) covering the upper end of the front surface and the inner periphery(portion of innermost 35) of the insulating film(35) covering the upper end.
Re claim 12 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein in the through electrode(26B)[0034], a cross-sectional area of an upper end on a front surface side is larger than a cross-sectional area of a lower end on a back surface side with respect to the front surface, andthe dummy gate(212 of Akiyama) is disposed between the outer periphery(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) covering the lower end of the front surface and the inner periphery(portion of innermost 35) of the insulating film(35) covering the lower end.
Re claim 13 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein the semiconductor substrate(10) includes an element isolation region(22A) formed over an entire surface of a region between the outer periphery(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) and the inner periphery(portion of innermost 35) of the insulating film(35).
Re claim 14 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein the semiconductor substrate(10) includes an element isolation region(22A) formed in a part of a region between the outer periphery(portion of 35 that extends from innermost 37 to outermost 35) of the insulating film(35) and the inner periphery(portion of innermost 35) of the insulating film(35), and the dummy gate(212 of Akiyama) is disposed on an upper side of the element isolation region(22A).
Re claim 15 Hayasaki and Akiyama disclose the semiconductor device according to claim 1, wherein a gate electrode(51 of Akiyama) of a Fin field-effect transistor (Fin-FET) is further disposed in the wiring layer(29A/28A/26A/24A).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812