DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of invention I and species I in the reply filed on 20 January 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 5 and 11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim.
The 21 November 2025 restriction requirement is maintained and is now made final.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01 June 2023 and 02 June 2023 are in compliance with the provisions of 37 CFR 1.97 and have been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the contact electrode extending through the first and second semiconductor layers must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a contact electrode extending through the first and second semiconductor layers and directly connected to any one of the pair of main electrode regions of the first field effect transistor, the gate electrode of the second field effect transistor, and the charge holding region.”
The recitation can be interpreted in two ways.
The contact electrode is directly connected to
Any one of the pair of main electrode regions of the first field effect transistor,
The gate electrode of the second field effect transistor, and
The charge holding region.
The contact electrode is directly connected to any one of
The pair of main electrode regions of the first field effect transistor,
The gate electrode of the second field effect transistor, and
The charge holding region.
In the first interpretation, the contact electrode is directly connected to all three components, and in the second interpretation, the contact electrode is directly connected to one of the three components. Therefore, it is unclear and indefinite as to whether the contact electrode is directly connected to the three components or just one of the components. Further, if it’s the referring to the latter, it is unclear and indefinite as to how the contact electrode is connected to both the main electrode regions and still be a field effect transistor. For compact prosecution, it will be interpreted as the contact electrode is directly connected to one of the three components.
Claims 2-4 and 6-10 depend either directly or indirectly from independent claim 1, do not remedy the issues of claim 1 and therefore are also rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Togashi et al. (U.S. Pub. 2019/0057997).
Claim 1: Togashi et al. discloses a solid-state imaging device, in Fig. 11B, comprising:
a first semiconductor layer (72; paragraph 129);
a second semiconductor layer (71; paragraph 129) provided on a side of the first semiconductor layer (72) remote from a light incident surface (lower surface of 72);
a photoelectric conversion part (PD2; paragraph 129) provided in the first semiconductor layer (72);
a charge holding region (FD; paragraph 132) provided in the first semiconductor layer (72) and configured to accumulate a signal charge generated by photoelectric conversion performed by the photoelectric conversion part (PD-2); and
first and second field effect transistors (21 and 22, respectively; paragraph 129) each including a gate electrode (21G and 142, respectively; paragraphs 83 and 129) and a pair of main electrode regions (31 and 32, and 33 and 35, respectively; paragraphs 84 and 93), each of the pairs of main electrode regions being provided in the second semiconductor layer (71); and
a contact electrode (14; paragraph 129) extending through the first and second semiconductor layers (72 and 71, respectively) and directly connected to any one of the pair of main electrode regions of the first field effect transistor, the gate electrode of the second field effect transistor, and the charge holding region (contact electrode (14) is directly connected to the gate electrode (22G) of the second field effect transistor).
Claim 7: Togashi et al. discloses the solid-state imaging device according to claim 1 and, in Fig. 11B, further discloses a transfer transistor (74; paragraph 132) provided in the first semiconductor layer (72) and configured to transfer, to the charge holding region (FD), the signal charge generated by photoelectric conversion performed by the photoelectric conversion part (PD2) in order to send an electrical signal to the elements of the second semiconductor layer (paragraph 132).
Claim 8: Togashi et al. discloses the solid-state imaging device according to claim 1, and, in Fig. 11B, further discloses comprising
a readout circuit (21 and 22) including the first and second field effect transistors (21 and 22, respectively) and configured to read out the signal charge held in the charge holding region (FD) (paragraphs 129 and 132).
Claim 9: Togashi et al. discloses the solid-state imaging device according to claim 8, and, in Fig. 11B, further discloses wherein
the first field effect transistor (21) is a switching transistor or a reset transistor (paragraph 129), and
the second field effect transistor (22) is an amplification transistor (paragraph 129).
Claim 10: Togashi et al. discloses the solid-state imaging device according to claim 1, and, in Figs. 11A, and 11B further discloses wherein
a wiring (wire connecting VDD to 35; paragraph 85) of a wiring layer (wiring layer above 71) located above the second semiconductor layer (71) is not connected to the contact electrode (14).
Allowable Subject Matter
Claims 2-4 and 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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