Prosecution Insights
Last updated: April 19, 2026
Application No. 18/255,516

METALLIZATION OF SEMICONDUCTOR WAFER

Final Rejection §103
Filed
Jun 01, 2023
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Heraeus
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1105 granted / 1312 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
68 currently pending
Career history
1380
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1312 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 5, 7-9, 11, 13-14, 16, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kodas et al (US Publication No. 2003/0148024) in view of Noda (US Publication No. 2016/0222525) and DeGroot et al (US Publication No. 2015/0000720). Regarding claims 1 and 24, Kodas discloses a method for manufacturing a semiconductor wafer and a semiconductor wafer precursor comprising: i) applying a Metal-Organic ink to a semiconductor wafer ¶0312 and 0314, thereby forming a precursor layer ¶0018, 0350-0362; and, ii) curing the precursor layer ¶0240, wherein the application in step i) is carried out by inkjet printing ¶0350, and wherein the metal in the ink composition is Ag, Ag/Sn or Au ¶0350-0362. Kodas discloses all the limitations but silent on a MOD method and the specific deposition area in the wafer. Whereas Noda discloses a method for manufacturing a semiconductor wafer, comprising: i) applying a MOD ink composition to a semiconductor wafer ¶0056, thereby forming a precursor layer ¶0056,and,ii) curing the precursor layer ¶0056. DeGroot also discloses a method for manufacturing a semiconductor wafer which causes the backside of the semiconductor wafer to be metallized ¶0026, comprising: i) applying a Metal composition, wherein the application in step i) is carried out by inkiet printing ¶0026, and wherein the metal composition is Ag, Ag/Sn or Au ¶0022. Kodas, Noda and DeGroot are analogous art because they are directed to application of metallization layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kodas because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Kodas and incorporate the teachings of Noda and DeGroot as an alternative method of deposition known in the art and also to provide another location for metallic connection for a TFT or solar applications as described in Kodas. Regarding claim 3, Noda discloses wherein a cycle comprising steps i) and ii) is carried out for one or more times, and in each cycle, step i) is performed one or more times and step ii) is carried out for one or more times ¶0056. Regarding claim 5, Noda discloses wherein the curing in step ii) is carried out by electromagnetic radiation and/or heating¶0056. Regarding claim 7, Noda discloses wherein the heating temperature is from 50°C to 500°C, preferably from 80°C to 400°C, more preferably from about 150°C to 300°C¶0056. Regarding claim 8, Noda discloses: iii) annealing the layer obtained after curing¶0056. Regarding claim 9, Kudos discloses wherein the annealing in step iii) is carried out at a temperature of from 120°C to 500°C ¶0061. Regarding claim 11, Noda discloses wherein the semiconductor wafer is a Si wafer, a SiC wafer, a GaN wafer, a GaAs wafer, or a Ga203 wafer, preferably a Si wafer ¶0034. Regarding claim 13, Noda discloses wherein the MOD ink composition comprises: a) at least one metal precursor; and b) a solvent ¶0039-0040, 0056. Regarding claim 14, Kudos discloses wherein the metal precursor has a decomposition temperature of from 80°C to 5000C ¶0353. Regarding claim 16, Kudos discloses wherein the metal precursor consists of:a) at least one metal cation; and,b) at least one anion selected from the group consisting of carboxylate, carbamate, nitrate, halide ion and oxime ¶0078. Claims 4, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kodas et al (US Publication No. 2003/0148024) in view of Noda (US Publication No. 2016/0222525) and DeGroot et al (US Publication No. 2015/0000720)and in further view of Kirihara et al (US Publication No. 2014/0230876). Regarding claim 4, Kodas and Noda disclose all the limitations except for the thickness. Whereas Kirihara discloses wherein in the case of carrying out a plurality of cycles, a layer with a thickness of from 100 nm to 800 nm, preferably from 150 nm to 500 nm, more preferably from 200 nm to 300 nm is formed in each cycle ¶0087-0088. Noda and Kirihara are analogous art because they are directed to metallization layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kodas/Noda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Noda and incorporate the teachings of Kirihara to achieve the desired thickness. Regarding claim 12, Kirihara discloses wherein the semiconductor wafer is a power electronic wafer or a logic IC wafer ¶0200. Regarding claim 20, Kirihara discloses the MOD ink composition is a bismuth-containing MOD ink composition ¶0086-0087. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kodas et al (US Publication No. 2003/0148024) in view of Noda (US Publication No. 2016/0222525) and DeGroot et al (US Publication No. 2015/0000720)and in further view of Rupp et al (US Publication No. 2008/0258183). Regarding claim 6, Kudas discloses all the limitations except for the curing type. Whereas Rupp discloses wherein the radiation intensity is from 100 W/cm2 to 1000 W/cm2, preferably from 100 W/cm2 to 500 W/cm2, more preferably from 100 W/cm2 to 400 W/cm2, and the radiation wavelength is from 100 nm to 1 mm, preferably from 100 nm to 2000 nm, more preferably from 100 nm to 800 nm ¶0038-0046. Noda and Rupp are analogous art because they are directed to metallization layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the curing method of Kudas and incorporate the teachings of Rupp as an alternative method known in the art as a matter of design choice. Claims 17-19, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kodas et al (US Publication No. 2003/0148024) in view of Noda (US Publication No. 2016/0222525) and DeGroot et al (US Publication No. 2015/0000720)view of Huang et al (US Publication No. 2009/0233800). Regarding claim 17, Huang discloses wherein the method further comprises the steps carried out prior to step i) o 1) forming an adhesion layer and a barrier layer on the semiconductor wafer; or 2) forming a layer having both adhesion and barrier functions on the semiconductor wafer ¶0008 Fig 1. Noda and Huang are analogous art because they are directed to metallization layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noda because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Noda and incorporate additional layers to improve layer protection and bonding. Regarding claim 18, Huang discloses wherein the formation of the layers in steps 1) and 2) is carried out by chemical vapor deposition, sputter deposition, electroplating, spraying, spin coating, dip coating or inkjet printing, preferably by inkjet printing ¶0111-0113, 0119-0127. Regarding claim 19, Huang discloses, wherein when the formation of the layer is carried out by spraying, spin coating, dip coating or inkjet printing, the ink used is a MOD ink composition¶0111-0113, 0119-0127. Regarding claim 21, Noda discloses wherein after each layer of step 1) or 2) is formed, the resultant wafer is cured and/or annealed ¶0056. Regarding claims 22 and 23, Noda discloses a semiconductor device comprising the semiconductor wafer according to claim 21. Response to Arguments Applicant’s arguments with respect to claims 1, 3-9, 11-14, 16-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Jun 01, 2023
Application Filed
Aug 04, 2025
Non-Final Rejection — §103
Oct 31, 2025
Response Filed
Feb 11, 2026
Final Rejection — §103
Apr 08, 2026
Response after Non-Final Action

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.1%)
2y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 1312 resolved cases by this examiner. Grant probability derived from career allow rate.

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