DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/26/2026 has been entered.
Response to Amendment
The Amendment filed on 06/26/2026 has been entered. Applicant's amendment have overcome
the 112 rejections previously set forth in the Final Office Action dated on 04/28/2026. Claim 2 is canceled. Claim 19 is new. Claims 1, 3-19 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Final Reject" filed on 06/26/2026, have been fully considered, the Applicant’s arguments related to “Endo does not describe that the combination of the first wiring layer 122 and the second wiring layer 123 of the first chip 101 connects the well region 124 of the second chip with the drain region 113 of the first chip”. These arguments are not persuasive because Endo (US 20180114808 A1) describes the first wiring layer 122 and the second wiring 123 are connected to the second wiring 129 to electrically connect the region 113 with the well 124 of the transistor having the gate electrode 126 in [0032,0034], Fig. 3, see the detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3, 12-14 and 16-19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim (US 20090166694 A1, hereinafter Kim, of the record) in view of Endo et al. (US 20180114808 A1, hereinafter Endo, of the record).
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Re: Independent Claim 1, Kim discloses an imaging element (Fig. 9), comprising:
Kim’s Figure 9-Annotated.
a first substrate (first substrate a polycrystalline silicon layer in [0047-0048], Figs. 3,9-Annotated) including a first semiconductor substrate (a portion of the first substrate wherein the photodiode 40 is formed and patterned into 45, 45a in [0047-0048], Figs. 3,9-Annotated) wherein
the first semiconductor substrate includes (a portion of the first substrate) a photoelectric conversion section (45, 45a first and second photodiode patterns in [0048], Fig. 9), wherein
the photoelectric conversion section is configured to perform photoelectric conversion of incident light to generate a charge ([0061]); and
a second substrate (second substrate-100-160 including a semiconductor layer 100 and an insulating layer 160 in [0018], Figs. 9-Annotated,10) including a second semiconductor substrate (100 a semiconductor layer 100 in [0018], Figs. 9-Annotated, 10) that includes:
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a pixel circuit (120, 120a first and second readout circuitries in [0018,0070], Figs. 9,10) configured to generate an image signal based on the charge generated by the photoelectric conversion (45, 45a);
Kim’s Figure 10-Annotated.
an element isolating region (160 an insulating layer in [0018], Figs. 9,10) that isolates elements of the pixel circuit (120, 120a); and
a high impurity concentration region (148 an N+ connection region in [0074], Fig. 10) below the element isolating region (160), wherein
the high impurity concentration region is connected to the first semiconductor substrate (a portion of the first substrate) to use a first reference potential in common (pinning voltage in [0035], Fig. 10), with the first semiconductor substrate (a portion of the first substrate),
the first semiconductor substrate is on a back surface side of the second semiconductor substrate (second substrate 100, 160).
Kim does not expressly disclose a first substrate including a first connecting location, the first semiconductor substrate includes a first semiconductor region, and the first connecting location of the first substrate connects the high impurity concentration region of the second semiconductor substrate with the first semiconductor region of the first semiconductor substrate.
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Endo’s Figure 3-Annotated.
However, in the same semiconductor device field of endeavor, Endo discloses a first substrate (101 first chip in [0050], Fig.3) including a first connecting location (122-123 a first wiring layer 122 and a second wiring layer 123 in [0032], Fig.3-Annotated) and a first semiconductor substrate (104 in [0032], Fig.3) includes a first semiconductor region (113 a drain region as a semiconductor region in [0035], Fig.3), and the first connecting location (122-123) of the first semiconductor substrate (101, Fig.3) connects (122-123 are connected to 129 to electrically connect 113 with 124 of the transistor having the gate electrode 126 in [0032,0034], Fig. 3) the impurity concentration region (124 P-type semiconductor region in [0036], Fig.3) of the second semiconductor substrate (108 in [0036], Fig.3) with the first semiconductor region (113) of the first semiconductor substrate (104, Fig.3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Endo’s feature of a first substrate including a first connecting location, the first semiconductor substrate includes a first semiconductor region, and the first connecting location of the first substrate connects the impurity concentration region of the second semiconductor substrate with the first semiconductor region of the first semiconductor substrate to Kim’s device to obtain a first substrate including a first connecting location, the first semiconductor substrate includes a first semiconductor region, and the first connecting location of the first substrate connects the high impurity concentration region of the second semiconductor substrate with the first semiconductor region of the first semiconductor substrate to further suppress generation of leakage current causing a white defect (of an image) or a dark current to be produced when the high-melting metal is mixed into the semiconductor region ([0050], Endo).
Re: Claim 3, Kim modified by Endo discloses the imaging element according to claim 1, wherein the high impurity concentration region (148, Kim) is in a well region (141 a P-well region in [0035], Fig. 10, Kim) of the second semiconductor substrate (second substrate 100, 160, Kim), and the first connecting location (122-123 from Endo applied to Kim) connects (all elements are electrically connected) the high impurity concentration region (148, Kim) and the well region (141, Kim) of the first semiconductor substrate (first substrate, Kim) to each other (Fig. 10, Kim).
Re: Claim 12, Kim modified by Endo discloses the imaging element according to claim 1, wherein the first semiconductor substrate (first substrate, Kim) further includes: a charge holding section (131 floating diffusion region in [0032,0034], Fig. 10, Kim) configured to hold the charge generated by the photoelectric conversion ([0034], Fig. 10, Kim); and a charge transfer section (140 PNP junction region, when the transfer transistor 121 is turned on, the electrons in 140 are transferred to 131 in [0034], Fig. 10, Kim) configured to transfer the charge from the photoelectric conversion section (45, 45a, Kim) to the charge holding section (131, Kim), and the pixel circuit (120, 120a, Kim) is configured to generate the image signal based on the held charge (the photo charges generated in the photodiode can be dumped or transferred into the floating diffusion region, thereby enhancing the sensitivity of the image sensor (and output images thereof) in [0030], Kim).
Re: claim 13, Kim modified by Endo discloses the imaging element according to claim 1,
further comprising a second semiconductor region (133 source/drain region in [0028], Fig. 10, Kim) in a layer (Fig. 10, Kim) of the second semiconductor substrate (second substrate 100, 160, Kim).
Re: Claim 14, Kim modified by Endo discloses the imaging element according to claim 13, wherein a second reference potential different from the first reference potential is supplied (a maximum voltage value of the FD 131 connected to 133, includes a Vdd minus the threshold voltage (Vth) of the reset transistor (Rx) in [0035], Kim) to the second semiconductor region (133, Kim).
Re: Claim 16, Kim modified by Endo discloses the imaging element according to claim 13,
Kim modified by Endo does not expressly disclose wherein the pixel circuit in the second semiconductor substrate comprises a transistor, and the transistor is configured to amplify a signal, based on the charge generated by the photoelectric conversion.
However, in the same semiconductor device field of endeavor, Endo discloses wherein the pixel circuit (402 circuit in [0053], Fig. 4B) in the second semiconductor substrate (402 and 111 circuit in [0053], Fig. 4B) comprises a transistor (126 gate electrode 126 of an amplification transistor 126 in [0034], Fig. 4B), and the transistor (126) is configured to amplify a signal (a signal received from 115-112 is amplified by 126 transistor [0034], Fig. 3), based on the charge generated by the photoelectric conversion (115-112 in [0035], Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Endo’s feature of wherein the pixel circuit in the second semiconductor substrate comprises a transistor, and the transistor is configured to amplify a signal, based on the charge generated by the photoelectric conversion to Kim’s device to further suppress generation of leakage current causing a white defect (of an image) or a dark current to be produced when the high-melting metal is mixed into the semiconductor region ([0050], Endo).
Re: Claim 17, Kim modified by Endo discloses the imaging element according to claim 13, further comprising a transistor (123, 125 reset transistor 123 and drive transistor 125 in [0028], Fig. 10, Kim) configured to control output of the image signal generated by the pixel circuit (123 as part of the readout circuitry 120 in [0028], Kim), and the second semiconductor region (133, Kim) includes the transistor (123, 125, Kim).
Re: Independent Claim 18, Kim discloses an imaging device (Fig. 9), comprising:
a first substrate (first substrate a polycrystalline silicon layer in [0047-0048], Figs. 3,9-Annotated) including a first semiconductor substrate (a portion of the first substrate wherein the photodiode 40 is formed and patterned into 45, 45a in [0047-0048], Figs. 3,9-Annotated) wherein
the first semiconductor substrate includes (a portion of the first substrate) a photoelectric conversion section (45, 45a first and second photodiode patterns in [0048], Fig. 9), wherein
the photoelectric conversion section is configured to perform photoelectric conversion of incident light to generate a charge ([0061]); and
a second substrate (second substrate-100-160 including a semiconductor layer 100 and an insulating layer 160 in [0018], Figs. 9-Annotated,10) including a second semiconductor substrate (100 a semiconductor layer 100 in [0018], Figs. 9-Annotated,10) that includes:
a pixel circuit (120, 120a first and second readout circuitries in [0018,0070], Figs. 9,10) configured to generate an image signal based on the charge generated by the photoelectric conversion (45, 45a);
an element isolating region (160 an insulating layer in [0018], Figs. 9,10) that isolates elements of the pixel circuit (120, 120a); and
a high impurity concentration region (148 an N+ connection region in [0074], Fig. 10) below the element isolating region (160), wherein
the high impurity concentration region is connected to the first semiconductor substrate (a portion of the first substrate) to use a first reference potential in common (pinning voltage in [0035], Fig. 10), with the first semiconductor substrate (a portion of the first substrate),
the first semiconductor substrate is on a back surface side of the second semiconductor substrate (second substrate 100, 160); and
a processing circuit (120, 120a) configured to process (120, 120a first and second readout circuitries in [0018,0070], Figs. 9,10) the generated image signal.
Kim does not expressly disclose a first substrate including a first connecting location, the first semiconductor substrate includes a first semiconductor region, and the first connecting location of the first substrate connects the high impurity concentration region of the second semiconductor substrate with the first semiconductor region of the first semiconductor substrate.
However, in the same semiconductor device field of endeavor, Endo discloses a first substrate (101 first chip in [0050], Fig.3) including a first connecting location (122-123 a first wiring layer 122 and a second wiring layer 123 in [0032], Fig.3-Annotated) and a first semiconductor substrate (104 in [0032], Fig.3) includes a first semiconductor region (113 a drain region as a semiconductor region in [0035], Fig.3), and the first connecting location (122-123) of the first semiconductor substrate (101, Fig.3) connects (122-123 are connected to 129 to electrically connect 113 with 124 of the transistor having the gate electrode 126 in [0032,0034], Fig. 3) the impurity concentration region (124 P-type semiconductor region in [0036], Fig.3) of the second semiconductor substrate (108 in [0036], Fig.3) with the first semiconductor region (113) of the first semiconductor substrate (104, Fig.3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Endo’s feature of a first substrate including a first connecting location, the first semiconductor substrate includes a first semiconductor region, and the first connecting location of the first substrate connects the impurity concentration region of the second semiconductor substrate with the first semiconductor region of the first semiconductor substrate to Kim’s device to obtain a first substrate including a first connecting location, the first semiconductor substrate includes a first semiconductor region, and the first connecting location of the first substrate connects the high impurity concentration region of the second semiconductor substrate with the first semiconductor region of the first semiconductor substrate to further suppress generation of leakage current causing a white defect (of an image) or a dark current to be produced when the high-melting metal is mixed into the semiconductor region ([0050], Endo).
Re: Claim 19, Kim modified by Endo discloses the imaging element according to claim 1,
Kim modified by Endo does not expressly disclose wherein the high impurity concentration region of the second semiconductor substrate is at a bottom portion of the element isolating region, and the element isolating region is groove shaped.
However, in the same semiconductor device field of endeavor, Endo discloses wherein the impurity concentration region (124 P-type semiconductor region in [0036], Fig.3) of the second semiconductor substrate (108 in [0036], Fig.3) is at a bottom portion of the element isolating region (127 element isolation region in [0036], Fig.3), and the element isolating region (127) is groove (127 has a groove around 124 in Fig. 3) shaped.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Endo’s feature of wherein the impurity concentration region of the second semiconductor substrate is at a bottom portion of the element isolating region, and the element isolating region is groove shaped to Kim’s device to obtain wherein the high impurity concentration region of the second semiconductor substrate is at a bottom portion of the element isolating region, and the element isolating region is groove shaped to further suppress generation of leakage current causing a white defect (of an image) or a dark current to be produced when the high-melting metal is mixed into the semiconductor region ([0050], Endo).
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Endo, and further in view of Choi (US 20190348433 A1, hereinafter Choi, of the record).
Re: claim 4, Kim modified by Endo discloses the imaging element according to claim 1,
Kim modified by Endo does not expressly disclose wherein the first connecting location comprises silicon.
However, in the same semiconductor device field of endeavor, Choi discloses wherein a connecting location (WCL a well contact structure in [0047], Fig. 1) comprises silicon (WCL made of silicon in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Choi’s feature wherein the first connecting location comprises silicon to the combination of Kim and Endo for contacting with the well structure, WE and extends toward the source contact structure SCL ([0047], Choi).
Claim(s) 5-7 and 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Endo and further in view of Ishii et al. (US 20180301509 A1, hereinafter Ishii, of the record).
Re: Claim 5, Kim modified by Endo discloses the imaging element according to claim 1, further comprising a second connecting location (151a metal line in [0039], Fig. 10, Kim), wherein the second connecting location supplies the first reference potential (a maximum voltage value of the P0/N-/P- junction 140 becomes the pinning voltage in [0035], Fig. 10, Kim).
Kim modified by Endo does not expressly disclose wherein the second connecting location that is on a front surface side of the second semiconductor substrate.
However, in the same semiconductor device field of endeavor, Ishii discloses a second connecting location (CL-BCP4 contact plug BCP4 that penetrates the lower insulating layer 211 and connection line CL, both connected to FD in [0031,0049], Fig. 2A) that is on a front surface side of the second semiconductor substrate (100-211 in [0031,0049], Fig. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the Kim’s second connection having the features of Ishii’s connection wherein the second connecting location that is on a front surface side of the second semiconductor substrate to electrically coupled the photoelectric conversion element to a charge storage node FD of the readout circuit through the connection lines ICL and CL ([0031], Ishii).
Re: Claim 6, Kim modified by Endo and Ishii discloses the imaging element according to claim 5, wherein the second connecting location (151a’s Kim modified by Ishii) is in the element isolating region (160’s Kim), and the second connecting location is connected to the high impurity concentration region (148’s Kim).
Re: Claim 7, Kim modified by Endo and Ishii discloses the imaging element according to claim 5, wherein the second connecting location (151a’s Kim modified by Ishii) is adjacent to the element isolating region (160’s Kim).
Re: Claim 9, Kim modified by Endo and Ishii discloses the imaging element according to claim 5, wherein the second connecting location (151a’s Kim modified by Ishii) comprises a metal (151a is a metal contact in [0039], Fig. 10, Kim).
Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Endo, in view of Ishii and further in view of Fan (US 20140320718 A1, hereinafter Fan, of the record).
Re: Claim 8, Kim modified by Endo and Ishii discloses the imaging element according to claim 5,
Kim modified by Endo and Ishii does not expressly disclose further comprising a third semiconductor substrate on the front surface side of the second semiconductor substrate, wherein the third semiconductor substrate is connected to the second connecting location.
However, in the same semiconductor device field of endeavor, Fan discloses a third semiconductor substrate (logic board 173 in [0169], Fig. 21A-E) on the front surface side of the second semiconductor substrate (transistor array 172 in [0169], Fig. 21A-E), wherein the third semiconductor substrate (logic board 173) is connected to the second connecting location (TSVs 354 in [0188], Fig. 21A-E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Fan’s feature of a third semiconductor substrate on the front surface side of the second semiconductor substrate, wherein the third semiconductor substrate is connected to the second connecting location to the combination of Kim, Endo and Ishii to increase the resolution of the image sensor ([0006], Fan).
Claim(s) 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Endo, in view of Ishii and further in view of Choi.
Re: claim 10, Kim modified by Endo and Ishii discloses the imaging element according to claim 5,
Kim modified by Endo and Ishii does not expressly disclose wherein the second connecting location comprises silicon.
However, in the same semiconductor device field of endeavor, Choi discloses wherein a connecting location (WCL a well contact structure in [0047], Fig. 1) comprises silicon (WCL made of silicon in [0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Choi’s feature wherein the second connecting location comprises silicon to the combination of Kim, Endo and Ishii device for contacting with the well structure, WE and extends toward the source contact structure SCL ([0047], Choi).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Endo, in view of Fan (US 20140320718 A1, hereinafter Fan, of the record).
Re: Claim 11, Kim modified by Endo discloses the imaging element according to claim 1,
Kim modified by Endo does not expressly disclose wherein the high impurity concentration region has an impurity concentration of 5x1017cm-3 or more.
However, in the same semiconductor device field of endeavor, Fan discloses wherein the high impurity concentration region (670 a first shallow doped region 670 may be formed at the source of the trigger transfer gate 658 in [0218], Fig. 25B) has an impurity concentration of 5x1017cm-3 or more (1018cm-3 in [0218]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Fan’s feature wherein the high impurity concentration region has an impurity concentration of 5x1017cm-3 or more to the combination of Kim and Endo to allow an ohmic contact between the photodiode and transistor array chips, while still providing a substantially complete charge transfer ([0218], Fan).
Claim(s) 15 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim in view of Endo, and further in view of Hsu (US 10886320 B2, hereinafter Hsu, of the record).
Re: Claim 15, Kim modified by Endo discloses the imaging element according to claim 14, wherein the high impurity concentration region (148, Kim) in a first well region (141p-well, Kim) of the second semiconductor substrate (second substrate-100-160, Kim),
Kim modified by Endo does not expressly disclose wherein the second semiconductor region is configured in a second well region having a conductivity type different from a conductivity type of the first well region of the second semiconductor substrate.
However, in the same semiconductor device field of endeavor, Hsu discloses wherein the second semiconductor region (source/drain regions 122B in Col. 4, lines 5-8, Fig. 2) is configured in a second well region (n-type well 122C in Col. 4, lines 5-8, Fig. 2) having a conductivity type different from a conductivity type of the first well region of the second semiconductor substrate (substrate 104 doped with a p-type dopant in Col. 3, lines 16-17, Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hsu’s feature wherein the second semiconductor region is configured in a second well region having a conductivity type different from a conductivity type of the first well region of the second semiconductor substrate to the combination of Kim and Endo to provide an operational environment for the pixel region (Col. 4, lines 1-3, Hsu).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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