Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in FEDERAL REPUBLIC OF GERMANY on 02/03/2021.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/07/2023 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2, 13, and 15-16 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, the following sets of limitations are interpreted to include a broad range/limitation with a narrow range/limitation in the same claim:
Claim 2 recites the broad recitation “the incidence area has a rectangular . . . shape in top view”, and the claim also recites “the incidence area has . . . in particular a square shape in top view” which is a narrower statement of the range/limitation in the same claim. A rectangular shape encompasses both the narrower square shape (four right angles and four equal straight sides) in addition to a broader rectangular shape (four right angles and four straight sides).
Claim 13 recites the broad recitation “The photodiode device according to claim 1”, and the claim also recites “further comprising an array of incidence areas as described in any of the preceding claims” which a the narrower statement of the range/limitation in the same claim. Each dependent claim (2-12) depends on claim 1 such that references to “any of the preceding claims” are necessarily narrower than the broader requirement of solely depending on claim 1.
Claim 16 recites the broad recitation “the optoelectronic system is provided for detection of electromagnetic radiation”, and the claim also recites “in particular ambient light detection” which is a narrower statement of the range/limitation in the same claim. Electromagnetic radiation encompasses both the narrower ambient light range in addition to the broader wavelengths which exist outside of ambient light wavelengths.
Claim(s) 2, 13, and 16 are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. For the purposes of this examination, any disclosure which includes a feature falling withing the range of the broader limitation(s) will be interpreted to read on the claim(s).
The term “high” in claim 15 is a relative term which renders the claim indefinite. The term “high” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, the limitation of “image grade epi starting material for high charge carrier lifetime” is indefinite as one of ordinary skill in the art has not been reasonably apprised of what range of lifetimes may constitute a high charge carrier lifetime. Claim 15 is therefore considered indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For the purposes of this examination, any disclosure which includes an epitaxial material used in an imaging device will be interpreted to read on the claim as producing a high charge carrier lifetime.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 8-12, and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2010/0065939 A1; Bui et al.; 03/2010; (“Bui”).
Regarding Claim 1. Bui discloses A photodiode device (#200, Figure 2, photodiode where Figure 3C is an example cross-sectional view ([0065]) and Figures 4A-4I and 5A-5E detail the manufacturing process ([0066]-[0079])), comprising:
a semiconductor substrate (#335 and #305, Figure 3C, mechanical support and thin active layer) with a main surface (Figure 3C, top surface of #305), the semiconductor substrate being of a first type of electric conductivity ([0120], #335 is n+ type and [0123], thin active layer is n-type), wherein the main surface comprises an incidence area for electromagnetic radiation (Figure 2, let any of the 7 areas surrounded on all four sides by #205 be an incidence area),
a plurality of doped wells of a second type of electric conductivity (#310, Figure 3C, p+ fishbones) at the main surface of the substrate (Figure 3C, #310s are at the top surface of #305), the second type of electric conductivity being opposite to the first type of electric conductivity (p-type fishbones are the opposite of the n-type substrate),
wherein the doped wells and the substrate are electrically contactable ([0052], p+ fishbones all include metal contact bars, i.e. they are electrically contactable; [0143] and Figure 4I, the substrate is contacted by metal layer #447 and metal contacts #446), and
wherein at least some of the doped wells being electrically connected with each other in parallel (Figure 2, several of the p+ bones #205 are electrically connected with each other in parallel), and
wherein the incidence area forms a pixel within an array of pixels of the photodiode device (Figure 2, let each of the 7 incidence areas be a pixel within an array of at least 7 pixels of the device) and the doped wells are arranged along a perimeter of the incidence area (Figure 2, p+ bones are arranged along the perimeter of each of the 7 incidence areas), such that a center region of the incidence area is free from the doped wells (Figure 3C, a center region of the incidence area between adjacent fishbones is free from the fishbones).
Regarding Claim 2. Bui discloses The photodiode device according to the claim 1, wherein the incidence area has a rectangular, in particular square shape in top-view (Figure 2, each of the 7 incidence areas has a rectangular shape in the top-view), such that the doped wells form a frame surrounding the center region of the incidence area (Figure 2, p+ fishbones form a frame surrounding the center region of the 7 incidence areas) .
Regarding Claim 4. Bui discloses The photodiode device according to claim 1,wherein the center region accounts for at least 40%, at least 60% or at least 80% of the incidence area (Figure 2, the center region free of the p+ bones encompasses 100% of the incidence area of the respective pixel).
Regarding Claim 8. Bui discloses The photodiode device according to claim 1, further comprising a dielectric surface passivation layer (#342, not numbered in Figure 3C but numbered in Figure 3A, AR layer comprising dielectric material silicon nitride according to [0119]) arranged on or above the center region of the incidence area (Figure 3C, #342 is above the center region of the incidence area), wherein the dielectric surface passivation layer is provided for repelling charge carriers and/or for use as anti-reflective coating ([0118], #342 is an anti-reflective layer).
Regarding Claim 9. Bui discloses The photodiode device according to the claim 8, further comprising an oxide film (#341, not numbered in Figure 3C but numbered in Figure 3A, AR layer comprising silicon oxide according to [0119]) arranged on the center region of the incidence area between the main surface and the dielectric surface passivation layer (Figure 3C, #341 is on the center region of the incidence area between the top surface of #305 and #342).
Regarding Claim 10. Bui discloses The photodiode device according to claim 8, wherein the dielectric surface passivation layer comprises positive space charges or negative space charges ([0119], #342 is a silicon nitride layer, page 12 of the instant application states that “the dielectric surface passivation layer comprises at least one of stoichiometric SiN or non-stoichiometric silicon nitride. With these materials positive space charges can be formed in the dielectric surface passivation layer”, i.e. #342 is interpreted to comprise positive space charges as a silicon nitride layer).
Regarding Claim 11. Bui discloses The photodiode device according to claim 1, further comprising
an intermetal dielectric (#440, Figure 4F and #425, Figure 4C, both of which are present, but not numbered, in the final structure Figure 4I, thick oxide layer (#440) and oxide layer (#425)) arranged on or above the main surface of the substrate (Figure 4I, #440 and #425 are arranged on and above the top surface of the thin active layer #405),
at least one conductor track (#446 left, Figure 4I, metal contact) embedded in the intermetal dielectric (Figure 4I, #446 left is at least partially embedded in #425) and electrically connected to the doped wells (Figure 4I, #446 left is electrically connected to the p+ bones (#430 in Figure 4E) through the thin active layer #405), and
at least one further conductor track (#446 right, Figure 4I, metal contact) embedded in the intermetal dielectric (Figure 4I, #446 right is at least partially embedded in #425) and electrically connected to the substrate (Figure 4I, #446 right is electrically connected to the substrate through direct contact),
wherein a region in the intermetal dielectric covering the center region of the incidence area is free from conductor tracks and/or further conductor tracks (Figures 3C and 4I, portions of the thick oxide layer (#440 in Figure 4I and #315 in Figure 3C) over the center region of the incidence area are free from any conductor tracks).
Regarding Claim 12. Bui discloses The photodiode device according to claim 11, further comprising a metal layer ([0138], “dual anti-reflective (AR) layers 441 and 442 are grown on the front side of thin active layer 405 and silicon substrate 410 . . . the dual layer anti-reflective coating design adopted herein utilizes a combination of thin film materials, such as . . . metals” i.e. #441 and #442 in Figure 4G may comprise a metal layer) embedded in the intermetal dielectric, such that the metal layer covers the doped wells (Figure 3C, the AR layers #341 and #342 are at least partially embedded in the thick oxide layers such that they cover the p+ bones).
Regarding Claim 14. Bui discloses The photodiode device according to claim 1,wherein the center region of the incidence area is free from a pn-junction (Figure 3C, the center region of the incidence areas are free from a pn-junction in the vertical directions as all layers are n-type).
Regarding Claim 15. Bui discloses The photodiode device according to claim 1, wherein the semiconductor substrate comprises an image grade epi starting material for high charge carrier lifetime ([0123], the thin active layer is an epi layer that is being used here in a device which may be used for imaging purposes (see [0008]), i.e. the thin active layer is an image grade epi starting material for high charge carrier lifetime in accordance with the 35 U.S.C. 112(b) rejection of claim 15 above).
Regarding Claim 16. Bui discloses An optoelectronic system comprising the photodiode device according to claim 1, wherein the optoelectronic system is provided for detection of electromagnetic radiation, in particular ambient light detection ([0009], the related photodiode arrays detailed in the reference may be used to detect electromagnetic radiation).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0065939 A1; Bui et al.; 03/2010; (“Bui”).
Regarding Claim 5. Bui discloses The photodiode device according to claim 1.
Bui does not disclose, as part of the identified embodiment, that the center region of the incidence area comprises a doped surface region of the first type of electric conductivity.
However, Bui does teach, in a different embodiment of Figures 9A-9B, a photodiode device (#900, Figures 9A-9B, photodiode array) wherein the center region of the incidence area (Figures 9A and 9B, 7 incidence areas as in the previous embedment) comprises a doped surface region of the first type of electric conductivity (#950, Figure 9A, shallow n+ layer).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the two embodiments disclosed adjacent to each other in the prior art reference, Bui, as doing so does not require a leap of inventiveness, Boston Scientific v. Cordis (Fed. Cir. 2009). Incorporating the feature of a shallow n+ layer (#950) from the embodiment of Figure 9A into the embodiment of Figure 3C would reduce the portion of photo-generated minority carriers which would otherwise recombine at the silicon/silicon dioxide interface and reduce the charge collection efficiency of device as taught by Bui in [0159].
Regarding Claim 6. Bui discloses The photodiode device according to claim 5, wherein in lateral directions, which run parallel to a main plane of extension of the substrate, there is a spacing between the doped wells and the doped surface region (Figure 9A, in lateral left and right directions which run parallel to a main upper plane of extension of the substrate (#905 and #935) there is a spacing between the p+ fishbones (#910) and the doped surface region (#950)).
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0065939 A1; Bui et al.; 03/2010; (“Bui”) as applied to claim 1 above, and further in view of US 2002/0140045 A1; Lauter et al.; 10/2002; (“Lauter”).
Regarding Claim 3. Bui discloses The photodiode device according to claim 1.
Bui does not disclose that each side of the incidence area has a length, the length being between 40 µm and 120 µm or between 60 µm and 100 µm.
However, Lauter teaches a photodiode (Figures 1 and 2, light sensitive semiconductor component) comprising a plurality of incidence areas (Figures 1 and 2, regions exposed to incident light (λ) bounded by four #7s in a rhombus shape) comprising a stack of first electrical conductivity type layers (#5, #9, and #10, Figure 2, p+ doped layer, p-epi channel region, and p-substrate) surrounded by doped wells of a second conductivity type (#7, Figure 2, n+ type dot zones) wherein each side of the incidence area has a length (Figure 2, distance between four respective dots in the rhombus shape), the length being between 40 µm and 120 µm or between 60 µm and 100 µm ([0019] and [0035], the length is between 10% and 200% of the diffusion length of the carriers which is identified as being on the order of 100 µm, i.e. length may be 100 µm). Lauter further teaches that the distance between doped dot regions requires optimization to smaller values to ensure maximum generated particle collection ([0003] and [0019], high yield of particles can reach the dot zones before recombination due to diffusion length) and optimization to larger values to maximize light exposure area ([0005], larger areas increase the number of collected photons to correspondingly increase the number of charge carriers).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the incidence area to have side lengths close to the diffusion length of 100 µm, within the claimed range of 40 µm to 120 µm, in Bui as a routine optimization (see MPEP 2144.05.II.A) based on the information provided by Lauter.
Regarding Claim 13. Bui discloses The photodiode device according to claim 1, further comprising an array of incidence areas as described in any of the preceding claims (Figure 2, let each of the 7 incidence areas be considered a pixel, as described in claim 1, within an array of at least 7 pixels of the device).
Bui does not disclose at least one trench or at least one guard ring is arranged in the substrate surrounding each incidence area in lateral directions, the trench or the guard ring being provided to prevent crosstalk between neighboring incidence areas.
However, Lauter teaches a photodiode (Figures 1 and 2, light sensitive semiconductor component) comprising an incidence areas (Figures 1 and 2, regions exposed to incident light λ) comprising a stack of first electrical conductivity type layers (#5, #9, and #10, Figure 2, p+ doped layer, p-epi channel region, and p-substrate) surrounded by doped wells of a second conductivity type (#7, Figure 2, n+ type dot zones), wherein at least one trench or at least one guard ring (#3, Figure 1, guard ring) is arranged in the substrate surrounding each incidence area in lateral directions (Figure 1, #3 is arranged in the substrate surrounding the incidence area in lateral directions), the trench or the guard ring being provided to prevent crosstalk between neighboring incidence areas ([0029], “a counter voltage may be applied to the guard ring 3 during operation so as to provide active support for the barrier function . . . The guard ring thus provides suppression of crosstalk (blur) and hence a strict separation of the pixels”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the guard ring of Lauter to surround the incidence areas in Bui as the guard ring “prevents charge carriers that are generated on the pixel surface by the incidence of light from leaving the area of the pixel by diffusion, thus allowing these charge carriers to be diffused into the region of a neighboring pixel. The guard ring thus provides suppression of crosstalk (blur)” (see [0029] of Lauter)
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0065939 A1; Bui et al.; 03/2010; (“Bui”) as applied to claim 1 above, and further in view of US 2015/0279894 A1; Cheng et al.; 10/2015; (“Cheng”).
Regarding Claim 7. Bui discloses The photodiode device according to claim 1.
Bui does not disclose the device further comprising an epi-layer of the first type of electric conductivity arranged on the center region of the incidence area.
However, Cheng teaches a photodiode device (#250, Figure 2B, complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device) comprising a including an incidence area of a first conductivity type (#252, Figure 2B, p-type front absorption layer), and further comprising an epi layer of the first type of electric conductivity (#202, Figure 2B, front passivation layer which may be a p-type epitaxial layer according to [0019]) arranged on the center region of the incidence area (Figure 2B, #202 is arranged on at least a center region of #252).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a first conductivity type front passivation layer over the top center of the incidence area in Bui as was done in Cheng since the front passivation layer “can provide a smooth interface with reduced roughness between the passivation layer and the light-sensing region” ([0018] of Cheng) and “may provide improved operation efficiency and performance of the CIS device” ([0022] of Cheng).
Regarding Claim 17. Bui discloses A photodiode device (#200, Figure 2, photodiode where Figure 3C is an example cross-sectional view ([0065]) and Figures 4A-4I and 5A-5E detail the manufacturing process ([0066]-[0079])), comprising:
a semiconductor substrate (#335 and #305, Figure 3C, mechanical support and thin active layer) with a main surface (Figure 3C, top surface of #305), the semiconductor substrate being of a first type of electric conductivity ([0120], #335 is n+ type and [0123], thin active layer is n-type), wherein the main surface comprises an incidence area for electromagnetic radiation (Figure 2, let any of the 7 areas surrounded on all four sides by #205 be an incidence area),
a plurality of doped wells of a second type of electric conductivity (#310, Figure 3C, p+ fishbones) at the main surface of the substrate (Figure 3C, #310s are at the top surface of #305), the second type of electric conductivity being opposite to the first type of electric conductivity (p-type fishbones are the opposite of the n-type substrate),
wherein the doped wells and the substrate are electrically contactable ([0052], p+ fishbones all include metal contact bars, i.e. they are electrically contactable; [0143] and Figure 4I, the substrate is contacted by metal layer #447 and metal contacts #446)
wherein the doped wells are arranged along a perimeter of the incidence area (Figure 2, p+ bones are arranged along the perimeter of each of the 7 incidence areas), such that a center region of the incidence area is free from the doped wells (Figure 3C, a center region of the incidence area between adjacent fishbones is free from the fishbones).
Bui does not disclose the device further comprising an epi-layer of the first type of electric conductivity arranged on the center region of the incidence area.
However, Cheng teaches a photodiode device (#250, Figure 2B, complimentary metal-oxide-semiconductor (CMOS) image sensor (CIS) device) comprising a including an incidence area of a first conductivity type (#252, Figure 2B, p-type front absorption layer), and further comprising an epi layer of the first type of electric conductivity (#202, Figure 2B, front passivation layer which may be a p-type epitaxial layer according to [0019]) arranged on the center region of the incidence area (Figure 2B, #202 is arranged on at least a center region of #252).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a first conductivity type front passivation layer over the top center of the incidence area in Bui as was done in Cheng since the front passivation layer “can provide a smooth interface with reduced roughness between the passivation layer and the light-sensing region” ([0018] of Cheng) and “may provide improved operation efficiency and performance of the CIS device” ([0022] of Cheng).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0319156 A1; Meinhardt et al.; 08/2019 - Figures 1 and 2 disclose a photodiode device including a doped surface region for incident light (#2, Figure 1) surrounded by doped regions (#3, doped wells) in a top view for charge collection in a lateral direction.
US 2018/0190708 A1; Lee et al.; 07/2018 - Figures 1 and2 disclose a light exposure region (#PDs, photodiodes) surrounded by doped regions (#FD1-3) in a top view for the purpose of charge collection in a lateral direction (Figure 2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J WIEGAND/Examiner, Art Unit 2812