DETAILED ACTION
This correspondence is in response to the communications received June 7, 2023. Claims 1-13 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
Claims 1, 5, 7, 12 and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The recitation, “the masking layer including a first masking part covering the non-capacitance generation region and a second masking part not covering at least part of the capacitance generation region”, renders the claim indefinite, as it is confusing as to what this limitation is attempting to set forth. The metes and bounds of the limitation are unclear and infinite, since there already is a portion of the masking layer that is not covering the capacitance region (e.g. “a first masking part covering the non-capacitance generation region”), so then it becomes either redundant or indefinite as the second portion of the limitation is set forth (e.g. “a second masking part not covering at least part of the capacitance generation region”). In the specification, “the second masking part” is identified as element “52”, ¶ 0051, as shown in Applicant’s Fig. 2D (provided below).
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It is unclear how element 52 can be interpreted to satisfy the limitation of “not covering at least part of the capacitance generation region”, when 52 is only covering the capacitance generating region. The entirety of the region bounded by the groove 4 is the capacitance generating region. It is unclear how this configuration is intended to be oriented, and for purposes of examination, this limitation will be understood to mean and interpreted in the manner of, wherein the mask layer has a portion which covers the capacitance generating region, and subsequently the “second masking part” exists for a moment in the method sequence, and then is ultimately removed by etching and patterning of the mask layer to expose the capacitance generating region, as can be seen in Applicant’s Fig. 3A (provided below).
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1, a method for manufacturing a capacitor, the method comprising:
a groove (4, ¶ 0017) forming step of preparing a silicon substrate (2, ¶ 0016) having a first surface and a second surface opposite the first surface, the silicon substrate including a capacitance generation region (31, ¶ 0017) and a non-capacitance generation region (32, ¶ 0017) which is a region other than the capacitance generation region when viewed along a direction connecting the first surface and the second surface (vertical dimension / direction) and
forming a groove (4) at a boundary between the capacitance generation region and the non-capacitance generation region (4 boundary between 31 and 32 regions), the groove being recessed from the first surface toward the second surface (groove made in top surface toward the lower surface of 2);
a masking layer (5, ¶ 0017) forming step of forming a masking layer on the first surface of the silicon substrate (top surface of 2), the masking layer including a first masking part (51, ¶ 0051) covering the non-capacitance generation region (51 covering 32) and a second masking part (52, ¶ 0051) not covering at least part of the capacitance generation region (52 not covering at least part of the 31 region);
a porous part (6, ¶ 0017) forming step of forming a porous part in the capacitance generation region (31) of the silicon substrate (2) by an anodic oxidation process,
the porous part (6) having fine pores (6 are “fine pores”);
a dielectric layer (7, ¶ 0020) forming step of forming a dielectric layer on inner surfaces of the fine pores (7 on inner surfaces of 6); and
a conductor layer (8, ¶ 0033) forming step of forming a conductor layer including a first conductive part (81, ¶ 0035) and a second conductive part (82, ¶ 0035) electrically connected to the first conductive part (shown in direct contact with each other), the first conductive part being in contact with the dielectric layer (shown), the second conductive part being in the capacitance generation region of the first surface (part of 82 in region 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 11,784,000) in view of Ho et al. (US 2015/0214244).
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Regarding claim 1, the prior art of Yoshida discloses in Figs. 1-4, 9 and 10, a method for manufacturing a capacitor (see title, “Capacitor and Method For Producing Same”), the method comprising:
a forming step of preparing a silicon substrate (“silicon substrate 1”, col. 2, lines 62-63) having a first surface (upper surface of 1) and a second surface (lower surface of 1) opposite the first surface, the silicon substrate (1) including a capacitance generation region (“capacitance generation region 11”, col. 2, lines 63-64) and a non-capacitance generation region (“non-capacitance generation region 12”, col. 2, lines 64-65) which is a region other than the capacitance generation region when viewed along a direction connecting the first surface and the second surface (vertical dimension / direction) and
a masking layer (“masking layer 40”, col. 10, line 19) forming step of forming a masking layer on the first surface of the silicon substrate (40 on upper surface of 1), the masking layer including a first masking part (portion of 40 over 12) covering the non-capacitance generation region (portion of 40 over 12) and a second masking part not covering at least part of the capacitance generation region (portion of 40 over 11 in Fig. 2C, which is then removed in Fig. 2D, which is interpreted as discussed in the 112b rejection above, wherein the mask layer has a portion which covers the capacitance generating region, and subsequently the “second masking part” exists for a moment in the method sequence, and then is ultimately removed by etching and patterning of the mask layer to expose the capacitance generating region);
a porous part (“forming the porous part 13”, col. 11, line 26) forming step of forming a porous part (13) in the capacitance generation region (11) of the silicon substrate (1), by an anodic oxidation process (“The porous part forming step includes, by the anode oxidation process, forming the porous part 13 in the capacitance generation region 11 in the thickness direction of the silicon substrate 1 by forming the fine pores 130 in the capacitance generation region 11 which is not covered with the masking layer 40.”, col. 11, lines 25-30).
the porous part (13) having fine pores (see Fig. 9, elements 130, “fine pores 130”, col. 3, line 3);
a dielectric layer (“dielectric layer 3”, col. 3, line 3-5) forming step of forming a dielectric layer on inner surfaces of the fine pores (col. 3, line 3-5, “dielectric layer 3 is provided between an inner surface of the fine pores 130 and the filling part 22”); and
a conductor layer (“surface layer part 21”, col. 6, lines 59-60, and “filling part 22”, col. 3, lines 6-21, both 21 and 22 are portions of electrode / “conductor layer 2”, col. 6, lines 56-58) forming step of forming a conductor layer (2) including a first conductive part (22) and a second conductive part (21) electrically connected to the first conductive part (21 and 22 are in direct electrical connection with each other), the first conductive part being in contact with the dielectric layer (22 in contact with 3), the second conductive part (21) being in the capacitance generation region of the first surface (21 in contact with region 11 and 22).
Yoshida does not disclose,
“a groove forming step of … forming a groove at a boundary between the capacitance generation region and the non-capacitance generation region, the groove being recessed from the first surface toward the second surface”.
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Ho discloses in Figs. 1-3, wherein the capacitor region (capacitors in the “ARRAY AREA”) is surrounded by a groove (“deep recess 120”, ¶ 0024), which is formed before the capacitors (see progression of formation in Figs. 1 to 3, capacitors and array areas discussed together in many areas including ¶ 0027).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use, “a groove forming step of … forming a groove at a boundary between the capacitance generation region and the non-capacitance generation region, the groove being recessed from the first surface toward the second surface”, as disclosed by Ho in the system of Yoshida, for the purpose of establishing a perimeter for the capacitor which can aid in the isolation of the device region. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, Yoshida et al. disclose the method of claim 1, further comprising a filling step of filling an insulative material in the groove (Ho discloses, “liner 125 of an insulating material such as silicon oxide or silicon nitride can then be deposited and the recess filled”, ¶ 0024).
Regarding claim 3, Yoshida et al. disclose the method of claim 1, further comprising a filling step of forming an insulating layer on an inner surface of the groove (Ho discloses, “liner 125 of an insulating material such as silicon oxide or silicon nitride can then be deposited and the recess filled”, ¶ 0024) and filling a filler material in the groove provided with the insulating layer (Ho discusses filling the trench 120 with dielectrics in ¶ 0025).
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 11,784,000) in view of Tian et al. (US 8,487,405).
Regarding claim 5, the prior art of Yoshida discloses in Figs. 1-4, 9 and 10, a method for manufacturing a capacitor (see title, “Capacitor and Method For Producing Same”), the method comprising:
an forming step of preparing a silicon substrate (1) which is a p-type semiconductor (“The silicon substrate 1 may be a p-type semiconductor”, col. 3, lines 49-50) having a first surface (top surface of 1) and a second surface (lower surface of 1) opposite the first surface (top and bottom surfaces being opposite to each other),
the silicon substrate (1) including a capacitance generation region (“capacitance generation region 11”, col. 2, lines 63-64) and a non-capacitance generation region (“non-capacitance generation region 12”, col. 2, lines 64-65) which is a region other than the capacitance generation region when viewed along a direction connecting the first surface and the second surface (vertical dimension / direction, two regions distinct from each other);
a masking layer (“masking layer 40”, col. 10, line 19) forming step of forming a masking layer (40) on the first surface of the silicon substrate (top surface of 1), the masking layer (40) including a first masking part (portion of 40 over 12) covering the non-capacitance generation region (covering 12) and a second masking part (portion of 40 over 11, then removed subsequently) not covering at least part of the capacitance generation region (portion of 40 over 11 in Fig. 2C, which is then removed in Fig. 2D, which is interpreted as discussed in the 112b rejection above, wherein the mask layer has a portion which covers the capacitance generating region, and subsequently the “second masking part” exists for a moment in the method sequence, and then is ultimately removed by etching and patterning of the mask layer to expose the capacitance generating region);
a porous part (“forming the porous part 13”, col. 11, line 26) forming step of forming a porous part (13) in the capacitance generation region (11) of the silicon substrate (1), by an anodic oxidation process (“The porous part forming step includes, by the anode oxidation process, forming the porous part 13 in the capacitance generation region 11 in the thickness direction of the silicon substrate 1 by forming the fine pores 130 in the capacitance generation region 11 which is not covered with the masking layer 40.”, col. 11, lines 25-30).
the porous part (13) having fine pores (see Fig. 9, elements 130, “fine pores 130”, col. 3, line 3);
a dielectric layer (“dielectric layer 3”, col. 3, line 3-5) forming step of forming a dielectric layer on inner surfaces of the fine pores (col. 3, line 3-5, “dielectric layer 3 is provided between an inner surface of the fine pores 130 and the filling part 22”); and
a conductor layer (“surface layer part 21”, col. 6, lines 59-60, and “filling part 22”, col. 3, lines 6-21, both 21 and 22 are portions of electrode / “conductor layer 2”, col. 6, lines 56-58) forming step of forming a conductor layer (2) including a first conductive part (22) and a second conductive part (21) electrically connected to the first conductive part (21 and 22 are in direct electrical connection with each other), the first conductive part being in contact with the dielectric layer (22 in contact with 3), the second conductive part (21) being in the capacitance generation region of the first surface (21 in contact with region 11 and 22).
Yoshida does not disclose,
“an n-type semiconductor part forming step of preparing a silicon substrate which is a p-type semiconductor having a first surface and a second surface opposite the first surface,
…
forming an n-type semiconductor part at a boundary between the capacitance generation region and the non-capacitance generation region,
…
the n-type semiconductor part extending from the first surface toward the second surface”.
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Tian discloses in Fig. 2,
an n-type semiconductor part forming step (104, “N+” type layer) of preparing a silicon substrate (“silicon substrate 102”, col. 6, line 59) which is a p-type semiconductor (Yoshida discloses that the substrate is p type, col. 3, lines 49-50, “The silicon substrate 1 may be a p-type semiconductor”) having a first surface and a second surface opposite the first surface (top and bottom surface of substrate),
…
forming an n-type semiconductor part at a boundary between the capacitance generation region and the non-capacitance generation region (N+ region 104, which has portions which are between a central capacitor region and a peripheral region),
…
the n-type semiconductor part extending from the first surface toward the second surface (104 extends from top of substrate to lower surface of substrate).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“an n-type semiconductor part forming step of preparing a silicon substrate which is a p-type semiconductor having a first surface and a second surface opposite the first surface,
…
forming an n-type semiconductor part at a boundary between the capacitance generation region and the non-capacitance generation region,
…
the n-type semiconductor part extending from the first surface toward the second surface”, as disclosed by Tian in the system of Yoshida, for the purpose of providing the access to the opposite side electrical connection of the capacitor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 12, the prior art of Yoshida discloses in Figs. 1-4, 9 and 10, a method for manufacturing a capacitor (see title, “Capacitor and Method For Producing Same”), the method comprising:
masking layer forming step of
preparing a silicon substrate (“silicon substrate 1”, col. 2, lines 62-63) having a first surface (upper surface of 1) and a second surface (lower surface of 1) opposite the first surface, the silicon substrate (1) including a capacitance generation region (“capacitance generation region 11”, col. 2, lines 63-64) and a non-capacitance generation region (“non-capacitance generation region 12”, col. 2, lines 64-65) which is a region other than the capacitance generation region when viewed along a direction connecting the first surface and the second surface (vertical dimension / direction),
forming a masking layer (“masking layer 40”, col. 10, line 19) on the first surface of the silicon substrate (top surface of 1),
the masking layer (40) including a first masking part (portion of 40 over 12) covering the non-capacitance generation region (covering 12) and a second masking part (portion of 40 over 11, then removed subsequently) not covering at least part of the capacitance generation region (portion of 40 over 11 in Fig. 2C, which is then removed in Fig. 2D, which is interpreted as discussed in the 112b rejection above, wherein the mask layer has a portion which covers the capacitance generating region, and subsequently the “second masking part” exists for a moment in the method sequence, and then is ultimately removed by etching and patterning of the mask layer to expose the capacitance generating region);
a porous part (“forming the porous part 13”, col. 11, line 26) forming step of forming a porous part (13) in the capacitance generation region (11) of the silicon substrate (1), by an anodic oxidation process (“The porous part forming step includes, by the anode oxidation process, forming the porous part 13 in the capacitance generation region 11 in the thickness direction of the silicon substrate 1 by forming the fine pores 130 in the capacitance generation region 11 which is not covered with the masking layer 40.”, col. 11, lines 25-30).
the porous part (13) having fine pores (see Fig. 9, elements 130, “fine pores 130”, col. 3, line 3);
a dielectric layer (“dielectric layer 3”, col. 3, line 3-5) forming step of forming a dielectric layer on inner surfaces of the fine pores (col. 3, line 3-5, “dielectric layer 3 is provided between an inner surface of the fine pores 130 and the filling part 22”); and
a conductor layer (“surface layer part 21”, col. 6, lines 59-60, and “filling part 22”, col. 3, lines 6-21, both 21 and 22 are portions of electrode / “conductor layer 2”, col. 6, lines 56-58) forming step of forming a conductor layer (2) including a first conductive part (22) and a second conductive part (21) electrically connected to the first conductive part (21 and 22 are in direct electrical connection with each other), the first conductive part being in contact with the dielectric layer (22 in contact with 3), the second conductive part (21) being in the capacitance generation region of the first surface (21 in contact with region 11 and 22).
Yoshida does not disclose,
“a low-resistance part forming step of forming a low-resistance part having a same shape as the capacitance generation region at a same location as the capacitance generation region in the silicon substrate when viewed along the direction connecting the first surface and the second surface, the low-resistance part having a lower specific resistance than the silicon substrate and extending from the second surface toward the first surface”.
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Tian discloses in Fig. 2,
a low-resistance part (N+ 104) forming step of forming a low-resistance part (N+ 104) having a same shape as the capacitance generation region at a same location as the capacitance generation region in the silicon substrate when viewed along the direction connecting the first surface and the second surface (104 matches the shape of the region of the capacitor), the low-resistance part having a lower specific resistance than the silicon substrate (“. The N+ well 104 may act as a landing pad 106 for the bottom of connection 108.”, col. 6, lines 62-63, where the highly conductive n-type material is of low resistivity) and extending from the second surface toward the first surface (104 extends from top of substrate 102 to lower surface thereof).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use,
“a low-resistance part forming step of forming a low-resistance part having a same shape as the capacitance generation region at a same location as the capacitance generation region in the silicon substrate when viewed along the direction connecting the first surface and the second surface, the low-resistance part having a lower specific resistance than the silicon substrate and extending from the second surface toward the first surface”, as disclosed by Tian in the system of Yoshida, for the purpose of providing the access to the opposite side electrical connection of the capacitor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 11,784,000).
Regarding claim 7, the prior art of Yoshida discloses in Figs. 1-4, 9 and 10, a method for manufacturing a capacitor (see title, “Capacitor and Method For Producing Same”), the method comprising:
a masking layer forming step of
preparing a silicon substrate (“silicon substrate 1”, col. 2, lines 62-63) having a first surface (upper surface of 1) and a second surface (lower surface of 1) opposite the first surface, the silicon substrate (1) including a capacitance generation region (“capacitance generation region 11”, col. 2, lines 63-64) and a non-capacitance generation region (“non-capacitance generation region 12”, col. 2, lines 64-65) which is a region other than the capacitance generation region when viewed along a direction connecting the first surface and the second surface (vertical dimension / direction),
and forming a masking layer (“masking layer 40”, col. 10, line 19) on the first surface of the silicon substrate (top surface of 1),
the masking layer (40) including a first masking part (portion of 40 over 12) covering the non-capacitance generation region (covering 12) and a second masking part (portion of 40 over 11, then removed subsequently) not covering at least part of the capacitance generation region (portion of 40 over 11 in Fig. 2C, which is then removed in Fig. 2D, which is interpreted as discussed in the 112b rejection above, wherein the mask layer has a portion which covers the capacitance generating region, and subsequently the “second masking part” exists for a moment in the method sequence, and then is ultimately removed by etching and patterning of the mask layer to expose the capacitance generating region);
a porous part forming step (“forming the porous part 13”, col. 11, line 26) of forming a backside electrode (53, Fig. 10) having a same shape as the capacitance generation region (shown in Fig. 10, 53 has same general shape of region 11) at a same location as the capacitance generation region on the second surface of the silicon substrate (53 on lower surface of 1) when viewed along a direction connecting the first surface and the second surface (vertical direction) and forming a porous part (13) in the capacitance generation region (11) of the silicon substrate (1) by an anodic oxidation process (“The porous part forming step includes, by the anode oxidation process, forming the porous part 13 in the capacitance generation region 11 in the thickness direction of the silicon substrate 1 by forming the fine pores 130 in the capacitance generation region 11 which is not covered with the masking layer 40.”, col. 11, lines 25-30) by using the backside electrode as an anode (“The back surface electrode 141 is an electrode used when the silicon substrate 1 is subjected to the anode oxidation process”, col. 11, lines 33-35),
the porous part (13) having fine pores (see Fig. 9, elements 130, “fine pores 130”, col. 3, line 3);
a dielectric layer (“dielectric layer 3”, col. 3, line 3-5) forming step of forming a dielectric layer on inner surfaces of the fine pores (col. 3, line 3-5, “dielectric layer 3 is provided between an inner surface of the fine pores 130 and the filling part 22”); and
a conductor layer forming step of forming a conductor layer (“surface layer part 21”, col. 6, lines 59-60, and “filling part 22”, col. 3, lines 6-21, both 21 and 22 are portions of electrode / “conductor layer 2”, col. 6, lines 56-58) including a first conductive part (22) and a second conductive part (21) electrically connected to the first conductive part (21 and 22 are in direct electrical connection with each other), the first conductive part being in contact with the dielectric layer (22 in contact with 3), the second conductive part (21) being in the capacitance generation region of the first surface (21 in contact with region 11 and 22).
Fig. 10 of Yoshida does not describe the anodic process using the backside electrode, “forming a porous part in the capacitance generation region of the silicon substrate by an anodic oxidation process by using the backside electrode as an anode”.
However Fig. 3A discloses the use of the backside electrode for the anodic process, see col. 11, lines 33-35, “The back surface electrode 141 is an electrode used when the silicon substrate 1 is subjected to the anode oxidation process”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use, “forming a porous part in the capacitance generation region of the silicon substrate by an anodic oxidation process by using the backside electrode as an anode”, as disclosed by Fig. 3A of Yoshida in the system of Fig. 10 of Yoshida, for the purpose of providing finer control of the spread of the anodic process to where the capacitor device is located and not to areas where the capacitor is not located. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 11,784,000) in view of Nishiyama et al. (US 2018/0277622).
Regarding claim 8, Yoshida et al. disclose the method of claim 7, however Yoshida does not disclose, “further comprising an insulating layer forming step of forming an insulating layer on the second surface of the silicon substrate except for part of the second surface on which the backside electrode is provided.”
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Nishiyama discloses in Fig. 1, further comprising an insulating layer (“insulator film 6”, ¶ 0038) forming step of forming an insulating layer on the second surface (lower surface of 1) of the silicon (silicon material already disclosed in the rejection of claim 7) substrate (1) except for part of the second surface on which the backside electrode is provided (6 located on lower surface of 1, except for where electrode 5 is located).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use, “further comprising an insulating layer forming step of forming an insulating layer on the second surface of the silicon substrate except for part of the second surface on which the backside electrode is provided”, as disclosed by Nishiyama in the system of Yoshida, for the purpose of passivating the active region exposed from the lower electrode, so as to prolong the lifetime of the active device by preventing intrusion of unwanted elements to the active region of the device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 4, 6, 9, 10, 11 and 13 would potentially be objected to if the 112b rejections are overcome and subsequently, they would be objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
4. (Original) The method of claim 1, further comprising a filling step, wherein the silicon substrate is a p-type semiconductor (Yoshida discloses in col. 3, lines 49-50, “The silicon substrate 1 may be a p-type semiconductor”), and the filling step includes forming an semiconductor layer on an inner surface of the groove and filling a filler material in the groove provided with the n-type semiconductor layer. Ho only teaches “a semiconductor material can be used for fill if optional liner 125 is deposited” (¶ 0024). The prior art fails to disclose, “and the filling step includes forming an n-type semiconductor layer on an inner surface of the groove and filling a filler material in the groove provided with the n-type semiconductor layer.”
6. (Currently Amended) The method of claim 1, wherein the second masking part has a plurality of through holes extending through the second masking part in a thickness direction defined with respect to the second masking part.
9. (Currently Amended) The method of claim 7, further comprising a groove forming step of forming a groove around the backside electrode, the groove being recessed from the second surface toward the first surface.
10. (Original) The method of claim 9, further comprising a filling step of filling an insulative material in the groove. Claim 10 being objected to for the reason that the claim upon which it depends has been objected to.
11. (Currently Amended) The method of claim 7, wherein the silicon substrate further has a third surface opposite the first surface, and a distance between the third surface and the first surface is shorter than a distance between the second surface on which the backside electrode is formed and the first surface.
13. (Currently Amended) The method of claim 7, wherein the second masking part has a plurality of through holes extending through the second masking part in a thickness direction defined with respect to the second masking part.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893