Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6-10 and 13 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Tanaka et. Al. (US 20190252442 A1 hereinafter Tanaka).
Regarding claims 1 and 13, Tanaka teaches in Figs. 1-3, 6 and 14 with associated text an electronic device 203 comprising: a photodetector 203; and an optical system 202 configured to form an image of image light from a subject on the photodetector ([0120]), wherein the photodetector includes:: a first semiconductor substrate 41A including; a first semiconductor layer in which a plurality of photoelectric conversion sections 31 is provided in an array along a row direction and a column direction (Figs. 1 and 6), and a first wiring layer 42 on a main surface side of the first semiconductor layer (Fig. 6, [0040]); a second semiconductor substrate including; a second semiconductor layer (logic circuit board (not shown) includes p-type MOSFETs 32, and the CMOS inverters 33 [0040] and therefore includes a semiconductor layer so that it is interpreted to be a semiconductor substrate) with an active element [0040] and a second wiring layer 43 on a main surface side of the second semiconductor layer (Fig. 1 and 6, [0040]), wherein the second wiring layer is overlapped with first wiring layer and the second wiring layer is joined to the first wiring layer (Fig. 6, [0062]); and a light shielding wall (portion of 63B of Fig. 6 or 72 and 75 of Fig. 2 separating two adjacent pixels in the row direction) that divides at least one of at least a part of an interlayer insulating film of the first wiring layer (Figs. 3 and 6, [0079]-[0080] or 75 is a metal layer surrounds 74 Figs. 3 and the option of the insulating layer around it Figs. 2-3, [0056] so that it is interpreted to be a light shielding wall)) or at least a part of a portion of an interlayer insulating film of the second wiring layer on a side of the first semiconductor substrate into respective portions corresponding to a first photoelectric conversion section of the plurality of photoelectric conversion sections and a second photoelectric conversion section of the plurality of photoelectric conversion sections, wherein the first photoelectric conversion section is adjacent to the second photoelectric conversion section (Fig. 3 and 6, [0079]-[0080]), and the light shielding wall extends only along the column direction (the light shielding wall in interpreted to be the portion of layer 63B or 75 extending vertically on one side of the pixel (see annotated figure below), as the term wall may refer to only a single segment of for example a four walled structure, the claim wouldn’t necessarily require the light shielding wall to divide more than two pairs of pixel regions or there to be no light shielding layers extending in the row direction).
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Regarding claim 2, Tanaka teaches the light shielding wall prevents transmission of light in a wavelength band that is photoelectrically convertible by the plurality of photoelectric conversion sections ([0079]-[0080]).
Regarding claim 6, Tanaka teaches the light shielding wall penetrates the interlayer insulating film of the first wiring layer (Fig. 1).
Regarding claim 7, Tanaka teaches the light shielding wall penetrates the portion of the interlayer insulating film of the second wiring layer on the main surface side of the first semiconductor substrate (here 79B, 82, 121, 103, 99, and 100 are also interpreted to be part of the light shielding wall Fig. 2).
Regarding claim 8, Tanaka teaches one end of the light shielding wall in a thickness direction (72 and 75 here) of the first semiconductor substrate is connected to one of the plurality of photoelectric conversion sections (Fig. 2, [0049]).
Regarding claim 9, Tanaka teaches the light shielding wall is configured to supply a bias voltage from the second semiconductor substrate to the plurality photoelectric conversion sections (Fig. 6, [0065]).
Regarding claim 10, Tanaka teaches the light shielding wall includes: a first connection wiring (here 79B, 82, 121 are also interpreted to be part of the light shielding wall Fig. 6) in the first wiring layer, wherein the first connection wiring faces a first surface opposite to a surface on a side of the first semiconductor layer among a plurality of surfaces of the first wiring layer (Fig. 6); and a second connection wiring 103, 99, and 100) in the second wiring layer, wherein the second connection wiring faces a second surface opposite to a surface on a side of the second semiconductor layer among a plurality of surfaces of the second wiring layer, and the second connection wiring is joined to the first connection wiring (Fig. 6, [0057]-[0060]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka.
Regarding claim 5, Tanaka teaches the photodetector according to claim 4, wherein a plurality of the photoelectric conversion sections provided in an array is applied with a bias voltage in units of rows (bias voltages are applied separately to rows by 13 Fig. 1, [0036]).
Tanaka does not specify rows to which the bias voltage is applied are sequentially selected along the column direction.
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
The following italicized limitations of claim 5 lines 2-4 are understood to be functional (i.e. is applied with a bias voltage in units of rows, and rows to which the bias voltage is applied are sequentially selected along a column direction): The limitation describes purpose, function, operation, or intent -of-use the photoelectric conversion sections provided in an array. However, the claim does not disclose a sufficient structure which supports the function. Since Tanaka shows an identical structure as claimed, namely the photoelectric conversion sections provided in an array., the Examiner submits that the photoelectric conversion sections provided in an array. is capable of producing the claimed results.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka as applied to claim 1 and further in view of Doi et. Al. (US 20140117486 A1 hereinafter Doi).
Regarding claim 11, Tanaka teaches each of the plurality of photoelectric conversion sections includes an avalanche photodiode [0035], the photodetector further comprises a reading electrode 77 that is configured to output carriers from the avalanche photodiode to the second semiconductor substrate for the each of the plurality of photoelectric conversion sections (Figs. 1 and 6 output signal is from the cathode or 53 [0043] connected to 71 Fig. 2 [0053])), the light shielding wall is configured to supply a bias voltage to the avalanche photodiode.
Tanaka does not specify the light shielding wall surrounds the reading electrode.
Doi teaches in Figs. 8 and 9 with associated text a light shielding wall (all of 26e, 26d and 24d of Fig. 8 and 440 of Fig. 9) similar to that of Tanaka that surrounds a reading electrode (440 surrounds pixels 72 and their reading electrodes 26c (contact plug 26c contacts reading unit 18 and so is a reading electrode Fig. 8, [0031]- [0032]) and further shows a separate embodiment with a light shielding wall 40 (Fig. 1, [0028]) having a shape similar to that of Tanaka.
One of ordinary skill in the art before the filing date of the invention would have used the shape taught Doi for the light shielding wall of Tanaka because according to Doi the shield electrode is formed in a square lattice pattern in plan view, however, it is not limited to this, for example, shield electrodes 440 may be formed in lines as illustrated in FIG. 9 such that each line of shield electrode 440 is provided only between adjacent columns [0094] One of ordinary skill in the art before the filing date of the invention would have been motivated to look to analogous art teaching alternative suitable or useful structures for light shielding walls, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 12, Tanaka teaches each of the plurality of photoelectric conversion sections includes an avalanche photodiode [0035], the photodetector further comprises a reading electrode 71 of a plurality of reading electrodes, the reading electrode is configured to output carriers from the avalanche photodiode to the second semiconductor substrate for the each of the plurality of photoelectric conversion sections (Figs. 1 and 6 output signal is from the cathode or 53 [0043] connected to 71 Fig. 2 [0053])), the light shielding wall is configured to supply a bias voltage to the avalanche photodiode, the light shielding wall divides each of a first reading electrode of the plurality of reading electrodes and a second reading electrode of the plurality of reading electrodes in the column direction and the first reading electrode is adjacent to the second reading electrode (75 and 72 Fig. 2-3 which is connected to anode 56 biased by VDB).
Tanaka does not specify the light shielding wall divides each of a first reading electrode of the plurality of reading electrodes and a second reading electrode of the plurality of reading electrodes in the column direction and the first reading electrode is adjacent to the second reading electrode.
Doi teaches in Figs. 8 and 9 with associated text a light shielding wall (all of 26e, 26d and 24d of Fig. 8 and 440 of Fig. 9) similar to that of Tanaka that divides each of a first reading electrode of the plurality of reading electrodes and a second reading electrode of the plurality of reading electrodes in the column direction and the first reading electrode is adjacent to the second reading electrode (contact plug 26c contacts reading unit 18 and so is a reading electrode Fig. 8, [0031]- [0032]) and further shows a separate embodiment with a light shielding wall 40 (Fig. 1, [0028]) having a shape similar to that of Tanaka.
One of ordinary skill in the art before the filing date of the invention would have used the shape taught Doi for the light shielding wall of Tanaka because according to Doi the shield electrode is formed in a square lattice pattern in plan view, however, it is not limited to this, for example, shield electrodes 440 may be formed in lines as illustrated in FIG. 9 such that each line of shield electrode 440 is provided only between adjacent columns [0094] One of ordinary skill in the art before the filing date of the invention would have been motivated to look to analogous art teaching alternative suitable or useful structures for light shielding walls, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Response to Arguments
Applicant's arguments filed 7/9/2026 have been fully considered but they are not persuasive. Regarding the arguments on pages 10-12 Tanaka teaches the light shielding wall extends only along the column direction (the light shielding wall is interpreted to be the portion of layer 63B or 75 extending vertically on one side of the pixel (see annotated figure below), as the term wall may refer to only a single linear segment of for example a four walled structure, the claim wouldn’t necessarily require the light shielding wall to divide more than two pairs of pixel regions or there to be no light shielding layers extending in the row direction).
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Furthermore even if the claim requires a light shielding wall to separate plural pairs of pixels examiner notes that Doi teaches a shielding wall 440 in Fig. 9, as applied to claims 11-12, with such a structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AARON J GRAY/Examiner, Art Unit 2897
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