Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-13 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by
Tanaka et. Al. (US 20190252442 A1 hereinafter Tanaka).
Regarding claims 1 and 13, Tanaka teaches in Figs. 1-3, 6 and 14 with associated text an electronic device 203 comprising: a photodetector 203; and an optical system 202 that forms an image of image light from a subject on the photodetector ([0120]), wherein the photodetector includes:: a first semiconductor substrate 41A including a first semiconductor layer in which a plurality of photoelectric conversion sections 31 is provided in an array along a row direction and a column direction (Figs. 1 and 6), and a first wiring layer 42 provided on a main surface side of the first semiconductor layer (Fig. 6, [0040]); a second semiconductor substrate including a second semiconductor layer (logic circuit board (not shown) includes p-type MOSFETs 32, and the CMOS inverters 33 [0040] and therefore includes a semiconductor layer so that it is interpreted to be a semiconductor substrate) provided with an active element [0040] and a second wiring layer 43 provided on a main surface side of the second semiconductor layer (Fig. 1 and 6, [0040]), the second wiring layer being overlapped with and joined to the first wiring layer (Fig. 6, [0062]); and a light shielding wall (63B of Fig. 6 or 72 and 75 of Fig. 2) that divides at least one of at least a part of an interlayer insulating film of the first wiring layer (Figs. 3 and 6, [0079]-[0080] or 75 is a metal layer surrounds 74 Figs. 3 and the option of the insulating layer around it Figs. 2-3, [0056] so that it is interpreted to be a light shielding wall)) or at least a part of a portion of an interlayer insulating film of the second wiring layer on a side of the first semiconductor substrate into respective portions corresponding to a first photoelectric conversion section and a second photoelectric conversion section adjacent to each other of a plurality of the photoelectric conversion sections (Fig. 3 and 6, [0079]-[0080]).
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Regarding claim 2, Tanaka teaches the light shielding wall does not pass light in a wavelength band that is photoelectrically convertible by the photoelectric conversion sections ([0079]-[0080]).
Regarding claim 3, Tanaka teaches the light shielding wall includes at least one of a first portion extending along the row direction or a second portion extending along the column direction (for example the light shielding wall in interpreted to be the wall of layer 75 extending vertically on the right side of the pixel Fig. 3).
Regarding claim 4, Tanaka teaches the light shielding wall includes only the second portion extending along the column direction (for example the light shielding wall in interpreted to be the wall of layer 63B or 75 extending vertically on the right side of the pixel Fig. 3 the claim wouldn’t necessarily require the light shielding wall to device more than two pixel regions or that the wall isn’t part of a structure that extends only one direction)..
Regarding claim 6, Tanaka teaches the light shielding wall penetrates the interlayer insulating film of the first wiring layer (Fig. 1).
Regarding claim 7, Tanaka teaches the light shielding wall penetrates a portion of the interlayer insulating film of the second wiring layer on a side of the first semiconductor substrate (here 79B, 82, 121, 103, 99, and 100 are also interpreted to be part of the light shielding wall Fig. 2).
Regarding claim 8, Tanaka teaches one end of the light shielding wall in a thickness direction (72 and 75 here) of the first semiconductor substrate is connected to one of the photoelectric conversion sections (Fig. 2, [0049]).
Regarding claim 9, Tanaka teaches the light shielding wall supplies a bias voltage from the second semiconductor substrate to the photoelectric conversion sections (Fig. 6, [0065]).
Regarding claim 10, Tanaka teaches the light shielding wall includes: a first connection wiring (here 79B, 82, 121 are also interpreted to be part of the light shielding wall Fig. 6) provided in the first wiring layer and facing a surface opposite to a surface on a side of the first semiconductor layer among surfaces of the first wiring layer (Fig. 6); and a second connection wiring 103, 99, and 100) provided in the second wiring layer, facing a surface opposite to a surface on a side of the second semiconductor layer among surfaces of the second wiring layer, and joined to the first connection wiring (Fig. 6, [0057]-[0060]).
Regarding claim 11, Tanaka teaches the photoelectric conversion sections each include an avalanche photodiode [0035], the photodetector comprises a reading electrode 77 that outputs carriers from the avalanche photodiode to the second semiconductor substrate for each of the photoelectric conversion sections (Figs. 1 and 6 output signal is from the cathode or 53 [0043] connected to 71 Fig. 2 [0053])), and the light shielding wall includes both the first portion and the second portion, supplies a bias voltage to the avalanche photodiode, and surrounds the reading electrode by the first portion and the second portion (here the light shielding wall is interpreted to include the full surrounding structure of 75 and 72 Fig. 2-3 which is connected to anode 56 biased by VDB).
Regarding claim 12, Tanaka teaches the photoelectric conversion sections each include an avalanche photodiode [0035], the photodetector comprises a reading electrode 71 that outputs carriers from the avalanche photodiode to the second semiconductor substrate for each of the photoelectric conversion sections (Figs. 1 and 6 output signal is from the cathode or 53 [0043] connected to 71 Fig. 2 [0053])), the light shielding wall supplies a bias voltage to the avalanche photodiode, and divides the reading electrodes adjacent to each other in the row direction by the second portion (75 and 72 Fig. 2-3 which is connected to anode 56 biased by VDB).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka.
Regarding claim 5, Tanaka teaches the photodetector according to claim 4, wherein a plurality of the photoelectric conversion sections provided in an array is applied with a bias voltage in units of rows (bias voltages are applied separately to rows by 13 Fig. 1, [0036]).
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). The patentability of an apparatus claim depends only on the claimed structure, not on the use or purpose of that structure, Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir. 2002), or the function or result of that structure. In re Danly, 263 F.2d 844, 848 (CCPA 1959). Please also see M.P.E.P. 2114 [R-1].
The following italicized limitations of claim 5 lines 2-4 are understood to be functional (i.e. is applied with a bias voltage in units of rows, and rows to which the bias voltage is applied are sequentially selected along a column direction): The limitation describes purpose, function, operation, or intent -of-use the photoelectric conversion sections provided in an array. However, the claim does not disclose a sufficient structure which supports the function. Since Tanaka shows an identical structure as claimed, namely the photoelectric conversion sections provided in an array., the Examiner submits that the photoelectric conversion sections provided in an array. is capable of producing the claimed results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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