DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on September 09, 2026. Claims 1, 4, 5, 7, 9 and 20 have been amended. New claims 21-22 have been added. Claims 2-3 and 6 have been canceled. Claims 11-19 have been withdrawn. Currently, claims 1, 4-5, 7-10 and 20-22 are pending.
Applicant’s amendment to claims 1 and 20 successfully overcomes the 112(b) rejection of claims 1 and 20 and dependent claims set forth in the previous Office Action. Cancellation of claim 3 renders moot the 112(b) rejection of claim 3 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 20 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The declaration under 37 CFR 1.132 filed September 9, 2026 is insufficient to overcome the rejection of claims 1 and 20 based upon Malhi (5,717,241).
Declarant argues with respect to Malhi (5,717,241) that the channel relied upon in the rejection is an inversion layer formed under gate electrode 52 and that such an inversion layer exists only when an appropriate bias is applied to the gate electrode. Declarant further argues that Malhi is a four terminal device and that Malhi’s channel cannot be incorporated into the three terminal device of the primary reference without also incorporating Malhi’s gate electrode. According to Declarant, removal of the gate would prevent formation of the inversion layer whereas incorporation of the gate would undesirably convert the primary three terminal device into a four terminal device having a different mode of operation.
These arguments have been considered but are not persuasive as to the combination relied upon in the rejection.
Malhi explicitly discloses that the surface region 49 of base region 48 is selectively doped with a light p-type implant beneath the gate electrode 52 and between the emitter and collector (see e.g., Figure 12). Malhi further describes the implant as a very shallow, low dose p-type implant introduced into the semiconductor during fabrication. Accordingly, region 49 constitutes a physically doped semiconductor region formed by implantation and is distinct from the gate induced inversion condition of the MOS channel. The presence of the p-type dopant in region 49 does not depend upon application of a gate voltage for its physical existence.
Malhi discloses in Figure 12 a three-terminal embodiment in which the gate electrode is connected to the emitter so that the surface modulated conduction channel is turned off. As used by Malhi, the surface modulated conduction channel refers to the gate controlled surface MOSFET channel formed beneath the gate electrode between the emitter and collector whose conductivity is controlled by the gate induced surface condition including inversion. Thus, turning the surface modulated conduction channel off means suppressing the MOSFET type surface conduction path, it does not remove or negate the physically implanted p-type region 49.
Moreover, the claims do not exclude the presence of an additional gate electrode or otherwise require the device to consist exclusively of three terminals. In any event, Malhi’s Figure 12 confirms that the underlying semiconductor structure including the physically implanted p-type surface region 49 remains present even when the gate controlled MOS conduction channel is turned off and the device is operated as a three terminal bipolar transistor. Thus, the presence or operational use of the gate does not negate Malhi’s disclosure of the relied upon p-type doped semiconductor region.
Declarant further argues that the remaining cited references do not teach the claimed channel.
Even when the references are combined, Malhi only provides a gate electrode with gate induced inversion channel and therefore does not provide the claimed channel structure.
These arguments are not persuasive. As discussed above Malhi explicitly teaches the physically implanted p-type surface region 49 in the base region between emitter and collector. This doped region is formed during fabrication and does not depend on application of gate voltage for its physical existence. Malhi also shows in Figure 12 that the doped semiconductor structure remains present when the gate controlled surface conduction channel is turned off and the device operates as a three terminal bipolar transistor. Further the cited references are relied upon for their respective teachings in combination rather than requiring each reference individually to disclose every claimed feature.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, 9 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Mita et al. (US 2008/0023796 A1; hereafter Mita) in view of Tang et al. (US 6,245,607 B1; hereafter Tang).
Regarding claim 1, Mita teaches a transistor device (see e.g., lateral PNP transistor, Figure 1) having:
a collector region provided by a first region of semiconductor of a first type (see e.g., the lateral PNP transistor 1 includes p-type diffusion layers 8 and 9 used as collector regions formed in the n-type epitaxial layer 4, Para [0023], Figure 1); a collector terminal associated with the collector region (see e.g., collector electrodes 15 and 17 associated with the collector regions 8 and 9, Para [0030], Figure 1);
an emitter region provided by a second region of semiconductor of the first type (see e.g., the lateral PNP transistor 1 includes a p-type diffusion layer 7 used as an emitter region formed in the n-type epitaxial layer 4, Para [0023], Figure 1); an emitter terminal associated with the emitter region (see e.g., emitter electrode 16 associated with the emitter region 7, Para [0030], Figure 1);
a base region provided by a third region of semiconductor lying between and interfacing with both the collector region and emitter region (see e.g., portion of the n-type epitaxial layer 4 in-between the collector and emitter regions having an n-type diffusion layer 6 used as a base leading region, Para [0023], Figure 1); a base terminal associated with the base region (see e.g., base electrode 18 associated with the base region, Para [0030], Figure 1);
wherein the base region includes:
a sub-region of semiconductor of a second type; and (see e.g., portion of the n-type epitaxial layer 4 in-between the collector and emitter regions having an n-type diffusion layer 6 used as a base leading region, Para [0023], Figure 1)
wherein the base terminal contacts the sub-region (see e.g., the base electrode 18 contacts the n-type diffusion layer 6 used as a base leading region, Para [0023], Figure 1);
the sub-region …. interfaces with both the emitter region and the collector region to form further diode junctions (see e.g., the portion of n-type epitaxial layer 4 between the collector and emitter regions forms junction diodes as the base region has doping opposite to that of the collector and emitter regions, Figure 1);
there is a lateral separation between the collector and the emitter (see e.g., the lateral separation between the collector regions 8 and 9 and, the emitter region 7 is small in order to minimize device size, Para [0045], Figure 1);
the sub-region lies in a semiconductor substrate layer of the first type (see e.g., the base region that is, portion of n-type epitaxial layer 4 between the collector regions 8 and 9 and, emitter region 7 lies in a p-type single crystal silicon substrate 3, Para [0023], Figure 1).
wherein the sub-region of the base region comprises a first portion and a second portion; and (see e.g., the first portion including n-type diffusion layer 6 and the second portion including the n-type epitaxial layer 4 between the collector regions 8 and 9, emitter region 7, Figure 1):
Mita does not explicitly teach
“a channel of semiconductor of the first type;
the sub-region interfaces with the channel to provide a first diode junction,
the channel interfaces with and interconnects the collector region and the emitter region;
the net doping concentration of the channel is less than the net doping concentration of the emitter and collector regions; and
the channel has a depth of less than or equal to 0.25 micron extending orthogonally from the first diode junction;
there is a lateral separation between the collector and the emitter that is less than or equal to 1.5 microns, and the emitter region, the channel, and collector region are configured as a lateral transistor;
wherein the net doping concentration of the channel is less than or equal 0.1 times the net doping concentration of the second portion of the sub-region.”
In a similar field of endeavor Tang teaches
a channel of semiconductor of the first type (see e.g., a low concentration buried channel 175 formed of the same conductivity type as the emitter 115 and collector 120, establishing a low resistivity conduction path between collector and emitter. This channel is implanted to a depth of approximatively 50nm from the substrate surface with a dopant concentration of approximately 5.times.10.sup.17 electrons/cm.sup.3, Column 3, Lines 27-40, Figure 3a);
the sub-region interfaces with the channel to provide a first diode junction (see e.g., the buried channel 175 directly interfaces with the oppositely doped base region 110 thereby forming a PN diode junction, Figure 3a),
the channel interfaces with and interconnects the collector region and the emitter region (see e.g., the buried channel 175 extends laterally between and interconnects emitter 115 and collector 120 to provide a low resistivity conduction path therebetween, Figure 3a);
the net doping concentration of the channel is less than the net doping concentration of the emitter and collector regions; and (see e.g., The emitter 115 and collector 120 are implanted with the material of the second conductivity type to a concentration of from approximately 1.times.10.sup.20 electrons/cm.sup.3 to approximately 5.times.10.sup.20 electrons/cm.sup.3. The buried channel 175 is implanted to a concentration of approximately 5.times.10.sup.17 electrons/cm.sup.3. The net doping concentration of the buried channel 175 is less than the net doping concentration of emitter and collector, Column 3, Lines 16-26, Figure 3a)
the channel has a depth of less than or equal to 0.25 micron extending orthogonally from the first diode junction (see e.g., the buried channel 175 is implanted to a depth of approximately 50nm from the surface of the substrate, Column 3, Lines 26-40, Figure 3a);
there is a lateral separation between the collector and the emitter that is less than or equal to 1.5 microns (see e.g., the distance between the emitter 115 and collector 120 is less than 1µm, Column 4, Lines 9-11, Figure 3), and the emitter region, the channel, and collector region are configured as a lateral transistor (see e.g., the emitter 115, buried channel 175 and collector 120 are configured as a lateral transistor. The buried channel 175 provides a conduction path between the emitter 115 and the collector 120.
With respect to gate 130, the buried channel 175 is not a gate induced inversion layer. Rather, the buried channel 175 is a physically implanted semiconductor region. As shown in Figure 3C when the gate and base voltages are both zero, a built-in potential barrier remains and when the gate and base voltages are increased together the built in potential barrier decreases. The transistor remains a buried channel device regardless of gate biasing. Thus, the gate bias alters the built in potential barrier and current through the already existing buried channel rather than creating the channel itself. The biasing voltage source may be brought to zero volts and gate terminal 145 connected directly to base terminal 150. Therefore, operation may be performed without independently biased fourth gate terminal, Column 7, Lines 3-24, Column 8, Lines 28-38, Figure 3a);
wherein the net doping concentration of the channel is less than or equal 0.1 times the net doping concentration of the second portion of the sub-region (see e.g., The buried channel is implanted with a concentration of from approximately 1.times.10.sup.17 electrons/cm.sup.3 to approximately 1.times.10.sup.18 electrons/cm.sup.3, preferably 5.times.10.sup.17 electrons/cm.sup.3. The base region 110 is implanted to a concentration of from approximately 1.times.10.sup.16 holes/cm.sup.3 to approximately 2.times.10.sup.17 holes/cm.sup.3, preferably 1.times.10.sup.17 holes/cm.sup.3. In the scenario the buried channel 175 has a concentration of approximately 1.times.10.sup.17 electrons/cm.sup.3 and the base region 110 has a concentration of approximately 2.times.10.sup.17 holes/cm.sup.3, the net doping concentration of buried channel 175 would be less than the net doping concentration of base region 110, Column 7, Lines 25-36, Figure 3a).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tang’s teachings of a channel of semiconductor of the first type; the sub-region interfaces with the channel to provide a first diode junction, the channel interfaces with and interconnects the collector region and the emitter region; the net doping concentration of the channel is less than the net doping concentration of the emitter and collector regions; and the channel has a depth of less than or equal to 0.25 micron extending orthogonally from the first diode junction; there is a lateral separation between the collector and the emitter that is less than or equal to 1.5 microns, and the emitter region, the channel, and collector region are configured as a lateral transistor; wherein the net doping concentration of the channel is less than or equal 0.1 times the net doping concentration of the second portion of the sub-region in the device of Mita to provide a low resistivity path between the emitter and collector and thereby improve carrier transport and high frequency operation.
Regarding claim 4, Mita, as modified by Tang, teaches the limitations of claim 1 as mentioned above. Mita further teaches
wherein the first portion has a higher net doping concentration than the second portion (see e.g., n-type diffusion layer 6 is heavily doped than the n-type epitaxial layer 4, Figure 1);
the base terminal electrically connects to the second portion through the first portion (see e.g., the base electrode 18 connects to the n-type epitaxial layer 4 through the n-type diffusion layer 6, figure 1); interfaces with both the emitter region and the collector region to form the further diode junctions (see e.g. the n-type epitaxial layer 4 interfaces with the collector regions 8 and 9 and, emitter region 7 to inherently form junction diodes due to opposing doping, Figure 1).
Mita does not explicitly teach
“in which the second portion interfaces with the channel to provide the first diode junction,”
In a similar field of endeavor Tang teaches
in which the second portion interfaces with the channel to provide the first diode junction (see e.g., buried channel 175 of first conductivity type interfaces with the oppositely doped base region 110 of a second conductivity type. Accordingly, the interface between the buried channel 175 and the surrounding base 110 forms a PN junction, Figure 3a).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tang’s teachings of in which the second portion interfaces with the channel to provide the first diode junction in the Mita to predictably improve carrier transport and high frequency performance of the lateral transistor while preserving control of the channel by the oppositely doped base region.
Regarding claim 5, Mita, as modified by Tang, teaches the limitations of claim 4 as mentioned above. Mita does not explicitly teach
“wherein the net doping concentration of the channel is less than or equal to one times the net doping concentration of second portion of the sub-region”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Tang teaches
wherein the net doping concentration of the channel is less than or equal to one times the net doping concentration of second portion of the sub-region (see e.g., The buried channel is implanted with a concentration of from approximately 1.times.10.sup.17 electrons/cm.sup.3 to approximately 1.times.10.sup.18 electrons/cm.sup.3, preferably 5.times.10.sup.17 electrons/cm.sup.3. The base region 110 is implanted to a concentration of from approximately 1.times.10.sup.16 holes/cm.sup.3 to approximately 2.times.10.sup.17 holes/cm.sup.3, preferably 1.times.10.sup.17 holes/cm.sup.3. In the scenario the buried channel 175 has a concentration of approximately 1.times.10.sup.17 electrons/cm.sup.3 and the base region 110 has a concentration of approximately 1.times.10.sup.17 holes/cm.sup.3, the net doping concentration of buried channel 175 would be equal to the net doping concentration of base region 110, Column 7, Lines 25-36, Figure 3a).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tang’s teachings of wherein the net doping concentration of the channel is less than or equal to one times the net doping concentration of second portion of the sub-region in the device of Mita in order to optimize the transistor operation and obtain desired buried channel operation.
Regarding claim 7, Mita, as modified by Tang, teaches the limitations of claim 5 as mentioned above. Mita does not explicitly teach
“wherein the second portion of the sub-region of the base has a net doping concentration of between 5e16/cm3 to 5e17/cm3”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Tang teaches
wherein the second portion of the sub-region of the base has a net doping concentration of between 5e16/cm3 to 5e17/cm3 (see e.g., The base region 110 is implanted to a concentration of from approximately 1.times.10.sup.16 holes/cm.sup.3 to approximately 2.times.10.sup.17 holes/cm.sup.3, preferably 1.times.10.sup.17 holes/cm.sup.3., Column 7, Lines 25-36, Figure 3a).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tang’s teachings of wherein the second portion of the sub-region of the base has a net doping concentration of between 5e16/cm3 to 5e17/cm3 in the device of Mita as this would have amounted to routine optimization of a known result effective semiconductor doping parameter to obtain desired junction potential barrier and carrier transport characteristics.
Regarding claim 9, Mita, as modified by Tang, teaches the limitations of claim 1 as mentioned above. Mita further teaches
wherein the sub- region is provided in a semiconductor substrate layer of the first type (see e.g., the n-type epitaxial layer 4 and the n-type diffusion layer 6 are provided in the p-type single crystal silicon substrate 3, Para [0023], Figure 1), and the device further comprises a highly doped region of the second type of semiconductor that lies between and separates the second portion of the sub-region from the substrate (see e.g., n-type buried diffusion layer 5 separates the n-type epitaxial layer 4 from the p-type substrate 3, Figure 1); the highly doped region having a high net doping concentration compared with the second portion of the sub-region (see e.g., the n-type diffusion layer 5 is heavily doped as compared to the n-type epitaxial layer 4, Figure 1).
Regarding claim 20, Mita teaches a transistor device (see e.g., lateral PNP transistor, Figure 1) having:
a collector region provided by a first region of semiconductor of a first type (see e.g., the lateral PNP transistor 1 includes p-type diffusion layers 8 and 9 used as collector regions formed in the n-type epitaxial layer 4, Para [0023], Figure 1); a collector terminal associated with the collector region (see e.g., collector electrodes 15 and 17 associated with the collector regions 8 and 9, Para [0030], Figure 1);
an emitter region provided by a second region of semiconductor of the first type (see e.g., the lateral PNP transistor 1 includes a p-type diffusion layer 7 used as an emitter region formed in the n-type epitaxial layer 4, Para [0023], Figure 1); an emitter terminal associated with the emitter region (see e.g., emitter electrode 16 associated with the emitter region 7, Para [0030], Figure 1);
a base region provided by a third region of semiconductor lying between and interfacing with both the collector region and emitter region (see e.g., portion of the n-type epitaxial layer 4 in-between the collector and emitter regions having an n-type diffusion layer 6 used as a base leading region, Para [0023], Figure 1); a base terminal associated with the base region (see e.g., base electrode 18 associated with the base region, Para [0030], Figure 1);
wherein the base region includes:
a sub-region of semiconductor of a second type; and (see e.g., portion of the n-type epitaxial layer 4 in-between the collector and emitter regions having an n-type diffusion layer 6 used as a base leading region, Para [0023], Figure 1)
wherein the base terminal contacts the sub-region (see e.g., the base electrode 18 contacts the n-type diffusion layer 6 used as a base leading region, Para [0023], Figure 1);
there is a lateral separation between the collector and the emitter (see e.g., the separation between the collector regions 8 and 9 and, the emitter region 7 is small in order to minimize device size, Para [0045], Figure 1)
the sub-region lies in a semiconductor substrate layer of the first type (see e.g., the base region that is, portion of n-type epitaxial layer 4 between the collector regions 8 and 9 and, emitter region 7 lies in a p-type single crystal silicon substrate 3, Para [0023], Figure 1);
wherein the sub-region of the base region comprises a first portion and a second portion; and (see e.g., the first portion including n-type diffusion layer 6 and the second portion including the n-type epitaxial layer 4 between the collector regions 8 and 9, emitter region 7, Figure 1)
Mita does not explicitly teach
“a channel of semiconductor of the first type, and interfaces with and interconnects the collector region and the emitter region;
the sub-region interfaces with the channel to provide a first diode junction;
the net doping concentration of the channel is less than the net doping concentration of the emitter and collector regions;
the channel has a depth of less than or equal to 0.25 micron extending orthogonally from the first diode junction;
there is a lateral separation between the collector and the emitter that is less than or equal to 1.5 microns, and the emitter region, the channel, and collector region are configured as a lateral transistor;
wherein the net doping concentration of the channel is less than or equal 0.1 times the net doping concentration of the second portion of the sub-region.”
In a similar field of endeavor Tang teaches
a channel of semiconductor of the first type (see e.g., a low concentration buried channel 175 formed of the same conductivity type as the emitter 115 and collector 120, establishing a low resistivity conduction path between collector and emitter. This channel is implanted to a depth of approximatively 50nm from the substrate surface with a dopant concentration of approximately 5.times.10.sup.17 electrons/cm.sup.3, Column 3, Lines 27-40, Figure 3a), and which interfaces with and interconnects the collector region and the emitter region (see e.g., the buried channel 175 extends laterally between and interconnects emitter 115 and collector 120 to provide a low resistivity conduction path therebetween, Figure 3a);
the sub-region interfaces with the channel to provide a first diode junction (see e.g., the buried channel 175 directly interfaces with the oppositely doped base region 110 thereby forming a PN diode junction, Figure 3a),
the net doping concentration of the channel is less than the net doping concentration of the emitter and collector regions; and (see e.g., The emitter 115 and collector 120 are implanted with the material of the second conductivity type to a concentration of from approximately 1.times.10.sup.20 electrons/cm.sup.3 to approximately 5.times.10.sup.20 electrons/cm.sup.3. The buried channel 175 is implanted to a concentration of approximately 5.times.10.sup.17 electrons/cm.sup.3. The net doping concentration of the buried channel 175 is less than the net doping concentration of emitter and collector, Column 3, Lines 16-26, Figure 3a)
the channel has a depth of less than or equal to 0.25 micron extending orthogonally from the first diode junction (see e.g., the buried channel 175 is implanted to a depth of approximately 50nm from the surface of the substrate, Column 3, Lines 26-40, Figure 3a);
there is a lateral separation between the collector and the emitter that is less than or equal to 1.5 microns (see e.g., the distance between the emitter 115 and collector 120 is less than 1µm, Column 4, Lines 9-11, Figure 3), and the emitter region, the channel, and collector region are configured as a lateral transistor (see e.g., the emitter 115, buried channel 175 and collector 120 are configured as a lateral transistor. The buried channel 175 provides a conduction path between the emitter 115 and the collector 120.
With respect to gate 130, the buried channel 175 is not a gate induced inversion layer. Rather, the buried channel 175 is a physically implanted semiconductor region. As shown in Figure 3C when the gate and base voltages are both zero, a built-in potential barrier remains and when the gate and base voltages are increased together the built in potential barrier decreases. The transistor remains a buried channel device regardless of gate biasing. Thus, the gate bias alters the built in potential barrier and current through the already existing buried channel rather than creating the channel itself. The biasing voltage source may be brought to zero volts and gate terminal 145 connected directly to base terminal 150. Therefore, operation may be performed without independently biased fourth gate terminal, Column 7, Lines 3-24, Column 8, Lines 28-38, Figure 3a);
wherein the net doping concentration of the channel is less than or equal 0.1 times the net doping concentration of the second portion of the sub-region (see e.g., The buried channel is implanted with a concentration of from approximately 1.times.10.sup.17 electrons/cm.sup.3 to approximately 1.times.10.sup.18 electrons/cm.sup.3, preferably 5.times.10.sup.17 electrons/cm.sup.3. The base region 110 is implanted to a concentration of from approximately 1.times.10.sup.16 holes/cm.sup.3 to approximately 2.times.10.sup.17 holes/cm.sup.3, preferably 1.times.10.sup.17 holes/cm.sup.3. In the scenario the buried channel 175 has a concentration of approximately 1.times.10.sup.17 electrons/cm.sup.3 and the base region 110 has a concentration of approximately 2.times.10.sup.17 holes/cm.sup.3, the net doping concentration of buried channel 175 would be less than the net doping concentration of base region 110, Column 7, Lines 25-36, Figure 3a).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tang’s teachings of a channel of semiconductor of the first type, and interfaces with and interconnects the collector region and the emitter region; the sub-region interfaces with the channel to provide a first diode junction; the net doping concentration of the channel is less than the net doping concentration of the emitter and collector regions; the channel has a depth of less than or equal to 0.25 micron extending orthogonally from the first diode junction; there is a lateral separation between the collector and the emitter that is less than or equal to 1.5 microns, and the emitter region, the channel, and collector region are configured as a lateral transistor; wherein the net doping concentration of the channel is less than or equal 0.1 times the net doping concentration of the second portion of the sub-region in the device of Mita to provide a low resistivity path between the emitter and collector and thereby improve carrier transport and high frequency operation.
Regarding claims 21 and 22, Mita, as modified by Tang, teaches the limitations of claim 20 and claim 1 as mentioned above. Mita does not explicitly teach
“wherein a lateral spacing between the collector and the emitter is selected by a circuit design for an anticipated nominal operating voltage range Vce for the transistor device to operate as a normally ON or normally OFF device”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Tang teaches that the geometric distance between the collector and emitter is less than 1µm preferably less than 0.1µm. Thus, Tang establishes selecting a specific lateral emitter to collector spacing as part of the device geometry.
Tang further teaches that the electrical conduction state of the lateral transistor depends upon applied bias conditions. Tang teaches a biasing voltage range from 0V to 0.7V and states that a voltage substantially greater than 0.7V causes the base to emitter junction to turn the transistor completely ON. Increasing the applied bias lowers the built-in potential barrier and thereby increases conduction through the buried channel.
Consequently, Tang teaches a lateral transistor having a selected emitter to collector spacing where the conduction state is determined by the predictable relationship between the physical transistor structure and the applied voltages.
The claimed recitation, “selected by a circuit design for an anticipated nominal operating voltage range Vce for the transistor device to operate as a normally ON or normally OFF device”, constitutes a functional and design intent language. This language describes the intended operation or design objective of the device rather than an additional structural limitation. Because Tang teaches the claimed lateral spacing and further teaches that the conduction state of the transistor changes with the applied bias including conditions in which the transistor is completely ON, Tang fully satisfies this functional optimization.
Therefore, it would have been obvious to one skilled in art at the time the invention was effectively filed to select and configure the lateral emitter to collector spacing in view of an anticipated operating voltage range to achieve a desired conduction state and switching behavior. Such modification represents nothing more than the routine optimization of known transistor geometries and bias conditions to achieve predictable, desired ON/OFF operational characteristics.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mita et al. (US 2008/0023796 A1; hereafter Mita) in view of Tang et al. (US 6,245,607 B1; hereafter Tang) and further in view of Moksvold et al. (5,387,553; hereafter Moksvold).
Regarding claim 8, Mita, as modified by Tang, teaches the limitations of claim 7 as mentioned above. Mita does not explicitly teach
“wherein the first portion of the sub-region of the base has a net doping concentration greater or equal to le18/cm3”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Moksvold teaches
wherein the first portion of the sub-region of the base has a net doping concentration greater or equal to le18/cm3 (see e.g., the n+ 26 and n++ 54 base regions are heavily doped, having a dopant concentration in the range of 10.sup.18 -10.sup.19, Column 3, Lines 30-42, Figure 1F).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Moksvold’s teachings of wherein the first portion of the sub-region of the base has a net doping concentration greater or equal to le18/cm3 in the device of Mita in order to optimize the transistor operation by enhancing switching speed and reducing the on-resistance.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Mita et al. (US 2008/0023796 A1; hereafter Mita) in view of Tang et al. (US 6,245,607 B1; hereafter Tang) and further in view of Norstrom et al. (US 2005/0035412 A1; hereafter Norstrom).
Regarding claim 10, Mita, as modified by Tang, teaches the limitations of claim 1 as mentioned above. Mita does not explicitly teach
“wherein the emitter region and/or collector region are provided by a doped polysilicon layer provided on a silicon die that defines the base region.”
In a similar field of endeavor Norstrom teaches
wherein the emitter region and/or collector region are provided by a doped polysilicon layer provided on a silicon die that defines the base region (see e.g., for the PMOS/PNP transistor p-type source 198 constituting the emitter of the PNP transistor and drain 199 constituting the collector of the PNP transistor are p-type doped regions. A thin polysilicon silicon layer 151 is deposited on the emitter and collector regions. The purpose of the polysilicon layer is to serve as contacts for the emitter and collector. The polysilicon layer is doped to p-type, Paras [0052], [0053], [0071], Figure 9).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Norstrom’s teachings of wherein the emitter region and/or collector region are provided by a doped polysilicon layer provided on a silicon die that defines the base region in the device of Mita in order to provide low resistance contacts for the emitter and collector regions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
