Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I and Species II in the reply filed on 12/01/2025 is acknowledged. The traversal is on the ground(s) that examination of all the claims would not result in a serious search or examination burden. This is not found persuasive because a different field of search it is necessary to search for one of the inventions in a manner that IS not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries), a different field of search is shown, even though the two are classified together particularly different keyword searches are needed to search for the mutually exclusive limitation of the inventions and species. Furthermore applicant identified claims 1-12, 14, 16 and 18-20 as reading on the elected species however claim 16 requires “the first or second direction is parallel to a <110> direction of the second semiconductor substrate, and the transistor is a fin-type transistor having a fin sidewall that is a {100} plane of the second semiconductor substrate and having a channel direction non-parallel to the first and second directions” which is only described with respect to the embodiment of Fig. 15 paragraphs [0109]-[0113] as Fig. 11 shows describes the first and second substrates as being aligned so that claim 16 should be withdrawn.
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The requirement is still deemed proper and is therefore made FINAL.
Claims 13 and 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention or Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/01/2025.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SOLID-STATE IMAGING DEVICE WITH A PIXEL SEPARATION SECTION AND METHOD FOR MANUFACTURING THE SAME.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Ohura et. Al. (US 20200350346 A1 hereinafter Ohura).
Regarding claims 1 and 18, Ohura teaches in Figs. 4, 29 and 32 with associated text a solid-state imaging device comprising: a first substrate 70 including a first semiconductor substrate (Fig. 29, [0285]); a plurality of photoelectric conversion sections 71r provided in the first semiconductor substrate (Fig. 29, [0279]); and a pixel separation section 82r provided between the plurality of photoelectric conversion sections in the first semiconductor substrate (Figs. 4, 32 [0282] and [0286]), wherein an interface between a side surface of the pixel separation section and the first semiconductor substrate has a {100} plane ([0287]).
Regarding claims 2 and 19, Ohura teaches the pixel separation section includes an insulating film 85r (Fig. 29, [0113]) .
Regarding claim 3, Ohura teaches the pixel separation section further includes a light shielding film 74 (Fig. 29, [0194]).
Regarding claim 4, Ohura teaches the insulating film contains an element contained in the first semiconductor substrate and oxygen (the substrate is Si [0095] and the insulating film is SiO2 [0113]).
Regarding claims 5 and 20, Ohura teaches the insulating film includes a first portion having a first film thickness in plan view, and a second portion provided at a corner portion of the pixel separation section and having a second film thickness thicker than the first film thickness (see annotated Fig. below).
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Regarding claim 6, Ohura teaches the pixel separation section includes a plurality of first portions extending in a first direction parallel to a surface of the first semiconductor substrate in plan view, and a plurality of second portions extending in a second direction parallel to the surface of the first semiconductor substrate (see annotated Fig. below).
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Regarding claim 7, Ohura teaches the plan view corresponds to a state in which a light incident surface (bottom surface of 70) of the first semiconductor substrate is viewed ([101]).
Regarding claim 8, Ohura teaches the first or second direction is parallel to a <100> direction of the first semiconductor substrate (since the isolation trench surface is a (100) surface [0287], the material of the substrate is Si [0095] which is very well known in the art to have a diamond lattice with 90 degree symmetry and the first and second direction are 90 degrees apart (Fig. 32) the first or second direction is parallel to a <100> direction).
Regarding claim 9, Ohura teaches the pixel separation section is provided in a pixel separation groove penetrating the first semiconductor substrate (Fig. 29, [0106], [0113]).
Regarding claim 10, Ohura teaches the pixel separation section is provided in a pixel separation groove that does not penetrate the first semiconductor substrate (the groove does not extend all the way through the substrate Fig. 29 and therefore is interpreted to not penetrate the substrate).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ohura as applied to claim 1.
Regarding claim 11, Ohura teaches the solid-state imaging device according to claim 1, further comprising: a first insulating layer (interlayer insulating film of wiring layer 79) provided on a side opposite to a light incident surface of the first substrate (Fig. 29 and 23); and a second substrate 23412 including a second semiconductor substrate [0379] provided so as to face the first insulating layer, wherein the second substrate includes a transistor Tr (Fig. 50).
Ohura does not specify in the embodiment of Figs. 29 and 32 a second substrate including a second semiconductor substrate provided so as to face the first insulating layer, wherein the second substrate includes a transistor however Ohura teaches a similar device in the embodiment of Fig. 50 a second substrate 23412 including a second semiconductor substrate [0379] provided so as to face the first insulating layer, wherein the second substrate includes a transistor Tr (Fig. 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a second substrate as taught by Ohura in the embodiment of Figs 29 and 32 because according to Ohura such a second substrate is useful for signal processing performed in the logic die 23412 [0380] and so would be useful is a control structure to operate the imager die of the embodiment of Figs. 29 and 32.
Regarding claim 12, Ohura teaches the pixel separation section includes a plurality of first portions extending in a first direction parallel to a surface of the first semiconductor substrate in plan view, and a plurality of second portions extending in a second direction parallel to the surface of the first semiconductor substrate (see annotated Fig. above).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ohura as applied to claim 12 and further in view of Kim et. Al. (US 20220165768 A1 hereinafter Kim).
Regarding claim 14, Ohura teaches the solid-state imaging device according to claim 12, further comprising: a first insulating layer (interlayer insulating film of wiring layer 79) provided on a side opposite to a light incident surface of the first substrate (Fig. 29 and 23); and a second substrate 23412 including a second semiconductor substrate [0379] provided so as to face the first insulating layer, wherein the second substrate includes a transistor Tr (Fig. 50).
Ohura does not specify the first or second direction is parallel to a <100> direction of the second semiconductor substrate, and the transistor is a fin-type transistor having a fin sidewall that is a {100} plane of the second semiconductor substrate and having a channel direction parallel to the first or second direction however Ohura teaches the first or second direction is parallel to a <100> direction of the first semiconductor substrate (since the isolation trench surface is a (100) surface [0287], the material of the substrate is Si [0095] which is very well known in the art to have a diamond lattice with 90 degree symmetry and the first and second direction are 90 degrees apart (Fig. 32) the first or second direction is parallel to a <100> direction) it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to simply align the first and second substrate so that any alignment identifying notches or other direction identifying features overlap and all the other space is utilized.
Kim teaches in Fig. 2C with associated text a transistor is a fin-type transistor (110 and 150) having a fin sidewall that is a {100} plane of the second semiconductor substrate [0066] so that by using such a transistor for those of Ohura a channel direction parallel would be to the first or second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a finfet similar to that taught by Kim because according to Kim an inclined recess R′ may be introduced to select a crystal plane having fewer defects such as a (100) plane.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897