Detailed Action
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohura et. Al. (US 20200350346 A1 hereinafter Ohura) and further in view of Mori et. Al. (US 20100133592 A1 hereinafter Mori).
Regarding claims 1 and 18, Ohura teaches in Figs. 3-4 and 29 with associated text a solid-state imaging device comprising: a first substrate 70 including a first semiconductor substrate (Fig. 29, [0285]); a plurality of photoelectric conversion sections 71r provided in the first semiconductor substrate (Fig. 29, [0279]); wherein the plurality of photoelectric conversion sections are arranged in a two-dimensional array along a first direction and a second direction (horizontal and vertical directions of Fig. 4, [0116]); and a pixel separation section 82r provided between the plurality of photoelectric conversion sections in the first semiconductor substrate (Fig. 4, [0282] and [0286]), wherein the pixel separation section includes a plurality of first portions (horizontal portions) extending in the first direction, and a plurality of second portions (vertical portions) extending in the second direction (Fig. 4, [0116]).
Ohura does not specify in the embodiment of Figs. 3-4 and 29 an interface between a side surface of the pixel separation section and the first semiconductor substrate has a {100} plane however Ohura discloses in the embodiment of Fig. 32 making an interface between a side surface of the pixel separation section and the first semiconductor substrate has a {100} plane ([0287]) by rotating the pixel separation section only (Fig. 32).
Mori teaches in Fig. 4 arranging the photoelectric conversion sections and an interface between a side surface of the pixel separation section and the first semiconductor substrate along a {100} plane (Fig. 4, [0076])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make an interface between a side surface of the pixel separation section and the first semiconductor substrate have a {100} plane as taught by taught by Mori because according to Mori by using such a structure the stress near the interface of the element isolation section 13 can be reduced, and hence the dark current occurring near the element isolation section 13 can be reduced [0090].
Regarding claims 2 and 19, Ohura teaches the pixel separation section includes an insulating film 85r (Fig. 29, [0113]) .
Regarding claim 3, Ohura teaches the pixel separation section further includes a light shielding film 74 (Fig. 29, [0194]).
Regarding claim 4, Ohura teaches the insulating film contains an element contained in the first semiconductor substrate and oxygen (the substrate is Si [0095] and the insulating film is SiO2 [0113]).
Regarding claims 5 and 20, Ohura teaches the insulating film includes a first portion having a first film thickness in plan view (thickness in horizontal or vertical direction), and a second portion provided at a corner portion (thickness in a diagonal direction at the corner) of the pixel separation section and having a second film thickness thicker than the first film thickness (Fig. 4).
Regarding claim 6, Ohura teaches the pixel separation section includes a plurality of first portions extending in a first direction parallel to a surface of the first semiconductor substrate in plan view, and a plurality of second portions extending in a second direction parallel to the surface of the first semiconductor substrate (Fig. 4).
Regarding claim 7, Ohura teaches the plan view corresponds to a state in which a light incident surface (bottom surface of 70) of the first semiconductor substrate is viewed ([101]).
Regarding claim 8, Ohura teaches the first or second direction is parallel to a <100> direction of the first semiconductor substrate (since the isolation trench surface is a (100) surface [0287], the material of the substrate is Si [0095] which is very well known in the art to have a diamond lattice with 90 degree symmetry and the first and second direction are 90 degrees apart (Fig. 32) the first or second direction is parallel to a <100> direction).
Regarding claim 9, Ohura teaches the pixel separation section is provided in a pixel separation groove penetrating the first semiconductor substrate (Fig. 29, [0106], [0113]).
Regarding claim 10, Ohura teaches the pixel separation section is provided in a pixel separation groove that does not penetrate the first semiconductor substrate (the groove does not extend all the way through the substrate Fig. 29 and therefore is interpreted to not penetrate the substrate).
Regarding claim 11, Ohura in view of Mori teaches the solid-state imaging device according to claim 1, further comprising: a first insulating layer (interlayer insulating film of wiring layer 79) provided on a side opposite to a light incident surface of the first substrate (Fig. 29 and 23); and a second substrate 23412 including a second semiconductor substrate [0379] provided so as to face the first insulating layer, wherein the second substrate includes a transistor Tr (Fig. 50).
Ohura does not specify in the embodiment of Figs. 3-4 and 29 a second substrate including a second semiconductor substrate provided so as to face the first insulating layer, wherein the second substrate includes a transistor however Ohura teaches a similar device in the embodiment of Fig. 50 a second substrate 23412 including a second semiconductor substrate [0379] provided so as to face the first insulating layer, wherein the second substrate includes a transistor Tr (Fig. 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a second substrate as taught by Ohura in view of Mori in the embodiment of Figs 29 and 32 because according to Ohura such a second substrate is useful for signal processing performed in the logic die 23412 [0380] and so would be useful is a control structure to operate the imager die of the embodiment of Figs. 29 and 32.
Regarding claim 12, Ohura teaches the pixel separation section includes a plurality of first portions extending in a first direction parallel to a surface of the first semiconductor substrate in plan view, and a plurality of second portions extending in a second direction parallel to the surface of the first semiconductor substrate (see annotated Fig. above).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ohura in view of Mori as applied to claim 12 and further in view of Kim et. Al. (US 20220165768 A1 hereinafter Kim).
Regarding claim 14, Ohura in view of Mori teaches the solid-state imaging device according to claim 12, further comprising: a first insulating layer (interlayer insulating film of wiring layer 79) provided on a side opposite to a light incident surface of the first substrate (Fig. 29 and 23); and a second substrate 23412 including a second semiconductor substrate [0379] provided so as to face the first insulating layer, wherein the second substrate includes a transistor Tr (Fig. 50).
Ohura does not specify the first or second direction is parallel to a <100> direction of the second semiconductor substrate, and the transistor is a fin-type transistor having a fin sidewall that is a {100} plane of the second semiconductor substrate and having a channel direction parallel to the first or second direction however Ohura teaches the first or second direction is parallel to a <100> direction of the first semiconductor substrate (since the isolation trench surface is a (100) surface [0287], the material of the substrate is Si [0095] which is very well known in the art to have a diamond lattice with 90 degree symmetry and the first and second direction are 90 degrees apart (Fig. 32) the first or second direction is parallel to a <100> direction) it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to simply align the first and second substrate so that any alignment identifying notches or other direction identifying features overlap and all the other space is utilized.
Kim teaches in Fig. 2C with associated text a transistor is a fin-type transistor (110 and 150) having a fin sidewall that is a {100} plane of the second semiconductor substrate [0066] so that by using such a transistor for those of Ohura in view of Mori a channel direction parallel would be to the first or second direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a finfet similar to that taught by Kim because according to Kim an inclined recess R′ may be introduced to select a crystal plane having fewer defects such as a (100) plane.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12, 14 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. However regarding the arguments on page 10 Ohura teaches in the embodiment of Figs. 3-4 and 29 to teach the plurality of photoelectric conversion sections are arranged in a two-dimensional array along a first direction and a second direction (horizontal and vertical directions of Fig. 4, [0116]); and a pixel separation section 82r provided between the plurality of photoelectric conversion sections in the first semiconductor substrate (Fig. 4, [0282] and [0286]), wherein the pixel separation section includes a plurality of first portions (horizontal portions) extending in the first direction, and a plurality of second portions (vertical portions) extending in the second direction (Fig. 4, [0116]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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