DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/24/26 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 and 27-33 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over WO/2019/130702 (“Nakazawa”), published 7/4/19.
US 2021/0084249 A1 claims priority to PCT/JP2018/036417, which is published as WO/2019/130712; the US document will be referred to herein, being used as an English translation of the WO document.
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Nakazawa teaches, for example:
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Nakazawa teaches:
1. An imaging element 1, comprising:
pixels (e.g. 12, see e.g. Fig. 1) each disposed on a first semiconductor substrate (e.g. 10, and possibly further comprising elements or layers thereon, such as 40 and 50, see e.g. Fig. 19) and including
a photoelectric conversion section (e.g. “photodiode 41”, see e.g. para 125, 127) that performs photoelectric conversion of incident light,
a charge holding section (e.g. “floating diffusion FD”, see e.g. para 125) that holds a charge generated by the photoelectric conversion, and
a charge transfer section (e.g. “transfer transistor TR”, see e.g. para 125) that transfers the charge from the photoelectric conversion section to the charge holding section (the “transfer gate TG” of a transistor may transfer the charge, see e.g. para 127);
a pixel circuit (e.g. “readout circuit 22” including elements thereof and wirings connected thereto within 20, see e.g. para 121 and e.g. Fig. 19) that is disposed on a second semiconductor substrate (e.g. 20, see e.g. Fig. 19) stacked on a front surface side (e.g. top side of 10 as shown in Fig. 19) of the first semiconductor substrate and generates an image signal on a basis of the held charge (certainly 22 contributes to the image output, see e.g. para 121, 283, etc.);
an isolating section (e.g. comprising “element separator 43” and “insulating layer 46”, see e.g. para 132-133 and Fig. 19) disposed at a boundary of the pixels (see e.g. Fig. 19, wherein 43 is at the lateral sides of the pixel and wherein 46 is at the top side of the pixel);
a buried electrode (e.g. 73 and/or 74 in Fig. 35; or 72 and/or 71 in Fig. 32) that is disposed by being buried in the front surface side of the first semiconductor substrate at a boundary of the pixel overlapping with and connected to the isolating section (see e.g. Figs. 32 and 35); and
a first through-substrate electrode (the “first through-substrate electrode” may be reasonably interpreted as an electrode or wiring that passes through a portion of a substrate, and which may comprise multiple portions; at least 54 passes vertically through a portion of substrate 20, is connected to another 55 which passes laterally through substrate 20, which is connected to a circuit having elements 23, 24, 58, and 65, which pass through portions of substrates 20 and 30; in total, at least some of these elements comprise the claimed electrode) connected to the buried electrode (see e.g. Fig. 19, wherein at least 54 couples to FD; see also the discussion of the modification examples below),
wherein the first through-substrate electrode is coupled with a third semiconductor substrate (the electrode as identified above “couples” with a third substrate such as 30 in that they are connected or combined together or are in close proximity so as to permit mutual influence, which both read on the definition of couple shown below from Merriam Webster online dictionary) that is stacked on a side of the second semiconductor substrate different from the side on which the first semiconductor substrate is disposed (it is on the top, whereas 10 is on the bottom, see e.g. Fig. 19) and that includes a circuit connected to the pixel circuit (see e.g. logic circuit 32, see e.g. para 121).
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Figs. 32 and 35 are “modification examples” that replace portions of Fig. 19 (i.e. only the bottommost portions of 20 and the uppermost portions of 10), while not showing the entirety of unmodified parts of Fig. 19 (i.e. the upper portions of 20, all portions of 30, and the lowermost portions of 10 of Fig. 19). See for example, para 193, 198-200. As such, it seems that the modification falls within the scope of 35 USC 102 because the portions relied upon above are a single coherent embodiment.
In any case, the obviousness of the modification of Fig. 19 to replace portions near the bottom of 20 and the top of 10 to instead include the portions shown in Fig. 32 or Fig. 35 is well within the skill of one of ordinary skill in the art at the time of invention, and the above rejection is proper under 35 USC 103. It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Nakazawa teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
2. The imaging element according to claim 1, further comprising a boundary wiring line (see e.g. 54, 55, 72, etc. in Figs. 32-33; see e.g. VSS, 47, etc. in Fig. 35) disposed at the boundary of the pixels and connected to the buried electrode.
3. The imaging element according to claim 2, wherein the boundary wiring line is disposed by being buried in the first semiconductor substrate (see e.g. Figs. 33 and 35, wherein 72 and 74, respectively, may be said “boundary wiring lines”’ and/or wherein 54 and 47 partially extend, and are thus buried within, first substrate 10).
4. The imaging element according to claim 2, wherein the boundary wiring line is disposed adjacent to the front surface side of the first semiconductor substrate (see e.g. Figs. 33 and 35).
5. The imaging element according to claim 2, wherein the first through-substrate electrode is connected to the buried electrode via the boundary wiring line (see e.g. Figs. 33 and 35).
6. The imaging element according to 6, wherein the buried electrode is connected to a well region of the first semiconductor substrate (see wherein “well layer 42” is connected to 73/74/47/VSS in Fig. 35), and the first through-substrate electrode supplies a reference potential (see e.g. para 125, 127).
7. The imaging element according to claim 6, wherein the buried electrode is formed in a shape surrounding the pixel (see e.g. wherein 49/TG1/TG2/TG3/TG4 fully surrounds the pixel in Fig. 31; the line itself seems to “surround” at least two portions of the pixel; see also Fig. 33).
8. The imaging element according to claim 6, wherein a plurality of the pixels are disposed on the first semiconductor substrate (see e.g. Fig. 1).
9. The imaging element according to claim 8, wherein the buried electrode is commonly connected to the well region (e.g. see Fig. 35 wherein the buried electrode touches at least four “well layers 42”; see also Fig. 33; see also Fig. 32, wherein the buried electrode contacts at least four FD regions, which each would in turn connect to each “well layer 42” shown in Fig. 19 but which is omitted from the partial views shown in Figs. 32 and 35) of each pixel of a pixel group including two or more pixels among the plurality of pixels.
10. The imaging element according to claim 9, wherein the first through-substrate electrode is disposed for each of the pixel groups (see e.g. Figs. 31, 33, etc.).
11. The imaging element according to claim 8, wherein the first through-substrate electrode is disposed on the first semiconductor substrate outside the plurality of pixels (see e.g. Figs. 31, 33, etc.).
12. The imaging element according to claim 8, wherein the pixel circuit is disposed for each of pixel sharing units, each pixel sharing unit including two or more pixels among the plurality of pixels (see e.g. Figs. 31, 33, etc.).
13. The imaging element according to claim 12, further comprising: a second through-substrate electrode connected to the charge holding section; and a charge holding section wiring line disposed between the first semiconductor substrate and the second semiconductor substrate and connected in common to the second through-substrate electrode of each of the plurality of pixels included in the pixel sharing unit, wherein the charge holding section wiring line is connected to the pixel circuit (see e.g. Figs. 30-35).
14. The imaging element according to claim 12, further comprising: a charge transfer section wiring line that is disposed between the first semiconductor substrate and the second semiconductor substrate, transmits a control signal to the charge transfer section, and is commonly connected to the charge transfer sections of another piece of the pixel sharing units; and a second through-substrate electrode that is connected to the charge transfer section wiring line and supplies the control signal (see e.g. Figs. 30-35).
15. The imaging element according to claim 6, wherein the first through-substrate electrode is connected to a well region (see e.g. “well layer 42”, para 127, Figs. 19, 32, 35, etc.) in which an element of the pixel circuit is disposed, on the second semiconductor substrate.
16. The imaging element according to claim 6, wherein the buried electrode is formed in a band shape in plan view (see e.g. Figs. 31, 33).
17. The imaging element according to 17, wherein the buried electrode is connected to the charge holding section, and the first through-substrate electrode is connected to the pixel circuit (see e.g. Figs. 32, 35).
18. The imaging element according to 18, wherein a plurality of the pixels is disposed on the first semiconductor substrate, and the pixel circuit is disposed for each of pixel sharing units, each pixel sharing unit including two or more pixels among the plurality of pixels (see e.g. Figs. 1, 31, 33).
19. The imaging element according to claim 18, wherein the buried electrode is commonly connected to the charge holding section of each pixel in the pixel sharing unit (see e.g. Figs. 32, 35).
20. The imaging element according to 20, wherein the buried electrode is formed in a shape protruding from the first semiconductor substrate (see e.g. Figs. 32, 35, wherein at least a portion of 54 and 47 are partially within 10 and partially protruding out of 10 into 20), and the charge transfer section includes a MOS transistor 22 including a gate electrode having a height equal to or less than a protruding height of the buried electrode from the first semiconductor substrate (see e.g. Fig. 32).
21. The imaging element according to claim 6, wherein the first through-substrate electrode is connected to the well region (e.g. “well layer 42”) via a semiconductor region having (e.g. FD) formed on the first semiconductor substrate (see e.g. para 233, 241, etc.).
22. The imaging element according to claim 1, wherein the buried electrode includes silicon (see “polysilicon”, para 151).
23. The imaging element according to claim 1, wherein the isolating section has a shape penetrating the first semiconductor substrate (see e.g. Fig. 19).
24. The imaging element according to claim 1, wherein the isolating section is formed with an insulator (43 is made of e.g. “silicon oxide”, see para 133).
25. The imaging element according to claim 1, wherein the isolating section is formed with a semiconductor region (see “p-well layer 44”, para 44 and/or the “fixed electric charge film” 45).
27. The imaging element according to claim 1, wherein the charge transfer section is formed with a MOS transistor (see e.g. the RST, SEL, and SMP, see e.g. para 126-127) that includes: a channel region disposed in a protrusion formed on a front surface side of the first semiconductor substrate; and a gate electrode adjacent to a side surface of the protrusion via an insulating film (see e.g. insulating films like 21, 52 in 20), and that transfers the charge in a thickness direction of the first semiconductor substrate (see “CMOS” transistors, see e.g. para 127).
28. The imaging element according to claim 27, wherein the protrusion includes an annular groove shape on the front surface side of the first semiconductor substrate (e.g. see Figs. 31, 33).
29. The imaging element according to claim 27, wherein the gate electrode is formed in a shape surrounding (e.g. see Figs. 31, 33) a side surface of the protrusion.
30. The imaging element according to claim 27, wherein the charge holding section is disposed at an end of the protrusion (e.g. see Figs. 31, 33).
31. The imaging element according to claim 30, wherein the gate electrode is disposed to be separated from the charge holding section in a thickness direction of the first semiconductor substrate (e.g. see Figs. 19, 32, 35).
32. The imaging element according to claim 27, wherein the channel region is formed to have a conductivity type different from a conductivity type of a well region of the first semiconductor substrate (this is well-known in CMOS transistors, see e.g. para 127; because the channel region needs to be of a conductivity type opposite that of the source/drain electrodes for a channel to form).
33. An imaging device (e.g. 2, see e.g. Fig. 68 and para 281-282), comprising:
pixels (e.g. 12, see e.g. Fig. 1) each disposed on a first semiconductor substrate (e.g. 10, and possibly further comprising elements or layers thereon, such as 40 and 50, see e.g. Fig. 19) and including
a photoelectric conversion section (e.g. “photodiode 41”, see e.g. para 125, 127) that performs photoelectric conversion of incident light,
a charge holding section (e.g. “floating diffusion FD”, see e.g. para 125) that holds a charge generated by the photoelectric conversion, and
a charge transfer section (e.g. “transfer transistor TR”, see e.g. para 125) that transfers the charge from the photoelectric conversion section to the charge holding section (the “transfer gate TG” of a transistor may transfer the charge, see e.g. para 127);
a pixel circuit (e.g. “readout circuit 22” including elements thereof and wirings connected thereto within 20, see e.g. para 121 and e.g. Fig. 19) that is disposed on a second semiconductor substrate (e.g. 20, see e.g. Fig. 19) stacked on a front surface side (e.g. top side of 10 as shown in Fig. 19) of the first semiconductor substrate and generates an image signal on a basis of the held charge (certainly 22 contributes to the image output, see e.g. para 121, 283, etc.);
an isolating section (e.g. comprising “element separator 43” and “insulating layer 46”, see e.g. para 132-133 and Fig. 19) disposed at a boundary of the pixels (see e.g. Fig. 19, wherein 43 is at the lateral sides of the pixel and wherein 46 is at the top side of the pixel);
a buried electrode (e.g. 73 and/or 74 in Fig. 35; or 72 and/or 71 in Fig. 32) that is disposed by being buried in the front surface side of the first semiconductor substrate at a boundary of the pixel overlapping with and connected to the isolating section (see e.g. Figs. 32 and 35); and
a first through-substrate electrode (the “first through-substrate electrode” may be reasonably interpreted as an electrode or wiring that passes through a portion of a substrate, and which may comprise multiple portions; at least 54 passes vertically through a portion of substrate 20, is connected to another 55 which passes laterally through substrate 20, which is connected to a circuit having elements 23, 24, 58, and 65, which pass through portions of substrates 20 and 30; in total, at least some of these elements comprise the claimed electrode) connected to the buried electrode,
wherein the first through-substrate electrode is coupled with a third semiconductor substrate (the electrode as identified above “couples” with a third substrate such as 30 in that they are connected or combined together or are in close proximity so as to permit mutual influence, which both read on the definition of couple shown below from Merriam Webster online dictionary) that is stacked on a side of the second semiconductor substrate different from the side on which the first semiconductor substrate is disposed (it is on the top, whereas 10 is on the bottom, see e.g. Fig. 19) and that includes a circuit connected to the pixel circuit (see e.g. logic circuit 32, see e.g. para 121), and
a processing circuit that processes the generated image signal (see e.g. para 165, circuits in 30 in Fig. 1, etc.; see e.g. Fig. 68 and para 284, etc.).
Figs. 32 and 35 are “modification examples” that replace portions of Fig. 19 (i.e. only the bottommost portions of 20 and the uppermost portions of 10), while not showing the entirety of unmodified parts of Fig. 19 (i.e. the upper portions of 20, all portions of 30, and the lowermost portions of 10 of Fig. 19). See for example, para 193, 198-200. As such, it seems that the modification falls within the scope of 35 USC 102 because the portions relied upon above are a single coherent embodiment.
In any case, the obviousness of the modification of Fig. 19 to replace portions near the bottom of 20 and the top of 10 to instead include the portions shown in Fig. 32 or Fig. 35 is well within the skill of one of ordinary skill in the art at the time of invention, and the above rejection is proper under 35 USC 103. It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are not persuasive, being moot in view of the new ground(s) of rejection (see above how it is reasonable to interpret the claimed “isolating section” in a way that meets the newly amended limitations of claims 1 and 33, which Applicant argued that it did not [see 6/23/26 remarks, pages 10-11]).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2020/0105815 A1 (Huang”) shows imagers made from stacked substrates.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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