DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Request for Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/26, has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu (US 2017/0263833, cited on IDS and previously used) in view of Watanabe (US 2015/0263239, previously used).
a. Re claim 1, Chiu discloses a light emitting diode package comprising: a body 1 (see figs. 1-9 and related text; see remaining of disclosure for more details) comprising a substrate 11&13&14 ([0035]-[0037]) and a sidewall 12 formed on the substrate, the body being formed with a cavity 121 ([0035]) therein; and a light emitting diode chip 2 ([0034]) mounted on the substrate in the cavity of the body, wherein the sidewall comprises [multiple] inner side surfaces formed to surround the cavity (explicit on fig. 3), and the substrate comprises: an insulating base 11; a first interconnect pattern 133 formed on the base; a second interconnect pattern 131 spaced apart from the first interconnect pattern; and an insulating region (gap or space between 131 and 133) disposed inside the cavity to separate the first interconnect pattern from the second interconnect pattern. But Chiu does not appear to explicitly disclose the multiple inner side surfaces being at least 6, and each of the at least six inner side surfaces is substantially parallel to one other inner side surface of the at least six inner side surfaces, the inner side surfaces of the sidewall comprising (i.e. being) adjacent inner side surfaces forming an angle of more than 90 degrees therebetween.
However, Watanabe discloses light emitting devices wherein an octagonal-shaped opening (thus an opening with eight inner side surfaces 79d forming an angle of more than 90 degrees therebetween) of a sidewall 79 allows for a more effective utilization and enhanced condensation of light emitted from a light emitting device chip 1 (see figs. 23-24&25D and related text; especially [0078]).
As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided, via a non-inventive change in shape (see MPEP 2144.04.IV), the cavity to be octagonal shaped with straight vertical inner surfaces (thus preserving the straight vertical inner surfaces configuration), thus having eight inner side surfaces, and this in order to allow for a more effective utilization and enhanced condensation of light emitted from a light emitting diode chip 2.The modification would have resulted in each of the at least six inner side surfaces being substantially parallel to one other inner side surface (one that is opposite relatively to a vertical middle axis of the octagonal shaped cavity) of the at least six inner side surfaces, the inner side surfaces of the sidewall comprising (i.e. being) adjacent inner side surfaces forming an angle of more than 90 degrees therebetween.
b. Re claim 2, the sidewall comprises an even number (8) of inner side surfaces greater than (explicit as per claim 1 rejection above).
c. Re claim 3, the inner side surfaces of the sidewall comprise inner side surfaces facing each other and having a same length (this will be true for similar side surfaces facing each other).
d. Re claim 4, the inner side surfaces of the sidewall comprise inner side surfaces facing each other (explicit in view of claim 1 rejection above).
PNG
media_image1.png
597
879
media_image1.png
Greyscale
e. Re claim 5, an upper surface of the sidewall is divided into a plurality of regions A1-A8 (see annotated fig. 24 above), and some regions of the upper surface of the sidewall have different areas than other regions of the upper surface (explicit on annotated fig. 24).
f. Re claim 6, the light emitting diode package according to claim 1, further comprises: a lens 5 ([0047]) disposed on an upper surface of the sidewall and covering the cavity.
g. Re claim 7, the light emitting diode package according to claim 6, further comprises: a bonding agent 4 ([0047]) interposed between the lens and the upper surface of the sidewall, wherein the upper surface of the sidewall is divided into a plurality of regions A1-A8 (see annotated fig. 24 above), and some regions of the upper surface of the sidewall have different areas than other regions of the upper surface of the sidewall (explicit on annotated fig. 24).
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu (US 2017/0263833, cited on IDS) in view of Watanabe (US 2015/0263239), and further in view of Abe et al. (US 2016/0190413).
a. Re claim 9, Chiu in view of Watanabe disclose all the limitations of claim 1 as stated above except explicitly that for the light emitting diode package according to claim 1, further comprising: a short preventing portion formed on the second interconnect pattern between the light emitting diode chip and the insulating region.
However, Abe et al. discloses providing a recess defined by dam portions (see recess defined by dam portions 5 or dam portion 7 on lead 30 on figs. 2&4-5&20 and related text; see remaining of disclosure for more details), wherein the recess and dam portions are used to contain overflow of bonding material and prevent short-circuit (see at least [0119]-[0120]).
As such, and noting from [0040] of Chiu ‘833 that a silver paste is used to bond the LED chip to pad 131, and further noting from MPEP 2141.03 that “A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton” and that a “hypothetical ‘person having ordinary skill in the art’ to which the claimed subject matter pertains would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art.”, it would have been obvious to one skilled in the art before the effective filing date of the invention to have formed a recess surrounded by a dam in pad 131 in order to prevent the silver past from overflowing to short pad 131 to pads 132 and 133 (see MPEP 2143.E&G). The modification would have resulted in having the light emitting diode package according to claim 1 further comprising: a short preventing portion (recess and dam) formed on the second interconnect pattern between the light emitting diode chip and the insulating region (the dam or the recess would be at least partly between the light emitting diode chip and the insulating region).
b. Re claim 10, the short preventing portion is (at least in part) a groove (recess as per claim 9 rejection above) formed on the second interconnect pattern formed on an upper side of the insulating base.
c. Re claim 11, the short preventing portion is (at least in part) a dam (as per claim 9 rejection above) formed on the second interconnect pattern formed on an upper side of the base, and an upper surface of the dam is placed above an upper surface of the interconnect pattern (this would the case as per the modification in claim 9 rejection above, noting how the upper surface of dam 5 is above an upper surface of lead 30 in Abe et al. ‘413 and picturing a dam on the upper side of pad 131 in Chiu ‘833).
Claim(s) 1, 5 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayakawa et al. (US 2012/0286301, previously used) in view of Watanabe (US 2015/0263239).
a. Re claim 1, Kobayakawa et al. disclose a light emitting diode package comprising: a body 800 (see figs. 49-51 and related text; see [0322] and remaining of disclosure for more details) comprising a substrate 300 and a sidewall 600 formed on the substrate, the body being formed with a cavity (cavity within which 700 is disposed) therein; and a light emitting diode chip 200 mounted on the substrate in the cavity of the body, wherein the sidewall comprises [multiple] inner side surfaces formed to surround the cavity (explicit on figs. 49-50), and the substrate comprises: an insulating base 310 ([0302]); a first interconnect pattern 321 formed on the base; a second interconnect pattern 322 spaced apart from the first interconnect pattern (explicit on figs. 49-51); and an insulating region (space between 321 and 322) disposed inside the cavity to separate the first interconnect pattern from the second interconnect pattern. But Kobayakawa et al. do not appear to explicitly disclose the multiple inner side surfaces being at least 6, and each of the at least six inner side surfaces is substantially parallel to one other inner side surface of the at least six inner side surfaces, the inner side surfaces of the sidewall comprising adjacent inner side surfaces forming an angle of more than 90 degrees therebetween.
However, Watanabe discloses light emitting devices wherein an octagonal-shaped opening (thus an opening with eight inner side surfaces 79d forming an angle of more than 90 degrees therebetween) of a sidewall 79 allows for a more effective utilization and enhanced condensation of light emitted from a light emitting device chip 1 (see figs. 23-24&25D and related text; especially [0078]).
As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided, via a non-inventive change in shape (see MPEP 2144.04.IV), the cavity to be octagonal shaped with straight vertical inner surfaces (thus preserving the straight vertical inner surfaces configuration), thus having eight inner side surfaces, and this in order to allow for a more effective utilization and enhanced condensation of light emitted from a light emitting diode chip 200.The modification would have resulted in each of the at least six inner side surfaces being substantially parallel to one other inner side surface (one that is opposite relatively to a vertical middle axis of the octagonal shaped cavity) of the at least six inner side surfaces, the inner side surfaces of the sidewall comprising (i.e. being) adjacent inner side surfaces forming an angle of more than 90 degrees therebetween.
b. Re claim 5, an upper surface of the sidewall is divided into a plurality of regions A1-A8 (see annotated fig. 24 above), and some regions of the upper surface of the sidewall have different areas than other regions of the upper surface (explicit on annotated fig. 24).
c. Re claim 8, the insulating region comprises a first insulating region (wider vertical space between 321 and 322 on fig. 50) and a second insulating region (narrower vertical space between 321 and 322), the first insulating region having a greater length than the second insulating region (explicit on fig. 50) and being parallel to one side (left side of 200) of the light emitting diode chip, and the second insulating region being parallel to an other side (right side) of the light emitting diode chip. In the alternative, the insulating region comprises a first insulating region (horizontal space between 321 and 322 on fig. 50) and a second insulating region (narrower vertical space between 321 and 322), the first insulating region having a greater length than the second insulating region (explicit on fig. 50) and being parallel to one side (bottom side of 200 on fig. 50) of the light emitting diode chip, and the second insulating region being parallel to an other side (left side) of the light emitting diode chip.
Claim(s) 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toyama (US 2012/0112227, previously used) in view of Watanabe (US 2015/0263239, previously used).
a. Re claim 12, Toyama discloses a light emitting diode package comprising: a body 300 (see figs. 14-16 and related text; see remaining of disclosure for more details) comprising a substrate SUB (including the wirings thereon and therein; see annotated fig. 16 below) and a sidewall SDW formed on the substrate, the body being formed with a cavity 303 therein; and a light emitting diode chip 500 (unlabeled LED chip 500 on the lower left on fig. 15; see [0163]) mounted on the substrate in the cavity of the body, wherein the sidewall comprises at least [multiple] inner side surfaces 305 (explicit on figs. 15) formed to surround the cavity, and the substrate comprises: an insulating base (horizontal portion of 300 with top surface 301 and bottom surface 302); a first interconnect pattern 411 IP1 (see annotated fig. 15 below; see [0141]) formed on the base; a second interconnect pattern 412 IP2 ([0141]) spaced apart from the first interconnect pattern; an insulating region (gap or space between 411 IP1 and 412 IP2, or the space defined by 308 SPP and 306 around the unlabeled LED chip 500 bonded to pad 412 IP2 and the protruding portions of 412 IP2 and the unlabeled pad 411 on the left and right of said unlabeled LED chip 500 on annotated fig. 15) disposed inside the cavity to separate (at least in part) the first interconnect pattern from the second interconnect pattern; and a short preventing portion 308 SPP disposed (at least in part) between the light emitting diode chip and the insulating region (LEDs 500 are soldered or adhered adhesively to pads 411&412 with solder/adhesive 510; see fig. 14 and [0182]; as such, portion 308 SPP is implicitly a barrier for preventing any excess solder/adhesive 510 from electrically shorting pads 411 IP1 and 412 IP2 on annotated fig. 15 below; additionally 308 SPP is at least in part between the light emitting diode chip 500 and a portion of the space between 411 IP1 and 412 IP2 and therefore is between the light emitting diode chip and the insulating region). But Kobayakawa et al. do not appear to explicitly disclose the multiple inner side surfaces being at least 6, and each of the at least six inner side surfaces is substantially parallel to one other inner side surface of the at least six inner side surfaces.
However, Watanabe discloses light emitting devices wherein an octagonal-shaped opening (thus an opening with eight inner side surfaces 79d) of a sidewall 79 allows for a more effective utilization and enhanced condensation of light emitted from a light emitting device chip 1 (see figs. 23-24&25D and related text; especially [0078]).
As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided, via a non-inventive change in shape (see MPEP 2144.04.IV), the cavity to be octagonal shaped with straight vertical inner surfaces (thus preserving the straight vertical inner major surfaces configuration and also making the sidewalls at the corner portions also straight vertical as a non-inventive reshaping), thus having eight inner side surfaces, and this in order to allow for a more effective utilization and enhanced condensation of light emitted from a light emitting diode chip 500.The modification would have resulted in each of the at least six inner side surfaces being substantially parallel to one other inner side surface (one that is opposite relatively to a vertical middle axis of the octagonal shaped cavity) of the at least six inner side surfaces.
PNG
media_image2.png
784
1561
media_image2.png
Greyscale
PNG
media_image3.png
889
1182
media_image3.png
Greyscale
b. Re claim 13, the modification as per claim 12 rejection above would have resulted in the inner side surfaces of the sidewall comprising adjacent inner side surfaces forming an angle of more than 90 degrees therebetween (this is implicit in view of fig. 24&25D of Watanabe ‘239).
c. Re claim 14, the inner side surfaces of the sidewall comprise inner side surfaces facing each other and having a same length (this is true for similar inner side surfaces facing each other in an octagonal shaped cavity).
d. Re claim 15, the inner side surfaces of the sidewall comprise inner side surfaces facing each other and symmetrical to each other (explicit on fig. 15 or fig. 15 as modified in view of claim 12 rejection above to have an octagon shape).
e. Re claim 16, the insulating region (when it is the space defined by 308 SPP and 306 around the unlabeled LED chip 500 bonded to pad 412 IP2 and the protruding portions of 412IP2 and the unlabeled pad 411 on the left and right of said unlabeled LED chip 500 on annotated fig. 15) comprises a first insulating region IR1 (see annotated fig. 15) and a second insulating region IR2 (see annotated fig. 15), the first insulating region having a greater length than the second insulating region and being parallel to one side of the light emitting diode chip, and the second insulating region being parallel to an other side of the light emitting diode chip (explicit on annotated fig. 15).
f. Re claim 17, the short preventing portion comprises at least some region (i.e. portion) parallel to the first insulating region (explicit on annotated fig. 15 wherein a portion of 308 SPP is parallel to the short side of the first insulating region IR1).
g. Re claim 18, the short preventing portion comprises at least some region parallel to the second insulating region (explicit on annotated fig. 15).
h. Re claim 19, the short preventing portion has a groove shape or a dam shape (308 SPP is a dam and has a dam shape, i.e. its shape).
i. Re claim 20, the short preventing portion has a greater length than the insulating region (this is true when the insulation region is the gap or space between 411 IP1 and 411 IP2 for the lengths in a vertical direction of fig. 15).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because they do not apply to the rationale in the new ground of rejection above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899