DETAILED ACTION
This action is responsive to the amendment received on 02/25/2026 and the information disclosure statement received on 03/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in JAPAN on 01/06/2021.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 03/15/2026 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claim(s) 18-21 is/are objected to because of the following informalities where proposed corrections are bolded and underlined: Claim 18, lines 8-9, “outputs a pixel signal based on the electric signal” where the word “on” is missing.
The balance of claims are objected to at least for their dependencies. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 7, and 16-19 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2020/0273895 A1; Sasago et al.; 08/2020; (“Sasago”).
Regarding Claim 1. Sasago discloses A light receiving element (Figures 8A-8B and 9A-9C, photoelectric conversion apparatus, [0077]-[0087]), comprising:
a first substrate (#104, Figure 9A, first component) on which an avalanche photodiode (#11a-#11d, Figure 8B, [0029], Each unit pixel #11a-#11d includes an avalanche multiplication type diode made up at least partially of element #112 according to [0081]) that converts received light into an electric signal ([0077], device is a photoelectric conversion system) and at least one element is formed (Figures 7, 8B and 9A-9C, plurality of elements are formed in #104 such as transistors #13a, #13b, inverter circuits #16, quench element #18, wiring lines #121, etc.), the at least one element being included in a read circuit which outputs a pixel signal based on the electric signal ([0028], [0067]-[0068], and [0090], readout circuit including first wiring layer #121 is located in the read circuit which may output a pixel signal to the second logic component #204 in Figure 7); and
a second substrate (#204, Figure 9A, second component) on which a logic circuit is formed (Figures 7 and 9A, second component #204 includes a plurality of logic transistors), the logic circuit being a circuit that processes the pixel signal which is read from the avalanche photodiode (Figure 7, [0076], “PDOUT from the inverter circuit 16 is transmitted to the second component 204 and input to the inverter circuit 17”, i.e. the logic circuit receives the signal from the photodiode circuit),
wherein the first substrate and the second substrate are stacked (Figure 9A, #104 and #204 are stacked),
wherein the first substrate includes a first semiconductor substrate (#101, Figure 9A, first semiconductor substrate) and a first wiring layer (#107, Figure 9A, first wiring portion); and
wherein the at least one element is disposed completely in the first wiring layer (Figure 9A, #121 is disposed completely in the layer #107).
Regarding Claim 2. Sasago discloses The light receiving element according to claim 1,
wherein the second substrate includes a second semiconductor substrate (#201, Figure 9A, second semiconductor substrate) and a second wiring layer (#207, Figure 9A, second wiring portion),
wherein the first substrate and the second substrate are stacked by bonding the first wiring layer and the second wiring layer (Figure 9C, #104 and #204 are stacked by bonding #107 to #207 at #400), and
wherein the at least one element is disposed between the first semiconductor substrate and the second semiconductor substrate (Figures 8B and 9A, #121 disposed between #101 and #201).
Regarding Claim 4. Sasago discloses The light receiving element according to claim 1,
wherein the at least one element is disposed in a region in which at least a part of the at least one element overlaps with the avalanche photodiode in a plan view (Figures 8B and 9A, #121 at least partially overlaps with #111 and #112 of the photodiode in the side view of Figure 9A such that it necessarily at least partially overlaps in the plan view).
Regarding Claim 5. Sasago discloses The light receiving element according to claim 1,
wherein the at least one element is disposed at a position different from a position of the avalanche photodiode in a thickness direction of the first substrate (Figures 8B and 9A, #121 is at least partially disposed in a different position from #112/#111 of the photodiode in the thickness direction).
Regarding Claim 7. Sasago discloses The light receiving element according to claim 1,
wherein the first substrate includes a resistor as the at least one element ([0037], “PMOS transistor 13a is the quench element 18, and forms predetermined quenching resistance”, i.e. respective wiring lines of the source/drain regions of transistor #13a may be interpreted as resistors and #121 may therefore be interpreted as a resistor).
Regarding Claim 16. Sasago discloses The light receiving element according to claim 1, further comprising:
a light shielding layer disposed between the avalanche photodiode and the at least one element (the instant application discloses throughout that wiring layers of the element function as light shielding layers such as in [0132] of the instant application, Figures 8B and 9A of Sasago shows wiring layers of the elements overlapping one another over the diode regions #112 such that portions of the wiring layers which are electrically between the photodiode and #121 may be interpreted as a light shielding layer).
Regarding Claim 17. Sasago discloses The light receiving element according to claim 1,
wherein the read circuit is shared by a plurality of the avalanche photodiodes (Figures 8A and 8B, the read circuit region is shared by at least four neighboring pixels #11a-11d).
Regarding Claim 18. Sasago discloses A ranging system (#300, Figure 15, photoelectric conversion system including a distance measurement unit #316), comprising:
a lighting device that emits irradiation light (Figure 15B and [0110], system is on a vehicle which necessarily includes headlights which emit irradiation light); and
a light receiving element that receives reflected light of the irradiation light, the reflected light being obtained by being reflected by a predetermined object ([0109]-[0110], #300 receives light reflected off of targets in front, which may be light from the headlights, to monitor distance),
wherein the light receiving element (#310, photoelectric conversion apparatus which may be any of the previous embodiments according to [0109], let it be Figures 8A-8B and 9A-9C, photoelectric conversion apparatus, [0077]-[0087]) includes
a first substrate (#104, Figure 9A, first component) on which an avalanche photodiode (#11a-#11d, Figure 8B, [0029], Each unit pixel #11a-#11d includes an avalanche multiplication type diode made up at least partially of element #112 according to [0081]) that converts received light into an electric signal ([0077], device is a photoelectric conversion system) and at least one element are formed (Figures 7, 8B and 9A-9C, plurality of elements are formed in #104 such as transistors #13a, #13b, inverter circuits #16, quench element #18, wiring lines #121, etc.), the at least one element being included in a read circuit which outputs a pixel signal based on the electric signal ([0028], [0067]-[0068], and [0090], readout circuit including first wiring layer #121 is located in the read circuit which may output a pixel signal to the second logic component #204 in Figure 7); and
a second substrate (#204, Figure 9A, second component) on which a logic circuit is formed (Figures 7 and 9A, second component #204 includes a plurality of logic transistors), the logic circuit being a circuit that processes the pixel signal which is read from the avalanche photodiode (Figure 7, [0076], “PDOUT from the inverter circuit 16 is transmitted to the second component 204 and input to the inverter circuit 17”, i.e. the logic circuit receives the signal from the photodiode circuit),
wherein the first substrate and the second substrate are stacked (Figure 9A, #104 and #204 are stacked)
wherein the first substrate includes a first semiconductor substrate (#101, Figure 9A, first semiconductor substrate) and a first wiring layer (#107, Figure 9A, first wiring portion); and
wherein the at least one element is disposed completely in the first wiring layer (Figure 9A, #121 is disposed completely in the layer #107).
Regarding Claim 19. Sasago discloses The ranging system according to claim 18,
wherein the at least one element is disposed in a region in which at least a part of the at least one element overlaps with the avalanche photodiode in a plan view (Figures 8B and 9A, #121 at least partially overlaps with #111 and #112 of the photodiode in the side view of Figure 9A such that it necessarily at least partially overlaps in the plan view).
Allowable Subject Matter
Claim(s) 6, 8-15, and 20-21 is are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art, either alone or in combination, teaches that the at least one element disposed entirely in the first wiring layer (as required by claims 1 and 18) is specifically a diode (claim 6), a resistor and a diode (claim 8), a polysilicon TFT (claim 9), a MOS transistor (claim 10), a resistor, a diode, and a MOS transistor (claim 11), a MOS transistor as a constant current source (claim 12), a MOS transistor as a constant current source and an inverter (claim 13), a resistor, a diode, a MOS transistor as a clamp circuit, and a MOS transistor as a constant current source (claims 14 and 20); in combination with all of the other required limitations required by the claim. The current interpretation of the closest cited reference, Sasago, considers a wire as the “at least one element” and it is not considered by the examiner to be obvious to replace a wire with an active device such as a transistor. Claims 15 and 21 contain allowable subject matter at least for their dependencies on claims 14 and 20, respectively.
Response to Arguments/Amendments
Applicant’s amendments to the abstract and corresponding remarks, see page 7 of the remarks, filed 02/25/2026, with respect to the objection to the abstract have been fully considered and are persuasive. The objection to the abstract has been withdrawn.
Applicant’s amendments to claims 1 and 18 and corresponding remarks, see pages 7-9 of the remarks, filed 02/25/2026, with respect to the 35 U.S.C. 102 rejections of claims 1 and 18 have been fully considered but are not found persuasive. Applicant argues that the currently cited reference (US 2020/0273895 A1; Sasago et al.; 08/2020; (“Sasago”)) does not disclose that the at least one element is disposed completely in the first wiring layer as required by claims 1 and 18. In the original interpretation, from the non-final rejection mailed on 11/28/2025, the examiner interpreted the PMOS transistor (#13a) of Sasago as the first element and the applicant is correct that this interpretation does not read on the amendments as the transistor from Sasago is not disposed entirely in the first wiring layer. However, in view of the amendments, the examiner has modified their interpretation of Sasago such that the wiring layer ([0028], [0067]-[0068], and [0090], readout circuit including first wiring layer #121 is located in the read circuit which may output a pixel signal to the second logic component #204 in Figure 7) is interpreted as the at least one element and is disposed completely within the first wiring layer (Figure 9A, #121 is disposed completely in the layer #107). The use of the term “element” is sufficiently broad that even a wiring line may be interpreted as the required at least one element. Therefore, Sasago is interpreted to disclose all of the limitations of amended claims 1 and 18.
Claim(s) 1, 2, 4, 5, 7, and 16-19 stand rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2020/0273895 A1; Sasago et al.; 08/2020; (“Sasago”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TYLER J WIEGAND/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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