DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3-13,19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al (US Pub No. 20090243041), in view of Hu e t al (US Patent No. 10163680).
With respect to claim 1, Mueller et al discloses a substrate (108,106,Fig.1) and a device layer formed on the substrate ( where the contacts are formed); a trench isolation ring formed in the substrate on a backside (122,Fig.5, para 32, the top side is considered backside), the trench isolation ring comprising a conductive layer (140,Fig.15); a first insulating dielectric layer formed on a back side of the surface of the first wafer (146), the first insulating dielectric layer having at least one first through hole (148) and at least one second through hole (148) formed therein, the first through hole exposing a surface of the first metal layer (where 148 on the left is formed), the second through hole (148 the through hole on the right) exposing the surface of the backside of the substrate wherein the first insulating dielectric layer is present between the first through hole and the second through hole (Fig.19); a barrier layer formed at least on the surface of the first wafer exposed in the second through hole (143); and a second layer formed on the first insulating dielectric layer (148), the second metal layer filling up the first through hole and the second through hole (Fig.19). However, Mueller et al does not explicitly disclose that the first and the second conductive layers are made from metal. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller such that the first and the second conductive materials are made from metal such as copper because of it’s greater conductivity and the manufacturer would not need to have doping step incorporated in the process to decrease the resistivity of the silicon, thereby cutting time of the production.
However, Mueller does not explicitly disclose a bias voltage is applied and then transferred into the substrate by he second metal layer, resulting in a bias voltage present across the whole semiconductor device, because of the buried insulating material, and wherein the first wafer comprises a substrate. However, Hu et al discloses that instead of buried insulating material it has doped material; therefore, if the biased voltage is high enough is applied and then transferred into the substrate by the second metal layer, resulting in a bias voltage present across the whole semiconductor device. On the other hand, Hu et al uses buried doped region instead of SOI region (106,Fig.3). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller et al according to the teachings of the Hu et al such that buried layers are formed instead of dielectric material, thereby if the biased voltage is high enough is applied and then transferred into the substrate by the second metal layer, resulting in a bias voltage present across the whole semiconductor device, to cut the cost and be able to test the entire device. Furthermore, the arts cited above do not explicitly disclose and wherein the first wafer comprises a substrate. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that a wafer is used and the device mentioned above is formed on the wafer, in order to have other parts wafer to be used for other devices, thereby be able to mass manufacture multiple devices at the same time.
With respect to claim 3, Mueller et al discloses wherein the trench isolation ring further comprises a second insulating dielectric layer (138), the second insulating dielectric layer formed on side (Fig.19) and bottom surfaces (bottom corners) of the trench isolation ring in the first wafer, the trench filled up by the first metal layer (Fig.19).
With respect to claim 4, Mueller et al discloses wherein each of the first insulating dielectric layer and the second insulating dielectric layer, and wherein each of the first insulating dielectric layer and the second insulating dielectric layer is a single-layer structure (Fig.19) or a structure consisting of at least two laminated layers. However, Mueller et al does not explicitly disclose that the insulating material comprising at least one of silicon oxide and a high-k dielectric with a dielectric constant k greater than 3.9. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller et al such that silicon oxide is used as dielectric layers, because of it’s abundance in the industry, therefore new equipment would not be required.
With respect to claim 5, Mueller et al discloses wherein the trench isolation ring has a rectangular (Fig.18), hexagonal or octagonal transverse cross-section.
With respect to claim 6, Mueller et al discloses wherein the first through hole is located above a side (top side, 148 on the left) and/or a corner of the trench isolation ring, and the second through hole is located above the first wafer at a location closer to a side (left side) and/or a corner of the trench isolation ring (148 on the right).
With respect to claim 7, Mueller et al disclose further comprising a second wafer (104) bonded to the first wafer (Fig.19). With regards to limitation “bonded” “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
With respect to claim 19, the arts cited above do not explicitly disclose wherein the first metal layer comprises a metallic material selected from the group consisting of tungsten, aluminum, copper, silver, gold, and alloys thereof. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that tungsten is used as conductive material because it would not require any doping like polysilicon and it is readily available in the industry.
With respect to claim 20, Mueller et al discloses wherein the first insulating dielectric layer has a thickness (Fig.19), with respect to claim limitation “sufficient to block sputtered metal from the first metal layer during a dry etching process used to form the first and second through holes”, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
With respect to claim 8, Mueller et al discloses providing a substrate (108,106,Fig.1);and device layer formed on the substrate (Fig.1) forming a trench isolation ring in the first wafer (122,Fig.5, para 32), the trench isolation ring comprising a conductive layer (140,Fig.15); forming a first insulating dielectric layer formed on a backside of the substrate (146), the first insulating dielectric layer having at least one first through hole (148) and at least one second through hole (148) formed therein, the first through hole exposing a surface of the first metal layer (where 148 on the left is formed), the second through hole (148 the through hole on the right) exposing the surface of the first wafer; wherein the first insulating dielectric layer is present between the first through hole and the second through hole (Fig.19); forming a barrier layer formed at least on the surface of the first wafer exposed in the second through hole (143); and a second layer formed on the first insulating dielectric layer (148), the second metal layer filling up the first through hole and the second through hole (Fig.19). However, Mueller et al does not explicitly disclose that the first and the second conductive layers are made from metal. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller such that the first and the second conductive materials are made from metal such as copper because of it’s greater conductivity and the manufacturer would not need to have doping step incorporated in the process to decrease the resistivity of the silicon, thereby cutting time of the production.
However, Mueller does not explicitly disclose a bias voltage is applied and then transferred into the substrate by he second metal layer, resulting in a bias voltage present across the whole semiconductor device, because of the buried insulating material, and wherein the first wafer comprises a substrate. However, Hu et al discloses that instead of buried insulating material it has doped material; therefore, if the biased voltage is high enough is applied and then transferred into the substrate by the second metal layer, resulting in a bias voltage present across the whole semiconductor device. On the other hand, Hu et al uses buried doped region instead of SOI region (106,Fig.3). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller et al according to the teachings of the Hu et al such that buried layers are formed instead of dielectric material, thereby if the biased voltage is high enough is applied and then transferred into the substrate by the second metal layer, resulting in a bias voltage present across the whole semiconductor device, to cut the cost and be able to test the entire device. Furthermore, the arts cited above do not explicitly disclose and wherein the first wafer comprises a substrate. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that a wafer is used and the device mentioned above is formed on the wafer, in order to have other parts wafer to be used for other devices, thereby be able to mass manufacture multiple devices at the same time.
However, Mueller does not explicitly disclose a bias voltage is applied and then transferred into the substrate by he second metal layer, resulting in a bias voltage present across the whole semiconductor device, because of the buried insulating material, and wherein the first wafer comprises a substrate. However, Hu et al discloses that instead of buried insulating material it has doped material; therefore, if the biased voltage is high enough is applied and then transferred into the substrate by the second metal layer, resulting in a bias voltage present across the whole semiconductor device. On the other hand, Hu et al uses buried doped region instead of SOI region (106,Fig.3). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller et al according to the teachings of the Hu et al such that buried layers are formed instead of dielectric material, thereby if the biased voltage is high enough is applied and then transferred into the substrate by the second metal layer, resulting in a bias voltage present across the whole semiconductor device, to cut the cost and be able to test the entire device. Furthermore, the arts cited above do not explicitly disclose and wherein the first wafer comprises a substrate. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that a wafer is used and the device mentioned above is formed on the wafer, in order to have other parts wafer to be used for other devices, thereby be able to mass manufacture multiple devices at the same time.
With respect to claim 9, Mueller et al discloses wherein the first wafer comprises a substrate (108) and a device layer formed on the substrate (130), wherein the trench isolation ring is formed in the substrate on a backside of the first wafer (Fig.19), and the first insulating dielectric layer is formed on a backside of the substrate (Fig.19).
With respect to claim 10, Mueller et al discloses wherein the trench isolation ring further comprises a second insulating dielectric layer (138), the second insulating dielectric layer formed on side (Fig.19) and bottom surfaces (bottom corners) of the trench isolation ring in the first wafer, the trench filled up by the first metal layer (Fig.19).
With respect to claim 11, Mueller et al discloses wherein each of the first insulating dielectric layer and the second insulating dielectric layer, and wherein each of the first insulating dielectric layer and the second insulating dielectric layer is a single-layer structure (Fig.19) or a structure consisting of at least two laminated layers. However, Mueller et al does not explicitly disclose that the insulating material comprising at least one of silicon oxide and a high-k dielectric with a dielectric constant k greater than 3.9. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Mueller et al such that silicon oxide is used as dielectric layers, because of it’s abundance in the industry, therefore new equipment would not be required.
With respect to claim 12, Mueller et al discloses wherein the trench isolation ring has a rectangular (Fig.18), hexagonal or octagonal transverse cross-section.
With respect to claim 13, Mueller et al discloses wherein the first through hole is located above a side (top side, 148 on the left) and/or a corner of the trench isolation ring, and the second through hole is located above the first wafer at a location closer to a side (left side) and/or a corner of the trench isolation ring (148 on the right).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al (US Pub No. 20090243041), in view of Hu e t al (US Patent No. 10163680), in view of Chiu (US Patent No. 11031462)
With respect to claim 18, the arts cited above do not explicitly disclose wherein the device layer is disposed on a front side of the first wafer opposite the backside of the first wafer. On the other hand, Chiu discloses wherein the device layer (200,Fig.5B) is disposed on a front side of the first wafer (Fig.5B) opposite the backside of the first wafer (where trench is formed). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of the Chiu such that that trenches are formed on the back and the device on the front, in order to prevent parasitic capacitance on the devices.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,3-8,10-13,18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817
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