DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of embodiment 6 of fig. 11 and modification A3 of fig. 7 (claims 1, 2, 8, 20, 21 readable thereon, claims 3-7, 9-20, 22 withdrawn) in the reply filed on 11/3/2025 is acknowledged. The traversal is on the ground(s) that a search for all of the species and modification As would not be burdensome on the Examiner. This is not found persuasive because the arguments has not explicitly pointed out the deficiencies of the restriction requirement, such as whether the species are obvious variants or not. Further, the search did not result in finding all species and modifications, therefore this is evidence that there would be serious burden on the Examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8, 20, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kudymov et al. (US PGPub 2019/0096877; hereinafter “Kudymov”).
Re claim 1: Kudymov teaches (e.g. figs. 1B, 4B, and 5) a semiconductor device, comprising: an active region (active area of transistor 102, 402; e.g. paragraph 26; hereinafter “AR”) and a passive region (region of gate resistor 104,404; hereinafter “PR”) surrounding the active region (AR); wherein the semiconductor device further comprises: a substrate (420); a multi-layer semiconductor layer (422, 424) located on one side (top side of 420) of the substrate (420); and at least one shielding structure (414, 416, 418) located on one side (top side of 420) of the substrate (420), the shielding structure (414, 416, 418) being electrically connected to a preset potential (gate voltage applied to gate bus 412, 412 is connected to 414, 416, 418), for forming an electric field or a zero electric field of the active region (AR) pointing toward (MPEP 2112.01(i) states that when a prior art structure is substantially identical to that of the claimed structure, claimed properties are presumed to be present) the passive region (PR).
Re claim 2: Kudymov teaches the semiconductor device according to claim 1, comprising a working region (region of AR and PR; hereinafter “WR”) and a scribe region (region surrounding WR which is cut during the dicing process of singulating a processed wafer; hereinafter “SR”) surrounding the working region (WR), the working region (WR) comprising the active region (AR) and the passive region (PR); wherein the semiconductor device further comprises: at least one bonding pad (gate bus 112, 412; e.g. paragraph 26) located on one side of the multi-layer semiconductor layer (422, 424) away from the substrate (420), and located in the passive region (PR); and the shielding structure (214) is for shielding and protecting (MPEP 2112.01(i) states that when a prior art structure is substantially identical to that of the claimed structure, claimed properties are presumed to be present) the bonding pad (112, 212); and the preset potential is greater than or equal to 0.
Re claim 8: Kudymov teaches the semiconductor device according to claim 2, wherein the semiconductor device further comprises a gate (516; e.g. paragraph 57) located on one side of the multi-layer semiconductor layer (422,424,522,524) away from the substrate (420,520), and located in the active region (AR); and a drain (538; e.g. paragraph 57) located on one side of the multi-layer semiconductor layer (422,424) away from the substrate (420, 520), and located in the active region (AR), the bonding pad (112,412) comprises a gate bonding pad (112,412) electrically connected to the gate (516) and/or a drain bonding pad electrically connected to the drain (538; e.g. paragraph 57); and at least one shielding structure (412) comprises a gate shielding structure for shielding and protecting the gate bonding pad (112,412) and/or a drain shielding structure for shielding and protecting the drain bonding pad.
Re claim 20: Kudymov teaches the semiconductor device according to claim 1, wherein the shielding structure (414, 416, 418) comprises a first portion (414 as shown in fig. 1B, 4B; hereinafter “1P”) extending along a first direction (left right direction of fig. 1B; hereinafter “1D”) and a second portion (416, 418 as shown in fig. 1B, 4B; hereinafter “2P”) extending along a second direction (up down direction of fig. 1B; hereinafter “2D”), the first direction (1D) and the second direction (2D) both are parallel to the plane where the substrate (420) is located, and the first direction (1D) intersects the second direction (2D); the semiconductor device comprises a first boundary (see below for 1B) extending along the first direction (1D) and a second boundary (see below for 2B) extending along the second direction (2D); minimum distance L1 between the first portion (414) and the first boundary (some arbitrary boundary that extends in direction 1D within 30 microns of 414) satisfies L1>30 μm; and minimum distance L2 between the second portion (416, 418) and the second boundary (some arbitrary boundary that extends in direction 2D within 30 microns of 416, 418) satisfies L2>30 μm.
Re claim 21: Kudymov teaches the semiconductor device according to claim 1, wherein the shielding structure (414, 416, 418) comprises a first portion (414 as shown in fig. 1B, 4B; hereinafter “1P”) extending along a first direction (left right direction of fig. 1B; hereinafter “1D”) and a second portion (416, 418 as shown in fig. 1B, 4B; hereinafter “2P”) extending along a second direction (up down direction of fig. 1B; hereinafter “2D”), the first direction (1D) and the second direction (2D) both are parallel to the plane where the substrate (420) is located, and the first direction (1D) intersects the second direction (2D); extension width D1 of the first portion (414) in the second direction (2D) satisfies D1>10 μm; and extension width D2 of the second portion (416, 418) in the first direction (1D) satisfies D2>10 μm (the layers 412 and 416 extend beyond 10 microns since that is the thickness of 422; e.g. paragraph 31).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898