DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/20/2026 have been fully considered but they are not persuasive.
Applicant argues that the prior art of record is silent as to what Applicant refers to as feature A. Examiner respectfully disagrees. As recited at the 5th from last line of the claim, the “and/or” statement makes optional the claimed features, therefore feature A is not necessarily required.
Rejection is being maintained and the rejection below has been updated to include the amended portions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 20, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kudymov et al. (US PGPub 2019/0096877; hereinafter “Kudymov”).
Re claim 1: Kudymov teaches (e.g. figs. 1B, 4B, and 5) a semiconductor device, comprising a working region (region of active area of transistor 102, 402 and region of gate resistor 104,404; hereinafter “WR”) and a scribe region (region surrounding WR which is cut during the dicing process of singulating a processed wafer; hereinafter “SR”) surrounding the working region (WR), the working region (WR) comprising an active region (active area of transistor 102, 402; e.g. paragraph 26; hereinafter “AR”) and a passive region (region of gate resistor 104,404; hereinafter “PR”) surrounding the active region (AR); the semiconductor device further comprising: a substrate (420); a multi-layer semiconductor layer (422, 424) located on one side (top side of 420) of the substrate (420); and at least one shielding structure (414, 416, 418) located on one side (top side of 420) of the substrate (420); at least one bonding pad (gate bus 112, 412; e.g. paragraph 26) located on one side of the multi-layer semiconductor layer (422, 424) opposite the substrate (420), and located in the passive region (PR); a gate (gate array 116; e.g. paragraph 26) located on one side of the multi-layer semiconductor layer (422, 424) opposite the substrate (420), and located in the active region (AR); a drain (drain of transistor 102; e.g. paragraph 25) located on one side of the multi-layer semiconductor layer (422, 424) opposite the substrate (420), and located in the active region; a source (source of transistor 102; e.g. paragraph 25) located on one side of the multi-layer semiconductor layer (422, 424) opposite the substrate (420), and located in the active region (AR); the shielding structure is electrically connected to the source, for forming i) an electric field or ii) a zero electric field of the active region pointing toward the passive region, for shielding and protecting the bonding pad; wherein the multi-layer semiconductor layer comprises a conductive region located in the passive region and a two-dimensional electron gas elimination region, the two-dimensional electron gas elimination region is located between the conductive region as the shielding structure, and the active region; and/or wherein the semiconductor device further comprises a dielectric layer located on one side of the multi-layer semiconductor layer opposite the substrate, and at least one conductive trace as the shielding structure, located on one side of the dielectric layer opposite the multi-layer semiconductor layer.
Re claim 8: Kudymov teaches the semiconductor device according to claim 1, wherein the bonding pad (112,412) comprises a gate bonding pad (112,412) electrically connected to the gate (516) and/or a drain bonding pad electrically connected to the drain (538; e.g. paragraph 57); and wherein the at least one shielding structure (412) comprises a gate shielding structure for shielding and protecting the gate bonding pad (112,412) and/or a drain shielding structure for shielding and protecting the drain bonding pad.
Re claim 20: Kudymov teaches the semiconductor device according to claim 1, wherein the shielding structure (414, 416, 418) comprises a first portion (414 as shown in fig. 1B, 4B; hereinafter “1P”) extending along a first direction (left right direction of fig. 1B; hereinafter “1D”) and a second portion (416, 418 as shown in fig. 1B, 4B; hereinafter “2P”) extending along a second direction (up down direction of fig. 1B; hereinafter “2D”), the first direction (1D) and the second direction (2D) both are parallel to the plane where the substrate (420) is located, and the first direction (1D) intersects the second direction (2D); the semiconductor device comprises a first boundary (see below for 1B) extending along the first direction (1D) and a second boundary (see below for 2B) extending along the second direction (2D); minimum distance L1 between the first portion (414) and the first boundary (some arbitrary boundary that extends in direction 1D within 30 microns of 414) satisfies L1>30 μm; and minimum distance L2 between the second portion (416, 418) and the second boundary (some arbitrary boundary that extends in direction 2D within 30 microns of 416, 418) satisfies L2>30 μm.
Re claim 21: Kudymov teaches the semiconductor device according to claim 1, wherein the shielding structure (414, 416, 418) comprises a first portion (414 as shown in fig. 1B, 4B; hereinafter “1P”) extending along a first direction (left right direction of fig. 1B; hereinafter “1D”) and a second portion (416, 418 as shown in fig. 1B, 4B; hereinafter “2P”) extending along a second direction (up down direction of fig. 1B; hereinafter “2D”), the first direction (1D) and the second direction (2D) both are parallel to the plane where the substrate (420) is located, and the first direction (1D) intersects the second direction (2D); extension width D1 of the first portion (414) in the second direction (2D) satisfies D1>10 μm; and extension width D2 of the second portion (416, 418) in the first direction (1D) satisfies D2>10 μm (the layers 412 and 416 extend beyond 10 microns since that is the thickness of 422; e.g. paragraph 31).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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