DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I, Species A, Subspecies (a) of Fig. 8, claims 1-2, 5-11 and 15-16, in the reply filed on November 7, 2025 is acknowledged. Examiner notes that claim 3 is not directed to the elected Subspecies (a), because the claimed limitation, “the first film has a different thickness depending on a position where the first film is formed”, is directed to Subspecies (b) of Fig. 14 from the restriction requirement, and claim 4 depends on claim 3. Therefore, claims 1-2, 5-11 and 15-16 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-9 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Takao (JP 3970210 B2).
Regarding claim 1, Takao discloses for a semiconductor device, comprising that
a first substrate (silicon chip 51, Fig. 6) including silicon (silicon chip or silicon wafer, [0030]);
a first film (insulating film 58, Fig. 6) formed on at least some surfaces of a hole-shaped portion (via hole VH, Fig. 6) formed in the first substrate (51, Fig. 6), because the insulating film 58 by Takao is conformably disposed on sidewall surface of the via hole VH (Fig. 6); and
a photosensitive second film (organic insulating film 60, Fig. 6) covering at least a part of a side surface of the hole-shaped portion (side surface of VH, Fig. 6) with the first film (58, Fig. 6) interposed therebetween, because the sidewall of organic insulating film 60A by Takao covers a sidewall surface of the via hole VH, the organic insulating film 60 by Takao is made of a photosensitive material such as polyimide, epoxy resin, or the like ([0022], see attached machine-translated copy), and the insulating film 58 is interposed between the sidewall of VH and the sidewall of 60A (Fig. 6).
Regarding claim 2, Takao further discloses for the semiconductor device according to claim 1 that the first film (58, Fig. 6) absorbs light having a wavelength sensitive to the second film (60, Fig. 6), because Applicants originally disclosed that “the first film 860 is an insulating film and includes a material of, for example, silicon nitride (SiN), silicon oxynitride (SiOxNy), titanium nitride (TiN), or the like” ([0092]) and “the second film 862 is, for example, an insulating resin film, and may include at least one of polyimide, silicones, acrylic, epoxy or spin-on-carbon (SOC)” ([0093]), Takao is found to teach corresponding structure. Specifically, Takao discloses that the insulating film 58, corresponding to the claimed first film, is formed of SiO2 or SiN film ([0037], machine-translated copy) and the sidewall organic insulating film 60A, corresponding to the claimed photosensitive second film, is formed of polyimide, epoxy resin or the like ([0022], machine-translated copy). Since Takao employs the same or equivalent materials for the respective films as those originally disclosed in the claimed invention, the insulating film 58 by Takao would inherently absorb light having a wavelength to which the sidewall organic insulating film 60A is sensitive.
Regarding claim 5, Takao further discloses for the semiconductor device according to claim 1 that the first film (58, Fig. 6) has an adsorption force of a predetermined value or more with respect to the first substrate (51, Fig. 6) and the second film (60A, Fig. 6), because Takao employs the same or equivalent materials for the respective films as those originally disclosed in the claimed invention, the insulating film 58 by Takao would inherently have an adsorption force of a predetermined value or more with respect to the silicon chip 51 and the sidewall organic insulating film 60A.
Regarding claim 6, Takao further discloses for the semiconductor device according to claim 1 that the first film (58, Fig. 6) is a substance containing at least one of silicon nitride (SiN), silicon oxynitride (SiOxNy), or titanium nitride (TiN), because Takao discloses that the insulating film 58, corresponding to the claimed first film, is formed of SiO2 or SiN film ([0037], machine-translated copy).
Regarding claim 7, Takao further discloses for the semiconductor device according to claim 1 that the second film (60A, Fig. 6) is an insulating film (organic insulating film, [0022], machine-translated copy).
Regarding claim 8, Takao further discloses for the semiconductor device according to claim 7 that the second film (60A, Fig. 6) is a substance containing at least one of polyimide, silicone, acryl, epoxy, or spin-on carbon (SOC), because Takao discloses that the sidewall organic insulating film 60A, corresponding to the claimed photosensitive second film, is formed of polyimide, epoxy resin or the like ([0022], machine-translated copy).
Regarding claim 9, Takao further discloses for the semiconductor device according to claim 1 that a multilayer wiring layer (multilayer of interlayer insulating film 52/pad electrode 53/passivation film 54/resin layer 55, Fig. 6) connected to the first substrate (51, Fig. 6), wherein the hole-shaped portion (VH, Fig. 6) is a through hole (VH, Fig. 6) penetrating the multilayer wiring layer (52/53/54/55, Fig. 6) from one surface of the first substrate (top surface of the silicon chip 51, Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over by Takao (JP 3970210 B2).
Regarding claim 10, Takao discloses for the semiconductor device according to claim 9 that a first connection conductor (vertical portion of wiring layer 61, Fig. 7) that covers the multilayer wiring layer (52/53/54/55, Fig. 7) through which the through hole (VH, Fig. 7) penetrates and the through hole (VH, Fig. 7) in which the second film (60A, Fig. 7) is formed, because Applicant originally disclosed that “the connection conductor 87 of the through silicon via 88 is connected to the redistribution layer 90…” ([0071], Fig. 8 of present application), and “note that the connection conductor 87 according to the present embodiment corresponds to the first connection conductor, and the redistribution layer 90 corresponds to the second connection conductor” ([0072] of present application), and therefore, the claimed first and second connection conductors can be formed of a single element with two portions. In this case, a vertical portion of the wiring layer 61 by Takao can correspond to the first connection conductor in the claimed invention and a lateral portion of the wiring layer 61 can correspond to the second connection conductor in the claimed invention;
an electrode (solder ball 63, Fig. 7) formed on a side of the one surface of the first substrate (upper side of top surface of the silicon chip 51, Fig. 7); and a second connection conductor (lateral portion of the wiring layer 61, Fig. 7) that connects the first connection conductor (vertical portion of the wiring layer 61, Fig. 7) and the electrode (63, Fig. 7).
Takao does not explicitly disclose that an electrode electrically connected to an external substrate.
However, Takao further discloses the solder balls 63 provided on the semiconductor substrate and it is well known in the semiconductor packaging industry that solder balls are conventionally used to provide external electrical interconnection between a semiconductor device and an external substrate or another chip. Therefore, one of ordinary skill in the art would have readily recognized that the solder balls 63 by Takao are suitable for electrically connecting the semiconductor device shown in Fig. 7 to an external substrate or chip.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect the solder balls 63 of Takao to external substrate or chip in order to provide external electrical interconnection.
Regarding claim 11, Takao further discloses that the first film (58, Fig. 7) is formed on at least a part of the one surface of the first substrate (51, Fig. 7), a side wall surface of the through hole (sidewall surface of VH, Fig. 7), and a surface of the multilayer wiring layer (top surface of 52/53/54/55, Fig. 7) on a side of the first substrate (top side of 51, Fig. 7).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Takao (JP 3970210 B2) in view of Kim et al. (US 2018/0012867, hereinafter Kim). The teachings of Takao are discussed in claim 9 above.
Regarding claim 15, Takao does not explicitly disclose that at least one of a logic circuit, a memory circuit, a control circuit, or an interposer are configured in the multilayer wiring layer.
However, Kim discloses for a semiconductor memory package including at least one through silicon via (TSV) (Abstract), and further disclose that a mobile system 4000 (Fig. 15) includes a camera image processor (CIP) ([0123]). Kim also teaches that the semiconductor memory package may include a memory module 500, an interposer 560, input/output circuits 551/552, memory controller MC (Fig. 7), and logic circuits ([0030])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the semiconductor device of Takao to include at least one of a logic circuit, a memory circuit, a control circuit or an interposer in a multilayer wiring layer, as disclosed by Kim, in order to provide essential circuitry for signal processing, control, and memory functions necessary for a functioning image sensor system.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Takao (JP 3970210 B2) in view of Kim et al. (US 2018/0012867, hereinafter Kim) as applied to claim 15 above, and further in view of Kim et al. (US 2018/0145104, hereinafter Kim(2)). The teachings of Takao in view of Kim are discussed in claim 15 above.
Regarding claim 16, Takao in view of Kim does not explicitly disclose that a second semiconductor substrate formed with a pixel region in which pixel units that perform photoelectric conversion are two-dimensionally arranged, wherein the logic circuit processes a pixel signal output from the pixel units.
However, Kim(2) discloses for an image sensor package including through silicon via (TSV) (Fig. 3A) that the image sensor package 1 (Fig. 1) includes the image sensor chip 10 and the logic chip 20. Kim(2) further discloses that the image sensor chip 10 includes unit pixels 120 (Fig. 2A-2B) having photodiodes PD (Fig. 3A), wherein the photodiodes are laterally arranged in a two-dimensional array (i.e., horizontally arranged array). Therefore, the image sensor chip 10 of Kim(2) corresponds to the second semiconductor substrate in the claimed invention. Kim(2) additionally discloses that the logic chip 20 is configured to process a pixel signal output from the image sensor chip 10 (Abstract, [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the second semiconductor substrate having unit pixels which is coupled to the logic circuitry, as disclosed by Kim(2), in order to provide two-dimensionally arranged photoelectric conversion pixels and signal processing functionality for an image sensor.
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815