DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirano (U.S. PGPub 2003/0122232).
Regarding claim 1, Hirano teaches a semiconductor device (Fig. 11) comprising a heat spreader (46, [0065]), a semiconductor element including a front surface electrode, the semiconductor element mounted on an upper surface of the heat spreader (12, [0067]), a metal block including a bonding surface bonded to the front surface electrode of the semiconductor element and at least one heat dissipating surface connected to the upper surface of the heat spreader with interposition of an insulating member, the metal block extending from the bonding surface to the at least one heat dissipating surface so as to straddle above at least one side of the semiconductor element (47, [0065]-[0066]; [0035] upper heat sink electrically connected to semiconductor chip 12 at upper surface; insulating member 48, [0068]), a terminal including a first end bonded to the metal block and a second end positioned on an opposite side from the first end and formed to be connectable to an external circuit (Fig. 12, [0066], 47b), and a sealing material sealing the heat spreader, the semiconductor element, the metal block, and the first end of the terminal, wherein the second end of the terminal is exposed from the sealing material (17, [0066]); wherein the semiconductor element includes a control electrode, a signal terminal bonded to the control electrode through a metal wire, wherein the sealing material seals the metal wire ([0036], control electrode connected to lead frame with bonding wire).
Regarding claim 3, Hirano teaches wherein the insulating member is an insulating resin film provided on the upper surface of the heat spreader ([0072]).
Regarding claim 4, Hirano teaches wherein the at least one heat dissipating surface is a plurality of heat dissipating surfaces, the bonding surface is positioned between the plurality of heat dissipating surfaces and is bonded to the front surface electrode, and the metal block extends from the bonding surface to the plurality of heat dissipating surfaces so as to straddle above a plurality of sides of the semiconductor element (Fig. 11).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Fujita (U.S. PGPub 2019/0221490).
Regarding claim 2, Hirano does not explicitly teach wherein the metal block includes a through hole in the bonding surface.
Fujita teaches wherein a metal block includes a through hole adjacent to a coupling portion ([0063], 29, Fig. 3).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Fujita with Hirano such that the metal block includes a through hole in the bonding surface for the purpose of restricting peeling of the sealing material (Fujita, [0063]).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Koide (U.S. PGPub 2009/0079062).
Regarding claim 5, Hirano does not explicitly teach wherein the metal block includes a recessed portion outside a bonding portion in which the bonding surface and the front surface electrode are bonded, and the recessed portion is recessed in a direction from a lower surface of the metal block toward the upper surface with respect to the bonding surface.
Koide teaches wherein a heat spreading metal block is bonded to a semiconductor device at a bonding surface and a substrate upper surface, wherein the metal block includes a recessed portion outside a bonding portion in which the bonding surface and the front surface electrode are bonded, and the recessed portion is recessed in a direction from a lower surface of the metal block toward the upper surface with respect to the bonding surface (Fig. 1, 14, [0021]; area between center and peripheral region of 14).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Koide with Hirano such that the metal block includes a recessed portion outside a bonding portion in which the bonding surface and the front surface electrode are bonded, and the recessed portion is recessed in a direction from a lower surface of the metal block toward the upper surface with respect to the bonding surface for the purpose of providing thicker portions at appropriate regions for heat dissipation ([Koide, [0021]).
Regarding claim 7, Hirano does not explicitly teach wherein the metal block is formed of a material having a linear expansion coefficient of 7 ppm/° C. or more and 12 ppm/° C. or less.
Koide teaches wherein a heat spreading metal block is bonded to a semiconductor device at a bonding surface and a substrate upper surface, wherein the metal block includes a recessed portion outside a bonding portion in which the bonding surface and the front surface electrode and wherein the metal block is formed from a material having a linear expansion coefficient of 11 ppm/° C ([0021]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Koide with Hirano such that the metal block is formed of a material having a linear expansion coefficient of 7 ppm/° C. or more and 12 ppm/° C. or less for the purpose of providing efficient heat dissipation (Koide, [0021]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Koide (U.S. PGPub 2009/0079062).
Regarding claim 6, Hirano does not explicitly teach wherein the metal block includes a hole penetrating between a bottom portion of the recessed portion and the upper surface of the metal block.
Fujita teaches wherein a metal block includes a through hole ([0063], 28, 29, Fig. 3).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Fujita with Hirano such that the metal block includes a through hole in the bonding surface for the purpose of restricting peeling of the sealing material (Fujita, [0063]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Arai (U.S. PGPub 2015/0008570).
Regarding claim 8, Hirano does not explicitly teach wherein the semiconductor element is formed of SiC. Hirano teaches wherein the semiconductor element is a power semiconductor device such as an IGBT ([0034]).
Arai teaches wherein an IGBT is formed of SiC ([0005]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Arai with Hirano such that the semiconductor element is SiC for the purpose of implementing the power device of Hirano (Hirano, [0034]; Arai, [0005]).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Kimura (U.S. PGPub 2013/0062745).
Regarding claim 9, Hirano teaches a semiconductor device (Fig. 11) comprising a heat spreader (46, [0065]), a semiconductor element including a front surface electrode, the semiconductor element mounted on an upper surface of the heat spreader (12, [0067]), a metal block including a bonding surface bonded to the front surface electrode of the semiconductor element and at least one heat dissipating surface connected to the upper surface of the heat spreader with interposition of an insulating member, the metal block extending from the bonding surface to the at least one heat dissipating surface so as to straddle above at least one side of the semiconductor element (47, [0065]-[0066]; [0035] upper heat sink electrically connected to semiconductor chip 12 at upper surface; insulating member 48, [0068]), a terminal including a first end bonded to the metal block and a second end positioned on an opposite side from the first end and formed to be connectable to an external circuit (Fig. 12, [0066], 47b), and a sealing material sealing the heat spreader, the semiconductor element, the metal block, and the first end of the terminal, wherein the second end of the terminal is exposed from the sealing material (17, [0066]); wherein the semiconductor element includes a control electrode, a signal terminal bonded to the control electrode through a metal wire, wherein the sealing material seals the metal wire ([0036], control electrode connected to lead frame with bonding wire).
Hirano does not explicitly teach wherein the insulating member is the sealing material.
Kimura teaches wherein a metal block and heat spreader are coupled by an insulating member which is the package sealing material (Fig. 14, A11, A6, A7/A75, [0200]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kimura with Hirano such that the insulating member is the sealing material for the purpose of reducing cost and increasing manufacturing efficiency (Kimura, [0214]).
Regarding claim 11, the combination of Hirano and Kimura teaches wherein the metal block has an inclined surface or a curved surface at an end portion of the heat dissipating surface (Kimura, [00233]-[0236], Fig. 28). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Hirano and Kimura for the purpose of improving manufacturability (Kimura, [0236]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Kimura (U.S. PGPub 2013/0062745) and Hirakawa (U.S. Pat. 5814878).
Regarding claim 10, the combination of Hirano and Kimura does not explicitly teach wherein the metal block includes a plurality of narrow grooves in the heat dissipating surface and extending directions of the plurality of narrow grooves are unidirectionally aligned.
Hirakawa teaches wherein a heat dissipating metal block includes a plurality of unidirectionally aligned narrow grooves at the heat transfer surface (Figs. 13-14, col. 1, l. 13-57).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hirakawa with Hirano and Kimura such that the metal block includes a plurality of narrow grooves in the heat dissipating surface and extending directions of the plurality of narrow grooves are unidirectionally aligned for the purpose of enhancing contact between the metal block and the sealing material and enhancing the filling process with the sealing material (Hirakawa, col. 1, l. 42-46).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Kimura (U.S. PGPub 2013/0062745) and Koide (U.S. PGPub 2009/0079062).
Regarding claim 12, the combination of Hirano and Kimura does not explicitly teach wherein the metal block is formed of a material having a linear expansion coefficient of 7 ppm/° C. or more and 12 ppm/° C. or less.
Koide teaches wherein a heat spreading metal block is bonded to a semiconductor device at a bonding surface and a substrate upper surface, wherein the metal block includes a recessed portion outside a bonding portion in which the bonding surface and the front surface electrode and wherein the metal block is formed from a material having a linear expansion coefficient of 11 ppm/° C ([0021]). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Koide with Hirano and Kimura such that the metal block is formed of a material having a linear expansion coefficient of 7 ppm/° C. or more and 12 ppm/° C. or less for the purpose of providing efficient heat dissipation (Koide, [0021]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Kimura (U.S. PGPub 2013/0062745) and Arai (U.S. PGPub 2015/0008570).
Regarding claim 13, the combination of Hirano and Kimura does not explicitly teach wherein the semiconductor element is formed of SiC. Hirano teaches wherein the semiconductor element is a power semiconductor device such as an IGBT ([0034]).
Arai teaches wherein an IGBT is formed of SiC ([0005]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Arai with Hirano and Kimura such that the semiconductor element is SiC for the purpose of implementing the power device of Hirano (Hirano, [0034]; Arai, [0005]).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hirano (U.S. PGPub 2003/0122232) in view of Kimura (U.S. PGPub 2013/0062745) and Hirakawa (U.S. Pat. 5814878)
Regarding claims 14-16, Hirano teaches a method of manufacturing a semiconductor device (Fig. 11), comprising mounting a semiconductor element on an upper surface of a heat spreader (46, [0065][ 12, [0067]), and fixing a metal block so as to straddle above at least one side of the semiconductor element (47, [0065]-[0066]), and bonding a signal terminal to a control electrode of the semiconductor element through a metal wire ([0036], control electrode connected to lead frame with bonding wire);
wherein the fixing of the metal block includes: bonding a bonding surface of the metal block to a front surface electrode of the semiconductor element (Fig. 11, [0035] upper heat sink electrically connected to semiconductor chip 12 at upper surface), and connecting a heat dissipating surface of the metal block to the upper surface of the heat spreader with interposition of an insulating member (48, [0068]), and providing a sealing material for sealing the heat spreader, the semiconductor element, and the metal block (17, [0065]).
Hirano does not explicitly teach wherein the connecting of the heat dissipating surface of the metal block comprises injecting the sealing material as the insulating member into a gap between the heat dissipating surface of the metal block and the upper surface of the heat spreader, and the sealing material is injected through an injection gate provided in a lateral direction of the gap between the heat dissipating surface of the metal block and the upper surface of the heat spreader, wherein a height of the injection gate matches a height of the upper surface of the heat spreader, and wherein the metal block includes a plurality of narrow grooves in the heat dissipating surface, and extending directions of the plurality of narrow grooves are a direction from the injection gate toward the gap.
Kimura teaches wherein a metal block and heat spreader are coupled by an insulating member which is the package sealing material (Fig. 14, A11, A6, A7/A75, [0200]).
Hirakawa teaches a heat dissipating metal block (Figs. 13-14, col. 1, l. 13-57), wherein the sealing material is injected through an injection gate provided in a lateral direction of the gap adjacent to the heat dissipating surface of the metal block (Fig. 8, 33, col. 7, l. 33-65), wherein a height of the injection gate matches a height of the heat dissipating surface, the metal block includes a plurality of narrow grooves in the heat dissipating surface, and extending directions of the plurality of narrow grooves are a direction from the injection gate toward the gap (Figs. 13-14, col. 1, l. 13-57; Fig. 8).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kimura and Hirakawa with Hirano such that the connecting of the heat dissipating surface of the metal block comprises injecting the sealing material as the insulating member into a gap between the heat dissipating surface of the metal block and the upper surface of the heat spreader, and the sealing material is injected through an injection gate provided in a lateral direction of the gap between the heat dissipating surface of the metal block and the upper surface of the heat spreader, wherein a height of the injection gate matches a height of the upper surface of the heat spreader, and wherein the metal block includes a plurality of narrow grooves in the heat dissipating surface, and extending directions of the plurality of narrow grooves are a direction from the injection gate toward the gap, for the purpose of for the purpose of reducing cost and increasing manufacturing efficiency (Kimura, [0214]), enhancing contact between the metal block and the sealing material, enhancing the filling process with the sealing material (Hirakawa, col. 1, l. 42-46), and preventing voids during filling (Hirakawa, col. 7, l. 54-65).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALIA SABUR/Primary Examiner, Art Unit 2812