Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1 and 3-4 in the reply filed on 05/18/2026 is acknowledged. Also, the restriction requirement on Group III (previous claims 6 and 10, which correspond to new claims 19-26) is withdrawn as no undue search burden is found.
Claim Status
In response to a preliminary amendment filed 05/18/2026, claims 2 and 5-10 are cancelled, new claims 11-24 have been added, and claims 1, 3-4, and 11-26 are pending and under examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4, and 11-24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected as it recites the limitation “forming a resist pattern on the surface of the copper layer” in lines 6-7. The limitation “the surface” renders the scope of the claim unclear due to lack of antecedent basis. It is ambiguous to which surface, top or bottom, of the copper layer it refers to, or if the surface is the same surface (in direct contact) as the surface of the insulating material layer. Similarly, since the layer can be reasonably presumed as a 3D structure, the side surfaces (transverse sides) of the layer can also be understood as “the surface”. For the same reason, claim 19 which recites the limitation “the surface”, and all dependent claims 3-4, 11-18, & 20-24, respectively, thereof are rejected as well by virtue of their dependencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 1, 3, 11-15, and 17-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toba et al (J.P. Patent Application Publication 2019212653 A1) hereinafter Toba.
Regarding claim 1, Toba discloses a method for manufacturing a wiring board (Title: Method for Manufacturing Wiring Board), the method comprising:
Providing a laminate (layers comprising: first insulating material layer 1, p. 3, ll. 22; first seed layer S1, p. 4, ll. 44; and second seed layer S2, p. 6, ll. 24) comprising an insulating material layer (first insulating material layer 1) and a copper layer (first & second seed layer S1 S2) provided on a surface of the insulating material layer (surface F, p. 4, ll. 41) (FIG. 1e depicts seed layers S1 S2 provided directly on surface F of the first insulating material layer 1) wherein the copper layer is an electroless copper plating layer (electroless copper plating, p. 5, ll. 14);
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Forming a resist pattern (resist R, p. 7, ll. 3) on the surface of the copper layer (FIG. 2a depicts the resist R provided on seed layers S1 S2), the resist pattern including a groove (opening R1, p. 7, ll. 3) reaching a surface of the copper layer (p. 7, ll. 3-4, “resist R having an opening R1… reaching the second seed layer S2”); and
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Filling the groove with a conductive material containing copper (conductive portion C1 & C2, p. 7, ll. 28-30, “conductive material (copper-containing material) is filled in the through holes (first opening H1 and opening R1) and the recess R2, and the conduction portion C1 and the wiring C2 are formed”) by electrolytic copper plating (electrolytic copper plating, p. 7, ll. 27).
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Regarding claim 3, Toba further discloses the method according to claim 1, as detailed above, wherein a thickness of the copper layer is 20 nm to 200 nm (p. 6, ll. 11-14 & 36-37, Toba discloses that S1 is formed with a thickness of 10 nm to 50 nm. Toba also discloses that S2 is formed with a thickness of 20 nm to 200 nm).
Regarding claim 11, Toba further discloses the method according to claim 1, as detailed above,
wherein the surface provided with the copper layer is a first surface of the insulating material layer (surface F, p. 4, ll. 41),
wherein the laminate further comprises a support board (support substrate S, p. 3, ll. 25-26,“"support substrate S may have a conductive layer Sa formed on the surface on which the insulating material layer is formed”) formed on a second surface of the insulating material layer opposite to the first surface (FIG. 1e depicts support substrate S, provided with conductive layer Sa, provided on the lower surface of the first insulating material layer 1), and
wherein the method further comprises:
forming an opening (first opening H1, p. 3, ll. 34) reaching a surface of the support board through the copper layer and the insulating material layer (p. 4, ll. 22-24, “first opening H1 is formed so as to reach the surface of the support substrate S, that is, the side surface made of the first insulating material layer 1 and the support substrate S”; as seen in FIG. 1e); and
forming a seed layer (second seed layer S2) on a surface of a side wall (inner wall, p. 4, ll. 21) of the opening by electroless copper plating (FIG. 1e depicts second seed layer S2 provided on the side walls of opening H1).
Regarding claim 12, Toba further discloses the method according to claim 11, as detailed above,
wherein the opening (opening H1) corresponds to a first opening in the laminate,
wherein the resist pattern includes a second opening (opening R1) communicating with the first opening (p. 7, ll. 3-4, “opening R1 communication with the first opening H1”), and
wherein the method further comprises concurrently filling the first opening and the second opening with a conductive material containing copper (conductive portion C1 & C2, p. 7, ll. 28-30, “conductive material (copper-containing material) is filled in the through holes (first opening H1 and opening R1) and the recess R2, and the conduction portion C1 and the wiring C2 are formed”) by electrolytic copper plating (electrolytic copper plating).
Regarding claim 13, Toba further discloses the method according to claim 11, as detailed above,
wherein prior to forming the resist pattern on the surface of the copper layer, the first surface of the insulating material layer is substantially covered by the copper layer (FIG. 2a depicts the top surface of layer 1 substantially covered by the first and second seed layer S1 S2), and the second surface of the insulating material layer is substantially covered by support board (FIG. 2a depicts the lower surface of layer 1 substantially covered by support substrate S and conductive layer Sa).
Regarding claim 14, Toba further discloses the method according to claim 13, as detailed above, wherein the support board is entirely made of a conductive material (conductive layer Sa of support substrate S, p. 3, ll. 25).
Regarding claim 15, Toba further discloses the method according to claim 11, as detailed above, wherein a thickness of the copper layer is 20 nm to 200 nm (p. 6, ll. 11-14 & 36-37, Toba discloses that S1 is formed with a thickness of 10 nm to 50 nm. Toba also discloses that S2 is formed with a thickness of 20 nm to 200 nm).
Regarding claim 17, Toba further discloses the method according to claim 1, as detailed above, further comprising:
Forming an opening through the copper layer and the insulating material layer (p. 4, ll. 22-24, “first opening H1 is formed so as to reach the surface of the support substrate S, that is, the side surface made of the first insulating material layer 1 and the support substrate S”; as seen in FIG. 1e); and
Forming a seed layer (second seed layer S2) on a surface of a side wall of the opening by electroless copper plating (FIG. 1e depicts second seed layer S2 provided on the side walls of opening H1).
Regarding claim 18, Toba further discloses the method according to claim 13, as detailed above,
wherein the opening corresponds to a first opening in the laminate (opening H1),
wherein the resist pattern (resist R) includes a second opening (opening R1) communicating with the first opening (FIG. 2a depicts opening R1 and H1 connecting), and
wherein the method further comprises concurrently filling the first opening and the second opening with a conductive material containing copper (conductive portion C1 & C2, p. 7, ll. 28-30, “conductive material (copper-containing material) is filled in the through holes (first opening H1 and opening R1) and the recess R2, and the conduction portion C1 and the wiring C2 are formed”) by electrolytic copper plating (p. 6, ll. 26, “(for example, electrolytic copper plating) performed to form the conductive portion C1”).
Regarding claim 19, Toba discloses (Title) a laminate (layers comprising: first insulating material layer 1, p. 3, ll. 22; first seed layer S1, p. 4, ll. 44; and second seed layer S2, p. 6, ll. 24) comprising:
An insulating material layer (first insulating material layer 1);
A copper layer (first & second seed layer S1 S2) provided on a surface of the insulating material layer (surface F, p. 4, ll. 41) (FIG. 1e depicts seed layers S1 S2 provided directly on surface F of the first insulating material layer 1), wherein the copper layer is an electroless copper plating layer (electroless copper plating, p. 5, ll. 14); and
A resist pattern (resist R, p. 7, ll. 3) formed on the surface of the copper layer (FIG. 2a depicts the resist R provided on seed layers S1 S2), wherein the resist pattern includes a groove reaching a surface of the copper layer, and wherein the groove is filled with a conductive material containing copper (p. 7, ll. 28-30, “conductive material (copper-containing material) is filled in the through holes (first opening H1 and opening R1) and the recess R2, and the conduction portion C1 and the wiring C2 are formed”) by electrolytic copper plating (electrolytic copper plating, p. 7, ll. 27).
Regarding claim 20, Toba further discloses the method according to claim 19, as detailed above, wherein a thickness of the copper layer is 20 nm to 200 nm (p. 6, ll. 11-14 & 36-37, Toba discloses that S1 is formed with a thickness of 10 nm to 50 nm. Toba also discloses that S2 is formed with a thickness of 20 nm to 200 nm).
Regarding claim 21, Toba further discloses the method according to claim 19, as detailed above,
wherein the surface provided with the copper layer is a first surface of the insulating material layer (surface F, p. 4, ll. 41),
wherein the laminate further comprises a support board (support substrate S, p. 3, ll. 25-26,“"support substrate S may have a conductive layer Sa formed on the surface on which the insulating material layer is formed”) formed on a second surface of the insulating material layer opposite to the first surface (FIG. 1e depicts support substrate S, provided with conductive layer Sa, provided on the lower surface of the first insulating material layer 1),
wherein an opening (first opening H1, p. 3, ll. 34) extending through the copper layer and the insulating material layer and reaching a surface of the support board, is filled with a conductive material containing copper (p. 4, ll. 22-24, “first opening H1 is formed so as to reach the surface of the support substrate S, that is, the side surface made of the first insulating material layer 1 and the support substrate S”; as seen in FIG. 1e), and
wherein a seed layer (second seed layer S2) is formed on a surface of a side wall of the opening by electroless copper plating (FIG. 1e depicts second seed layer S2 provided on the side walls of opening H1).
Regarding claim 22, Toba further discloses the method according to claim 21, as detailed above,
wherein the opening (opening H1) corresponds to a first opening in the laminate,
wherein the resist pattern includes a second opening (opening R1) communicating with the first opening (p. 7, ll. 3-4, “opening R1 communication with the first opening H1”), and
wherein the first opening and the second opening are filled continuously with the conductive material containing copper (conductive portion C1 & C2, p. 7, ll. 28-30, “conductive material (copper-containing material) is filled in the through holes (first opening H1 and opening R1) and the recess R2, and the conduction portion C1 and the wiring C2 are formed”).
Regarding claim 23, Toba further discloses the method according to claim 21, as detailed above,
Wherein the support board substantially covers the second surface of the insulating material layer (FIG. 1e depicts support substrate S and conductive layer Sa covering the entire lower surface of the first insulating material layer 1), and
Wherein the support board is entirely made of a conductive material (conductive layer Sa of support substrate S, p. 3, ll. 25).
Regarding claim 24, Toba further discloses the method according to claim 23, as detailed above, wherein the support board includes a copper clad laminate (support substrate S) and a copper layer (conductive layer Sa) provided on a surface of the copper clad laminate (FIG. 1e depicts conductive layer Sa provided on support substrate S).
Regarding claim 25, Toba further discloses the method according to claim 19, as detailed above, wherein a first opening (opening H1) formed through the copper layer (first and second seed layer S1 S2) and the insulating material layer (first insulating material layer 1) and a second opening (opening R1) formed in the resist pattern (resist R) are filled with a continuous conductive material containing copper (p. 6, ll. 26, “(for example, electrolytic copper plating) performed to form the conductive portion C1”).
Regarding claim 26, Toba further discloses the method according to claim 19, as detailed above, wherein a conductive material containing copper (conduction portion C1) extends continuously through the copper layer and through the insulating material layer (p. 7, ll. 28-30, “the conductive material is filled in the through holes (first opening H1 and opening R1”; as depicted in FIG. 2b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Toba, and further in view of Matsuura (U.S. Patent Application Publication 20180376602 A1).
Regarding claim 4, Toba further discloses the method according to claim 1, as detailed above.
However, Toba fails to disclose the method wherein the laminate is prepared by providing a copper plated carrier which comprises the copper layer and carrier that supports the copper layer; pasting the copper layer of the copper plated carrier onto a surface of the insulating material layer; and peeling the carrier from the copper layer.
Matsuura discloses a method (Title: Copper Foil with Carrier, Copper Foil with Resin and Method for Manufacturing Printed Wiring Board) wherein a laminate (printed circuit board, ¶53) is prepared by:
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providing a copper plated carrier (copper foil 10, ¶45) which comprises the copper layer (plurality of layers comprising 14, 16, 18, & 20 in FIG. 1, ¶45) and a carrier that supports the copper layer (carrier 12, ¶45, FIG. 1 depicts plurality of layers 14, 16, 18, & 20 provided on carrier 12);
pasting the copper layer of the copper plated carrier onto a surface of the insulating material layer (resin layer 22, ¶55, “The resin layer 22 and then the copper foil 10 with a carrier according to the present invention are laminated on at least one side of a core layer”; FIG. 3a depicts the copper foil 10 provided on the top surface of resin layer 22); and
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peeling the carrier from the copper layer (¶64, “the carrier 12 is removed”; FIG. 3c depicts the carrier 12 removed from the plurality of layers and resin layer 22).
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Toba discloses a method for manufacturing a wiring board including the steps of providing a laminate with a plurality of layers, including a copper layer, a resist pattern layer, and grooves with a seed layer such that the hole can be provided with a conductive material that electrically connects the conductive layers together. Matsuura discloses a method for producing a printed circuit board that comprises steps on providing a plurality of layer to the resin layer using a carrier. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the providing method of Matsuura’s disclosure to transport and provide a copper layer to the first insulating material of Toba’s to achieve routine optimization, allowing for obvious alternative method of providing a layer to a substrate layer such that the layer can be predictably applied to the first insulating layer, thereby enhancing adhesion qualities, reducing thermal mismatch, and/or reducing costly rework due to cracking, delamination, or the like. Furthermore, utilizing the method of providing via a carrier allows for extremely thin layers to be pressed against and tightly bonded to a substrate for improved adherence between a multitude of layers (Matsuura ¶2).
Regarding claim 16, Toba in view of Matsuura teaches the method according to claim 11, and Matsuura further discloses the laminate prepared by:
providing a copper plated carrier (copper foil 10, ¶45) which comprises the copper layer (plurality of layers comprising 14, 16, 18, & 20, ¶45) and a carrier that supports the copper layer (carrier 12, ¶45, FIG. 1 depicts plurality of layers 14, 16, 18, & 20 provided on carrier 12);
pasting the copper layer of the copper plated carrier onto a surface of the insulating material layer (resin layer 22, ¶55, “The resin layer 22 and then the copper foil 10 with a carrier according to the present invention are laminated on at least one side of a core layer”; FIG. 3a depicts the copper foil 10 provided on the top surface of resin layer 22); and
peeling the carrier from the copper layer (¶64, “the carrier 12 is removed”; FIG. 3c depicts the carrier 12 removed from the plurality of layers and resin layer 22). (Regarding the reason to combine references, refer to the rejection of claim 4, supra, as it is applicable to the rejection of claim 16 in the manner of utilizing a carrier manufacturing method to provide a conductive layer onto a substrate layer).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE REY D LEGASPI whose telephone number is (571)272-2956. The examiner can normally be reached Monday-Friday 8-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hong can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.D.L./Examiner, Art Unit 3729 /THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729
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