Prosecution Insights
Last updated: April 19, 2026
Application No. 18/260,659

Display Panel and Terminal Device

Non-Final OA §103
Filed
Jul 07, 2023
Examiner
LEBENTRITT, MICHAEL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Honor Device Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
916 granted / 992 resolved
+24.3% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
25 currently pending
Career history
1017
Total Applications
across all art units

Statute-Specific Performance

§101
3.3%
-36.7% vs TC avg
§103
40.8%
+0.8% vs TC avg
§102
30.2%
-9.8% vs TC avg
§112
10.1%
-29.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 992 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-13 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN109671742A and further in view of CN109656067A. Claim 1 claims a display panel, (CN109671742A) likewise discloses a display panel, and specifically discloses the following technical features (see specification paragraph [0007-0093], figures 1-9): an AMOLED display panel, comprising a driver circuit region D2 (first display region) for driving the display light emitting region D1 to emit light, a fan-out region D3 for disposing fan traces, and a display light emitting region D1 disposed over the driver circuit region D2 and the fan-out region D3 and a bending region D4 for bending, as can be seen from Figure 3, with a bonding area, one end of the fan-out lead extends towards the direction of the signal line to which it is connected, and the other end of the fan-out lead extends towards the direction of the bonding area belongs to what is implicitly disclosed by CN109671742A. The area of the driver circuit region D2 is less than the area of the display light emitting area D1 (beyond being part of the second display area), and the display light emitting area D1 fully covers the driver circuit region D2 and covers at least part of the fan-out region D3. The driving units 21 are not completely directly below the corresponding display units 22, so when space for the source/drain 215 is insufficient, the driving units 21 located around the edge regions (upper, lower, and both side edge regions) of the driving circuit area and the display units 22 electrically connected thereto are electrically connected by the source/drain traces 216. The driving array tier includes a plurality of pixel driver circuits and a plurality of signal lines extending in a first direction, each of the signal lines being connected to the pixel driver circuit in the same column, and each of the pixel driver circuits and each of the signal lines in the driving array tier being distributed over the first display region (FIGS. 4-5 and 8). CN109671742A fails to teach: that the display panel includes a drive array layer, a first insulating layer, a bridge trace layer, a second insulating layer, and a light emitting device layer disposed in layers on a substrate; the bridging trace layer comprises a plurality of bridging traces, each of the bridging traces connected with the pixel driver circuitry by a first via through the first insulating layer, each of the bridging traces also connected with the light emitting device by a second via through the second insulating layer; a driver chip is disposed within the bonding region. The technical problem actually solved by the present invention, determined on the basis of the above-mentioned distinguishing technical features, is how specifically the bridging traces are arranged. On the basis of CN109671742A disclosing that "when space of the source/drain 215 is insufficient, the driving units 21 located around the edge regions (upper, lower, and both side edge regions) of the driving circuit area and the display units 22 electrically connected thereto are electrically connected by the source/drain wiring 216", the provision of the bridging traces as defined in claim 1 belongs to a conventional arrangement adopted by a person skilled in the art according to actual requirements; further, (CN109656067A) discloses a display panel and specifically discloses the following technical features (see specification paragraph [0001-0175], Figures 1-9): a driver chip is provided within a bonding region. Therefore, it would have been obvious to one of ordinary skill in the art to combine the above reference in-order to solve the technical problem thereof, all being the provision of bridging traces in the bonding zones. Claims 2-6 are dependent claims of claim 1. CN109671742A also discloses (see paragraph [0007- 0093], Figures 1-9) that the area of the driver circuit region D2 is smaller than the area of the display light emitting area D1 (beyond part of the second display area), and that the display light emitting area D1 covers the driver circuit region D2 completely and covers at least part of the fan-out region D3. On the basis, the positioning of the second display region on one side, two sides, three sides of the first display region, and the position of the exit of the fan-out lead, all belong to conventional arrangements taken by those skilled in the art. Claims 7-8 are dependent claims of claim 1. To improve uniformity of display brightness, the difference between the number of light emitting devices through which any two of said bridging traces pass is less than a preset number, is a conventional setting adopted by a person skilled in the art according to actual requirements; the orthogonal projection of each of the bridging traces onto the substrate as any one or more combinations of straight lines, broken lines, and curved lines is also conventional in the art. Claim 9 is a dependent claim of any one of claim 1. Claims 10-11 are dependent claims of claim 9. As can be seen from Figures 1 and 4, CN109671742A discloses additional technical features of claim 9; figure 1 discloses additional technical features such as gradual angle increase in claim 10; figure 4 discloses the features of claim 11 as being equal in angle, obtuse in angle. Claim 12 is a dependent claim of claim 11. Claim 13 is a dependent claim of claim 12. CN109671742A also discloses (see paragraph [0007-0093] of the specification, Figures 1-9): employing less resistivity metal as the fan-out region conductor, and patterning the wire with a "bow" pattern, by employing the wire 200 in an "arch" pattern, as shown in FIG. 2 or FIG. 3, the length of the wire in the otherwise smaller intermediate region is increased to reduce the difference in length between the wires, thereby reducing the difference in color between the two sides of the display area and the intermediate display (FIG. 2) due to the long wires and short intermediate wires. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN109671742A and further in view of CN109656067A as applied to claim 1 above, and further in view of (CN102323681A). Claim 14 is a dependent claim of claim 12. (CN102323681A) discloses a display panel and specifically discloses the following technical features (see specification paragraph [0005-0046], Fig. 1-7B): Although the lead length at the edge region E of the sector structure F may be greater than/equal to the lead length at the middle region M of the sector structure F, the wire widths W1-Wn-1 of the leads L1-Ln-1 of the present embodiment gradually increase from the middle region M to the edge region E. In other words, the smaller the lead line width closer to the middle region M of the sector structure F, the larger the lead line width closer to the edge region E of the sector structure F. Thus, such a design may result in a balance in the impedance of the leads L1-Ln. In this way, the delay variability of the signaling of the leads L1-Ln may be reduced. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because it narrows the impedance difference. Claims 15-16 are dependent claims of claim 1. As can be seen in Figures 4 and 5 of CN109671742A, the orthogonal projection of each of the light emitting devices distributed along the first direction and the pixel defining structure between two adjacent light emitting devices in the first direction onto the substrate overlays the orthogonal projection of the signal lines onto the substrate. As can be seen in Figures 4-9 of CN109671742A, the structural spacing between two adjacent light emitting devices is defined by pixels, and there is a gap between two adjacent pixel driving circuits, the pixel driving circuits comprising respective transistors arranged in the same layer; a sum of a dimension of the pixel driving circuitry and a dimension of the gap in a direction in which the second display region points toward the first display region is less than a sum of a dimension of the light emitting device and a dimension of the pixel defining structure. Claim 17 is a dependent claim of claim 1. CN109671742A also discloses (see paragraph [0007-0093], Figures 1-9) that each driving unit 11 comprises a driving thin film transistor for driving the display unit 12 to emit light and at least one switching thin film transistor functioning as a switch. Wherein the second transistor is provided on a side of the first transistor group away from the substrate to secure display quality, and there is a region of coincidence of an orthographic projection of each transistor in the second set of transistors onto the substrate with an orthographic projection of each transistor in the first set of transistors onto the substrate, as desired in the art. Claim 18 claims a terminal device comprising a housing and a display panel as claimed in claim 1. A person skilled in the art knowing that it is common general knowledge to apply a display panel to a terminal device and that the device comprises a housing. Claims 19 and 20 are dependent claims of claim 18. CN109671742A also discloses (see paragraph [0007- 0093], Figures 1-9) that the area of the driver circuit region D2 is smaller than the area of the display light emitting area D1 (beyond part of the second display area), and that the display light emitting area D1 covers the driver circuit region D2 completely and covers at least part of the fan-out region D3. On the basis, the positioning of the second display region on one side, two sides, three sides of the first display region, and the position of the exit of the fan-out lead, all belong to conventional arrangements taken by those skilled in the art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MICHAEL . LEBENTRITT Primary Examiner Art Unit 2893 /MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 07, 2023
Application Filed
Oct 21, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 992 resolved cases by this examiner. Grant probability derived from career allow rate.

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