Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1, 3-7 are pending.
-Claim 2 is cancelled.
-Claims 1, 3, 4, 6 and 7 are amended.
Priority
Examiner noted in the previous Office Action, dated September 5, 2025, that in order to effectively benefit from the foreign priority date based on the application filed in Japan on January 15, 2021, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented. The Applicant has not included these documents in the instant application. Therefore, the right to foreign priority under 35 U.S.C. 119 (a)-(d) is not considered perfected.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
Response to Arguments
Applicant's amendments and arguments filed December 3, 2025 have been fully considered but they are not persuasive.
Applicant submits that Tae et al. (U.S. Pub. 2013/0264703), hereinafter Tae, “does not expressly or inherently describe at least, for example, the features of ‘an adhesive that bonds the extended portion of the frame and the circuit region, wherein the plurality of wires is outside a layer of the adhesive.’ as recited in the amended independent claim 1”. (Page 7) Examiner disagrees with this conclusion.
Examiner brings Applicant’s attention to Tae’s fourth embodiment of the semiconductor package, as described in Paragraphs [0065] and [0066], and seen in Fig. 12. Clearly this anticipates the newly amended limitation (in that the plurality of wires are outside a layer of the adhesive).
The rejection has been updated to address the newly amended limitations.
Claim Objections
Claim 4 is objected to because of the following informalities:
The limitation “the second portion of the plurality of wires is remaining portion of the plurality of wires other than the first portion of the plurality of wires.” has unclear syntax (whether “remaining portion” is a new element) and is missing a grammatical article (“a remaining portion” or “the remaining portion”). The Examiner recommends amending Claim 4 such that it reads as follows: --The semiconductor package according to claim 3, wherein the frame further covers a second portion of the plurality of wires, wherein
the second portion of the plurality of wires comprises the plurality of wires not comprising the first portion of the plurality of wires.--
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the plurality of wires". There is insufficient antecedent basis for this limitation in the claim.
For the purposes of this examination, the Examiner will read the limitation “the plurality of wires” of Claim 7 as --a plurality of wires--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tae et al. (US Pub. 2013/0264703), hereinafter Tae.
Regarding Claim 1, Tae teaches a semiconductor package (e.g. (100); Fig. 12, Paragraph [0042]) comprising:
-a solid-state imaging element (‘image sensor chip’ (20); Fig. 12, Paragraph [0043]), wherein the solid-state imaging element (20) includes:
-a pixel region, wherein the pixel region includes an array of a plurality of pixels ((PA); Fig. 12, Paragraph [0043]); and
-a circuit region, wherein the circuit region includes a circuit ((EA); Fig. 12, Paragraphs [0043] and [0044]) that is adjacent to the pixel region (PA);
-a frame (‘holder’ (40) consisting of portions (40a), (40b), and (40c); Fig. 12, Paragraph [0046]) wherein
-the frame includes an inner wall (e.g. (40c)) and an outer periphery portion (e.g. (40b)),
-the inner wall of the frame (40c) surrounds an outer periphery of the solid-state imaging element (20),
-the inner wall (40c) of the frame includes an extended portion (e.g. (40a)), and
-the extended portion of the frame (40a) is extended from the outer peripheral portion (40b) to the circuit region (EA);
-a substrate ((10), consisting of portions (1), (1a), and (1b); Fig. 12, Paragraph [0042]), wherein the solid-state imaging element (20) is on a surface of the substrate (1a);
-a plurality of wires ((30); Fig. 12, Paragraph [0045]) configured to connect the solid-state imaging element (20) to the substrate (10); and
-an adhesive ((35); Fig. 12, Paragraph [0048]) that bonds the extended portion of the frame (40a) and the circuit region (EA), wherein
-the plurality of wires (30) is outside a layer of the adhesive (e.g. the top left layer of (35) between the left (40a) and (20)). (As is indicated by the ‘second empty space’ (S2); Fig. 12, Paragraph [0066])
Regarding Claim 3, Tae teaches a semiconductor package according to claim 1, wherein:
-the frame (40) covers the circuit region (EA) and a first portion of the plurality of wires (e.g. (30) on the left).
Regarding Claim 4, Tae teaches a semiconductor package according to claim 3, wherein:
-the frame (40) further covers a second portion of the plurality of wires (e.g. (30) on the right), wherein
-the second portion of the plurality of wires (right (30) comprises the plurality of wires not comprising the first portion of the plurality of wires (left (30)).
Regarding Claim 5, Tae teaches a semiconductor package according to claim 1, wherein:
- the extended portion of the frame (40a) has a tapered end surface (See Fig. 10, Paragraph [0062]).
Regarding Claim 6, Tae teaches a method of manufacturing a semiconductor package (Figs. 3 – 9, 12; Paragraph [0028]), the method comprising:
-connecting a solid-state imaging element (‘image sensor chip’ (20); Fig. 4, Paragraphs [0043] and [0054]) to a substrate ((10), consisting of portions (1), (1a), and (1b); Fig. 4, Paragraph [0042]) by a wire ((30); Fig. 4, Paragraph [0045]), wherein the solid-state imaging element (20) includes:
-a pixel region, wherein the pixel region includes an array of a plurality of pixels ((PA); Fig. 12, Paragraph [0043]); and
-a circuit region, wherein the circuit region includes a circuit ((EA); Fig. 12, Paragraphs [0043] and [0044]) that is adjacent to the pixel region (PA);
-bonding (Figs. 6 and 7, Paragraph [0056]), with an adhesive ((35); Figs. 6 and 7, Paragraph [0048]), the circuit region (EA) and an extended portion of a frame (e.g. portion (40a) of ‘holder’ (40); Fig. 6 and 7, Paragraph [0046]), wherein
-the frame includes an inner wall (e.g. (40c)) and an outer periphery portion (e.g. (40b)),
-the inner wall of the frame (40c) surrounds an outer periphery of the solid-state imaging element (20),
-the extended portion of the frame (40a) is extended from the outer peripheral portion (40b) to the circuit region (EA), and
-the plurality of wires (30) is outside a layer of the adhesive (e.g. the top left layer of (35) between the left (40a) and (20)). (As is indicated by the ‘second empty space’ (S2); Fig. 12, Paragraph [0066])
(Examiner notes that this method is a variant of the method shown in Figs. 3 to 9 to reach the fourth embodiment of the device of Fig. 12, Paragraphs [0065] and [0066], such that (35) “may only be disposed between the bottom surface of the inner cover part (40a) and the semiconductor chip (20) and between the bottom surface of the outer cover part (40c) and the package substrate (10).”)
Regarding Claim 7, Tae teaches an electronic device (e.g. ‘digital camera’ (6000); Fig. 19, Paragraph [0073]) comprising:
-a solid-state imaging element (‘image sensor chip’ (20); Fig. 12, Paragraph [0043]), wherein the solid-state imaging element (20) includes:
-a pixel region, wherein the pixel region includes an array of a plurality of pixels ((PA); Fig. 12, Paragraph [0043]); and
-a circuit region, wherein the circuit region includes a circuit ((EA); Fig. 12, Paragraphs [0043] and [0044]) that is adjacent to the pixel region (PA);
-a frame (‘holder’ (40) consisting of portions (40a), (40b), and (40c); Fig. 12, Paragraph [0046]) wherein
-the frame includes an inner wall (e.g. (40c)) and an outer periphery portion (e.g. (40b)),
-the inner wall of the frame (40c) surrounds an outer periphery of the solid-state imaging element (20),
-the inner wall (40c) of the frame includes an extended portion (e.g. (40a)), and
-the extended portion of the frame (40a) is extended from the outer peripheral portion (40b) to the circuit region (EA);
-an adhesive ((35); Fig. 2A, Paragraph [0048]) that bonds the extended portion of the frame (40a) and the circuit region (EA), wherein
-a plurality of wires ((30); Fig. 12, Paragraph [0045]) is outside a layer of the adhesive (e.g. the top left layer of (35) between the left (40a) and (20)). (As is indicated by the ‘second empty space’ (S2); Fig. 12, Paragraph [0066]); and
-an optical unit (e.g. a camera lens; Fig. 19) configured to:
-collect light (via the lens itself); and
-guide the light to the solid-state imaging element ((20)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/D.M./Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812