Detailed Action
This office action is in response to applicant’s submission filed on July 18, 2025. Claims 3 and 5-6 have been canceled. Claims 7 and 8 have been previously canceled. Claims 1-2, 4, 9-22 are pending and rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This communication is in response to the amendment filed on July 18, 2025. The Examiner has acknowledged the amended claims 1, 4, 9, 10, 14, 17-19, and 21. Claims 1-2, 4, 9-22 are pending and are rejected.
Response to Arguments
Applicant’s Arguments (Remarks) filed July 18, 2025 have been fully considered, but are not persuasive. Note that this action is made FINAL. See MPEP § 706.07(a).
Applicant’s amendments have already been claimed in present and past dependent claims in a reworded format as they were brought up from claims 5 and 6. Applicant argued that although Chen and Harland mention the role of CPLD in protecting and monitoring I2C bus, neither specifically mentions that dual verification of the state of the BMC and hardware configuration jumper is required before the command is sent, which is a key difference from the described distinguishing features. However, in the described distinguishing features of the present application, a multilayer verification mechanism is introduced: with regard to a command of a second level, it depends on the feedback of a BMC to judge whether the command is allowed to be executed; While for the third level of commands, it further requires that the hardware configuration jumper be in the enabled state. Such a dual verification mechanism is not disclosed or suggested in the cited references (page 3 of Remarks dated 07/18/2025). Examiner respectfully disagrees. Harland teaches a system where messages like power states messages are influenced by hardware configuration (jumpers/bridges). The hardware here indirectly affects which messages are generated. The logic device checks which messages are allowed or blocked reflecting firmware/BMC verification. This sets the stage for dual verification as it identifies messages influences by hardware, which must pass the logic device’s check [Col. 3, lines 18-24]. There is also an explicit check against access policy, plus sending response (ACK/NAK) to indicate approval [Col. 16, lines 15-26]. Examiner also wants to note that the bridge FSM acts like a hardware gate (analogous to the jumper) as a command cannot proceed unless the bridge FSM allows it, mirroring how a jumper must be “on” for a command to execute. This means there is a filter FSM + pattern matcher + access policy implementation for software/BMC approval [Col. 15, lines 7-39]. This shows that there is a dual verification done by a hardware-like and software-like component that are considered before a command is sent. The hardware jumper is a physical gate; a command can only proceed if it is in the correct state (“on” or “off). The bridge FSM is acting as a gatekeeper for commands/messages as it blocks messages that do not match the expected pattern and allows messages that do match to pass through. Functionally, it is analogous to a jumper as they both control the flow of allowed operations based on some condition. Therefore, the rejections have been made based off of the same rationale. See also 103 rejection below.
For the above reasons, Examiner maintains that Chen and Harland teach each and every limitation as currently claimed.
Applicant amended claim 10, and therefore the 101 rejection is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, and 9-22 are rejected under 35 U.S.C. 103 as being unpatentable over CN 108777639 A to Chen in view of US 10387672 B1 to Harland et al. (hereinafter, “Harland”).
Regarding claim 1, Chen discloses: A method for monitoring an I2C, the method being applied to a complex programmable logic device (CPLD), the CPLD being connected to a baseboard management controller (BMC) and a device by an inter-integrated circuit (I2C) (“In the server design, the BMC of the baseboard management controller BMC is remotely operated through the special port of the baseboard management controller BMC, and the CPLD is added between the baseboard management controller BMC and the IC, so that the CPLD performs data transmission through the I2C bus” [page 1]), respectively, the method comprising:
obtaining a first command from the BMC (“the data write of the I2C bus of the BMC to Command = 0x02 is completed” [page 2]);
recognizing a level of the first command according to a pre-stored command level list (“Preferably, the instruction of the internal register read-write operation is divided according to the data table data sheet of the IC, level division is performed on the instruction according to the importance, when the command = 0x01 indicates that the read-write operation is performed on the register 1, when the command = 0x02 indicates that the read-write operation is performed on the register 2, the command = 0x02 is higher than the command = 0x01, and in the product mass production stage, any modification action on the register 2 inside the IC is prohibited” [page 1] [Examiner notes that there is a pre-stored table filled with various command levels that the register can refer to in order to recognize the security parameters of each command]),
wherein the level comprises a first level, a second level, and a third level, a security level of the third level is higher than a security level of the second level, and the security level of the second level is higher than a security level of the first level (“Preferably, the instruction of the internal register read-write operation is divided according to the data table data sheet of the IC, level division is performed on the instruction according to the importance, when the command = 0x01 indicates that the read-write operation is performed on the register 1, when the command = 0x02 indicates that the read-write operation is performed on the register 2, the command = 0x02 is higher than the command = 0x01, and in the product mass production stage, any modification action on the register 2 inside the IC is prohibited. Preferably, the importance level is determined by whether the change of the value in the register affects the function of the IC, the change of the value in Register 1 has no effect on the function implementation of the IC, and the value change in the Register 2 causes the function failure of the IC” [page 1]; “Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that text describes how the combination of stating that the command = 0x02 is higher than command 0x01 and the behavior of blocking 0x02 to protect important registers shows a system that is treating the command of a higher level more sensitive and important. 0x02 has a higher priority or security concern and the system uses this to handle it stricter than 0x01 and so forth. Examiner interprets that the next command (= 0x03) would be higher and the determinations will continue. CPLD is added between BMC and IC, so that CPLD transmits data through I2C information level, and divides the instructions for internal register write operation according to the data-sheet of IC, that is, the instruction level is divided according to the importance, command = 0x01 (relative to the first level) is to write to register 1, and command = 0x02 (relative to the second level) is to write to register 2; command = 0x02 is more important than command = 0x01 (relative to the security level of the second level is higher than the first level) ; When the monitoring module in the CPLD parses command = Ox02 and wants to perform a write operation, the write operation when command = Ox 02 is prohibited; the CPLD detects the I2C of the BMC, and after the data writing of command = Ox02 is completed, it re-enables the I2C between the BMC and the IC, thereby ensuring that other data can be written normally]); and
sending the first command to the device in different modes according to the level of the first command (“Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that it depends on the command level for the data to be sent, how it will be sent, and if it will be sent]),
Chen does not explicitly disclose: wherein sending the first command to the device in the different modes according to the level of the first command comprises: reading a sending mode parameter of the first command from the command level list according to the level of the first command; and sending the first command to the device according to the sending mode parameter of the first command wherein reading the sending mode parameter of the first command from the command level list according to the level of the first command comprises: in a case that the level of the first command is the second level, reading the sending mode parameter of the first command from the command level list, and obtaining a second preset parameter; sending the first command to the device according to the sending mode parameter of the first command comprises: returning the first command to the BMC according to the second preset parameter, so that the BMC outputs first prompt information according to the first command; receiving first reply information sent by the BMC according to the first prompt information; in a case that the first reply information meets a preset condition, modifying the sending mode parameter of the first command to the first preset parameter; and directly sending the first command to the device according to the first preset parameter, in a case that the level of the first command is the third level, reading the sending mode parameter of the first command from the command level list, and obtaining a second preset parameter; sending the first command to the device according to the sending mode parameter of the first command comprises: returning the first command to the BMC according to the second preset parameter, so that the BMC outputs second prompt information according to the first command; receiving turn-on information of a security setting jumper and second reply information sent by the BMC according to the second prompt information, wherein the security setting jumper is initially in a turn-off state; in a case that the second reply information meets a preset condition, modifying the sending mode parameter of the first command to the first preset parameter; and directly sending the first command to the device according to the first preset parameter and the turn-on information of the security setting jumper.
However, Harland discloses: wherein sending the first command to the device in the different modes according to the level of the first command comprises: reading a sending mode parameter of the first command from the command level list according to the level of the first command; and sending the first command to the device according to the sending mode parameter of the first command wherein reading the sending mode parameter of the first command from the command level list according to the level of the first command comprises: in a case that the level of the first command is the second level, reading the sending mode parameter of the first command from the command level list, and obtaining a second preset parameter; sending the first command to the device according to the sending mode parameter of the first command comprises: returning the first command to the BMC according to the second preset parameter, so that the BMC outputs first prompt information according to the first command; receiving first reply information sent by the BMC according to the first prompt information (“The chipset may then relay any received messages to the BMC and may in turn receive a “message acknowledged” or “ACK” message, or alternatively may receive a “message not acknowledged” or “NAK” message, indicating whether the message was permitted access to the BMC. In other embodiments, one or both of the CPU and/or management engine are disposed within the chipset itself, which still performs the above-noted operations” [Col. 2 lines 57 - 65]; “As illustrated in FIG. 1, in protection of unwanted access to the BMC 170, the CPLD 110 is disposed in stream of the data traffic between the VMI's 120, 130, 140, the chipset 190, and the BMC 170. The CPLD 110 may be configured in any fashion, and can allow specific messages, specific message types, headers, or metadata, content, or any other identifying information to be allowed or blocked by the CPLD 110. In an embodiment, the CPLD 110 allows only messages such as message 4, 151 from the chipset 190 (including messages originating from the CPU 160 such as BIOS 150 errors, CPU 160 or management engine 180 messages, etc.) to propagate to the BMC 170. Errant, malicious, redundant, or irrelevant messages such as messages 121, 131, and 141 are NAK′d (NAK 1-3, messages 122, 132, and 142) to protect the BMC 170 asset from each of the threats mentioned above. As previously discussed, the CPU 160 may suffer from a BIOS 150 error which may need to be given direct access to the BMC 170 for a corrective response. In this instance, the CPLD 110 decides if the message is an authenticated control plane error message (such as a BIOS error message), and depending on the determination, take any necessary action (if applicable). The message type (such as being a control plane error message) may be identified by any portion of the submitted message such as in the message metadata, header, payload, origin (such as an IP address or memory location), etc. Once such a genuine message is received, the CPLD 110 can allow passage of the message to the BMC 170, and may also send an ACK (ACK/NAK 1, 152) to the chipset 190 notifying it that the message has been received and was transmitted to the BMC 170. Alternatively, if the message is unauthorized (regardless of source), a NAK is generated by the CPLD 110 indicating to the originating source that the message was not delivered to the BMC 170. As noted in FIG. 1, messages from the control plane are not always automatically ACK′d, depending on whether or not they are error messages, otherwise authorized control plane messages, or neither. For this reason, control plane messages may receive ACK/NAK 1-3 (152, 162, and 172). However, messages originating from VMI's 120, 130 and 140 are always NAK′d (NAK 1, 122, NAK 2, 132, and NAK 3, 142) for security reasons” [Col. 5 line 53 – Col. 6 line 26] [Examiner notes that returning a command is a way for the system to acknowledge, reject, or handle an incoming instruction. It helps ensure that the right commands are acted upon and unauthorized ones are controlled. This then leads to the system sending out an "ACK" or "NACK" response message to show that if the command went through or not]);
in a case that the first reply information meets a preset condition, modifying the sending mode parameter of the first command to the first preset parameter; and directly sending the first command to the device according to the first preset parameter (“In some embodiments, multiple filter FSMs may be used, each matching different patterns. For example, a filter FSM may be configured to match a write address for an EEPROM (which may include a 7-bit address and write flag). Upon matching the pattern, the write can be allowed. If the pattern is not matched, a stop condition may be forced to the output 512 and a “No Acknowledgement” (NACK) condition is returned. Other patterns may be used to match known commands, including IMPB commands. In some embodiments, a masking filter FSM may be configured to match a read address for an EEPROM, bus, or other address. If the read address is matched, the data being read may be replaced by data specified by the access policy. For example, the access policy may include a pointer to a different memory address including data to be provided in place of the requested data. In some embodiments, the masking filter FSM may be configured to replace all or a portion of the requested data with 0s or 1s. The portion of the requested data to be masked may be specified by the access policy” [Col. 15, lines 40 - 58] [Examiner notes that replacing here can be seen as modifying the parameters of the commands before transmission occurs, this way, it can follow access policies already distinguished by the system]),
in a case that the level of the first command is the third level, reading the sending mode parameter of the first command from the command level list, and obtaining a second preset parameter; sending the first command to the device according to the sending mode parameter of the first command comprises: returning the first command to the BMC according to the second preset parameter, so that the BMC outputs second prompt information according to the first command (“The chipset may then relay any received messages to the BMC and may in turn receive a “message acknowledged” or “ACK” message, or alternatively may receive a “message not acknowledged” or “NAK” message, indicating whether the message was permitted access to the BMC. In other embodiments, one or both of the CPU and/or management engine are disposed within the chipset itself, which still performs the above-noted operations” [Col. 2, lines 57 - 65]; “As illustrated in FIG. 1, in protection of unwanted access to the BMC 170, the CPLD 110 is disposed in stream of the data traffic between the VMI's 120, 130, 140, the chipset 190, and the BMC 170. The CPLD 110 may be configured in any fashion, and can allow specific messages, specific message types, headers, or metadata, content, or any other identifying information to be allowed or blocked by the CPLD 110. In an embodiment, the CPLD 110 allows only messages such as message 4, 151 from the chipset 190 (including messages originating from the CPU 160 such as BIOS 150 errors, CPU 160 or management engine 180 messages, etc.) to propagate to the BMC 170. Errant, malicious, redundant, or irrelevant messages such as messages 121, 131, and 141 are NAK′d (NAK 1-3, messages 122, 132, and 142) to protect the BMC 170 asset from each of the threats mentioned above. As previously discussed, the CPU 160 may suffer from a BIOS 150 error which may need to be given direct access to the BMC 170 for a corrective response. In this instance, the CPLD 110 decides if the message is an authenticated control plane error message (such as a BIOS error message), and depending on the determination, take any necessary action (if applicable). The message type (such as being a control plane error message) may be identified by any portion of the submitted message such as in the message metadata, header, payload, origin (such as an IP address or memory location), etc. Once such a genuine message is received, the CPLD 110 can allow passage of the message to the BMC 170, and may also send an ACK (ACK/NAK 1, 152) to the chipset 190 notifying it that the message has been received and was transmitted to the BMC 170. Alternatively, if the message is unauthorized (regardless of source), a NAK is generated by the CPLD 110 indicating to the originating source that the message was not delivered to the BMC 170. As noted in FIG. 1, messages from the control plane are not always automatically ACK′d, depending on whether or not they are error messages, otherwise authorized control plane messages, or neither. For this reason, control plane messages may receive ACK/NAK 1-3 (152, 162, and 172). However, messages originating from VMI's 120, 130 and 140 are always NAK′d (NAK 1, 122, NAK 2, 132, and NAK 3, 142) for security reasons” [Col. 5, line 53 – Col. 6, line 26] [Examiner notes that returning a command is a way for the system to acknowledge, reject, or handle an incoming instruction. It helps ensure that the right commands are acted upon and unauthorized ones are controlled. This then leads to the system sending out an "ACK" or "NACK" response message to show that if the command went through or not]);
receiving turn-on information of a security setting jumper and second reply information sent by the BMC according to the second prompt information, wherein the security setting jumper is initially in a turn-off state (“As further described below, control plane messages will be frequently referred to simply as error messages (often BIOS error messages). These are more frequently observed than other control plane error messages. Other related control plane messages such as read event buffer messages, power state messages, and others could also constitute a family of generic messages that may be allowed or blocked by the logic device” [Col. 3, lines 18 - 34]; “At step 606, the logic device 402 checks if the message type or memory location of the message matches the corresponding entries of the access policy 414 as being an authorized control plane message type, which could include a BIOS error message, or any other authorized message type such as a read event buffer or power state message. At step 608, if the match is successful, the message is allowed to be transmitted to the BMC 412. At 610, alternatively, the message is blocked. At step 612, an appropriate response, based on the one or more access policies 414, is returned to the PCH 408 or an associate server by the logic device 402” [Col. 16, lines 15 – 26]; “FIG. 5 illustrates a finite state machine 500 implementing secure error handling as implemented by the logic device 402 (shown in FIG. 4), in accordance with various embodiments. As shown in FIG. 5, error handling may be implemented over an I2C protocol in the logic device 402. As previously noted, further embodiments can use other protocols, such as PCI-e, I2C, SMBus, SMBus System Interface (SSIF), Intelligent Platform Management Bridge/Bus (IPMB), PMBus, SPI, Intelligent Chassis Management Bus (ICMB) or any other protocol. A message over the I2C may be received at input 504 and passed to an I2C bridge finite state machine (hereinafter FSM) 506. The bridge FSM 506 may act as the analysis monitor 404 (shown in FIG. 4). The bridge FSM 506 may determine a command from the message packet. The command may pertain to a platform event. This data may be passed to a filter FSM 508. The filter FSM 508 may be an implementation of the message filter 410 (shown in FIG. 4) and performs filtering of the messages based on the access policies. The filter FSM 508 can also pass the details of the message to a pattern matcher 510. The pattern matcher 510 may define one or more read/write sequences that represent known commands (such as SMBUS commands). These specific sequences or patterns can be identified by the filter FSM 508 using the pattern data of pattern matcher 510. Based on the match, the pattern matcher 510 can return policy details, which might be a write block parameter whose value indicates whether the message may be allowed. For example, if write block is 1, the bridge FSM 506 may allow the write. The message is passed to an output 512 and a response indicative of transmission of the message may be returned to the platform controller hub 408 (shown in FIG. 4)” [Col. 15, lines 7-39] [Examiner notes that by receiving power state messages, whether the device is on and it is turning off or vice versa, the jumper (bridge) influences how BIOS handles power-related events. This is not novel as it is known in the art that jumpers or bridges can directly affect the power state and BIOS behavior of a system by handling the configurations]);
in a case that the second reply information meets a preset condition, modifying the sending mode parameter of the first command to the first preset parameter; and directly sending the first command to the device according to the first preset parameter and the turn-on information of the security setting jumper (“In some embodiments, multiple filter FSMs may be used, each matching different patterns. For example, a filter FSM may be configured to match a write address for an EEPROM (which may include a 7-bit address and write flag). Upon matching the pattern, the write can be allowed. If the pattern is not matched, a stop condition may be forced to the output 512 and a “No Acknowledgement” (NACK) condition is returned. Other patterns may be used to match known commands, including IMPB commands. In some embodiments, a masking filter FSM may be configured to match a read address for an EEPROM, bus, or other address. If the read address is matched, the data being read may be replaced by data specified by the access policy. For example, the access policy may include a pointer to a different memory address including data to be provided in place of the requested data. In some embodiments, the masking filter FSM may be configured to replace all or a portion of the requested data with 0s or 1s. The portion of the requested data to be masked may be specified by the access policy” [Col. 15, lines 40 – 58] [Examiner notes that replacing here can be seen as modifying the parameters of the commands before transmission occurs, this way, it can follow access policies already distinguished by the system]).
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, to combine the method of Chen’s I2C monitoring methods with the added structure of Harland’s secure message handling elements in order for the system to respond and verify any action applied as Harland suggests [Col. 2, line 4 – Col. 3, line 5]).
Regarding claim 2, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: obtaining a second command from the device and sending the second command to the BMC (“CPLD detects that the data write of the I2C bus of the BMC to Command = 0x02 is completed” [page 2]),
wherein the second command corresponds to the first command, so that the BMC determines the level of the first command according to the second command (“Therefore, firstly, the command instruction that the chip is allowed to exist and the specific operation corresponding to each command are first required, and the I2C data is monitored and protected for a specific command in the quantity production stage of the server product” [page 2] [Examiner notes that the chip has a predefined set of allowed commands - it doesn't accept arbitrary instructions. So for each valid command, there should be a structures or logical relationship between them. Examiner then interprets that the security level can be accessed in part by comparing commands across a sequence. This is especially true in designs using CPLDs to filter/block on command type and importance]);
receiving the level of the first command (“Preferably, the instruction of the internal register read-write operation is divided according to the data table data sheet of the IC, level division is performed on the instruction according to the importance, when the command = 0x01 indicates that the read-write operation is performed on the register 1, when the command = 0x02 indicates that the read-write operation is performed on the register 2, the command = 0x02 is higher than the command = 0x01, and in the product mass production stage, any modification action on the register 2 inside the IC is prohibited” [page 1]); and
generating the command level list according to the level of the first command (“Secondly, the instruction of the internal register read/write operation is divided according to the data table data sheet of the IC, and level division is performed on the instruction according to importance, for example, when command = 0x01 is to perform a read/write operation on Register 1, when Command = 0x02 is to perform a read/write operation on Register 2, the change of the value in Register 1 has no effect on the function implementation of the IC, but the value change in Register 2 causes the function of the IC to fail. Therefore, Command = 0x02 is higher in importance than Command = 0x01. In the product mass production phase, it is not allowed to perform any modification action on Register 2 inside the IC” [page 2] [Examiner notes that this text describes a system capable of organizing instructions based on their level of importance. It generates a type of hierarchy to handle commands appropriately and securely]).
Regarding claim 4, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: in a case that the level of the first command is the first level, reading the sending mode parameter of the first command from the command level list, and obtaining a first preset parameter (“Preferably, the instruction of the internal register read-write operation is divided according to the data table data sheet of the IC, level division is performed on the instruction according to the importance, when the command = 0x01 indicates that the read-write operation is performed on the register 1, when the command = 0x02 indicates that the read-write operation is performed on the register 2, the command = 0x02 is higher than the command = 0x01, and in the product mass production stage, any modification action on the register 2 inside the IC is prohibited” [page 1] [Examiner notes that there is a pre-stored table filled with various command levels that the register can refer to in order to recognize the security parameters of each command]);
sending the first command to the device according to the sending mode parameter of the first command comprises: directly sending the first command to the device according to the first preset parameter (“Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that it depends on the command level for the data to be sent, how it will be sent, and if it will be sent]).
Claim 9 recites substantially the same limitation as claim 1, in the form of a system for implementing the corresponding method, therefore it is rejected under the same rationale. Examiner notes that the elements listed in this claim are taught by Chen including: “an inter-integrated circuit (I2C), a baseboard management controller (BMC), a complex programmable logic device (CPLD), a device, and… , wherein the CPLD is connected to the BMC and the device by the I2C” (“BMC, and the CPLD is added between the baseboard management controller BMC and the IC, so that the CPLD performs data transmission through the I2C bus” [page 1]) and “an executable program stored on the CPLD,” (“CPLD serves as a monitoring module to parse the data on the I2C bus in real time” [page 2] [Examiner notes that the CPLD is parsing signals like I2C commands. This behavior stems from a program stored in it]).
Claim 10 recites substantially the same limitation as claim 1, in the form of a non-transitory computer readable medium comprising computer readable program code for implementing the corresponding method, therefore it is rejected under the same rationale.
Regarding claim 11, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: wherein, a command of the first level is an ordinary register read operation (“when the command = 0x01 indicates that the read-write operation is performed on the register 1” [page 1]).
Regarding claim 12, Chen discloses: wherein, a command of the second level is a register write operation, which configured to change an operating state of the device (“Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that the command of the second level is seen as changing an operating state of the device because it is locking write access to certain protected registers]).
Regarding claim 13, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: wherein, a command of the third level is a sensitive operation which includes at least one of the following: setting the device to be shut down, setting the device to be powered off, setting the device to be reset, and setting the device to be restarted (“BMC is used as a small operating system independent of a server system, and can be operated remotely to facilitate operations such as remote management, monitoring, installation, restart and the like of the server” [page 1] [Examiner notes here that the BMC can restart a server by sending a command to trigger the restart operation]).
Regarding claim 14, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: wherein, different sending mode parameters are set according to commands of different security levels (“Preferably, the instruction of the internal register read-write operation is divided according to the data table data sheet of the IC, level division is performed on the instruction according to the importance, when the command = 0x01 indicates that the read-write operation is performed on the register 1, when the command = 0x02 indicates that the read-write operation is performed on the register 2, the command = 0x02 is higher than the command = 0x01, and in the product mass production stage, any modification action on the register 2 inside the IC is prohibited” [page 1] [Examiner notes that there is a pre-stored table filled with various command levels that the register can refer to in order to recognize the security parameters of each command]; “Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that it depends on the command level for the data to be sent, how it will be sent, and if it will be sent]).
Regarding claim 15, a combination of Chen-Harland discloses all limitations of claim 4.
Furthermore, Chen discloses: wherein, when the BMC sends the first command to the device, the first command is monitored in real time by the CPLD (“The CPLD is added to the hardware design to monitor and protect the data on the I2C bus, the CPLD serves as a monitoring module to parse the data on the I2C bus in real time” [page 2]).
Regarding claim 16, a combination of Chen-Harland discloses all limitations of claim 4.
Furthermore, Chen discloses: wherein, when the first preset parameter is set to be 1, which indicates that the first command is allowed to be sent, the CPLD directly transmits the first command back to the device (“CPLD performs data transmission through the I2C bus” [page 1] [Examiner notes that since the system recognizes when the data transmission should be disabled, it can automatically recognize when it is legal and secure]).
Regarding claim 17, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: wherein, when the second preset parameter is set to be 0, which indicates that the command is not allowed to be sent, the CPLD directly sets a clock signal and a data signal of the device to be both at high levels, so as to prevent the command from being transmitted to the device (“Preferably, the I2C bus may be replaced with an SPI bus” [page 2]; “Preferably, a monitoring module is arranged inside the CPLD, and the monitoring module can monitor the data of the I2C signal, analyze the I2C address of the data on the I2C bus, and the command instruction on the I2C bus. Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that the CPLD has a monitoring module that watches the I2C communication. It analyzes both the IC address and the command instruction on the I2C bus and when it detects a command like 0x02, it can take action to prevent a write operation. It does this by triggering a disable signal that prevents the data from being transmitted into the target IC. When the CPLD pulls the IC bus high, Examiner is interpreting this as setting the block and/or data line high in order to halt the transmission of data. This is especially true in this case because a SPI bus includes a SCLK or Serial Clock which contains the clock signal generated by the master]).
Regarding claim 18, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: wherein modifying the sending mode parameter of the first command to the first preset parameter comprises: when the sending mode parameter is set to be 0, modifying the sending mode parameter to 1 (“it is not allowed to perform any modification action on Register 2 inside the IC” [page 1] [Examiner notes that modifications are not novel and can happen but some systems, including this one, does not allow modifications because of malicious actors causing a security threat]).
Regarding claim 19, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: in a case that the sending mode parameter automatically restore to initial value thereof in preset time after being modified, re-modifying the sending mode parameter for sending the first command of the second level (“it is not allowed to perform any modification action on Register 2 inside the IC” [page 1] [Examiner notes that modifications are not novel and can happen but some systems, including this one, does not allow modifications because of malicious actors causing a security threat]).
Regarding claim 20, a combination of Chen-Harland discloses all limitations of claim 19.
Furthermore, Chen discloses: wherein the initial value of the sending mode parameter is initial set value of the sending mode parameter in the command level list (“Preferably, the instruction of the internal register read-write operation is divided according to the data table data sheet of the IC, level division is performed on the instruction according to the importance, when the command = 0x01 indicates that the read-write operation is performed on the register 1, when the command = 0x02 indicates that the read-write operation is performed on the register 2, the command = 0x02 is higher than the command = 0x01, and in the product mass production stage, any modification action on the register 2 inside the IC is prohibited” [page 1] [Examiner notes that there is a pre-stored table filled with various command levels that the register can refer to in order to recognize the security parameters of each command]; “Preferably, when the command = 0x02, the write operation is prohibited, the CPLD immediately triggers the internal disable signal, and pulls the I2C bus high, so that the data behind the command = 0x02 is truncated, so that the data cannot be transmitted into the I2C, thereby protecting the important register in the I2C” [page 2] [Examiner notes that it depends on the command level for the data to be sent, how it will be sent, and if it will be sent]).
Regarding claim 21, a combination of Chen-Harland discloses all limitations of claim 1.
Furthermore, Chen discloses: in a case of the sending mode parameter automatically restore to initial value thereof in preset time after being modified, re-modifying the sending mode parameter for sending the first command of the third level (“it is not allowed to perform any modification action on Register 2 inside the IC” [page 1] [Examiner notes that modifications are not novel and can happen but some systems, including this one, does not allow modifications because of malicious actors causing a security threat]).
Regarding claim 22, Chen discloses all limitations of claim 21.
Chen does not explicitly disclose: wherein the security setting jumper represents a jumper of the device.
However, Harland discloses: wherein the security setting jumper represents a jumper of the device (“A message over the I2C may be received at input 504 and passed to an I2C bridge finite state machine (hereinafter FSM) 506. The bridge FSM 506 may act as the analysis monitor 404 (shown in FIG. 4). The bridge FSM 506 may determine a command from the message packet. The command may pertain to a platform event. This data may be passed to a filter FSM 508. The filter FSM 508 may be an implementation of the message filter 410 (shown in FIG. 4) and performs filtering of the messages based on the access policies. The filter FSM 508 can also pass the details of the message to a pattern matcher 510. The pattern matcher 510 may define one or more read/write sequences that represent known commands (such as SMBUS commands). These specific sequences or patterns can be identified by the filter FSM 508 using the pattern data of pattern matcher 510. Based on the match, the pattern matcher 510 can return policy details, which might be a write block parameter whose value indicates whether the message may be allowed. For example, if write block is 1, the bridge FSM 506 may allow the write. The message is passed to an output 512 and a response indicative of transmission of the message may be returned to the platform controller hub 408 (shown in FIG. 4)” [Col. 15, lines 17 – 39] [Examiner notes that this text illustrates how the jumper (bridge) is in charge of configuring and filtering commands based on the access policies defined. It is a jumper of the device but also is a security setting jumper because of its role in the system]).
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains, to combine the method of Chen’s I2C monitoring methods with the added structure of Harland’s analysis processing elements in order for the system to respond and pertain to a platform event applied as Harland suggests [Col. 15, lines 17 – 39]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/SARON MATTHEWOS WORKU/Examiner, Art Unit 2408
/MORSHED MEHEDI/Primary Examiner, Art Unit 2408
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