DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 07/10/2023.
Claims1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 07/10/2023. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wyland (US 2020/0083171)
Regarding claim 1, Wyland discloses an integrated circuit (IC) support, shown in figs. 5-7, 10-12, comprising:
a first microstrip 700 (see fig. 7A), wherein the first microstrip includes a first conductive line 720 (in layer 755L3 of fig. 7A, or conductive line in layer 915 of fig. 10; see paras. 0041, 0045), a ground plane 730 (in layer 755L1, fig. 7A, which is equivalent to ground plane 615 in fig. 6, para. 0041), and a first dielectric material 755L2 (fig. 7A) or 916 (fig. 10) between the first conductive line 720/755L3/915 and the ground plane 730/755L1/917;
a second microstrip (Fig. 6 shows multiple microstrips formed in substrate 610), wherein the second microstrip includes a second conductive line 720 (as shown in fig. 7A, or a second conductive line in layer 915 of fig. 10) coplanar with the first conductive line;
a second dielectric material 755L4 (fig. 7A) or 914 (fig. 10) at least partially over the first conductive line 720/915 and the second conductive line 720/915; and
a conductive segment 710 (in layer 755L5 in fig. 7A; or conductive segment in layer 913 in fig. 10), wherein the second dielectric material 755L4/914 is between the conductive segment 710/755L5/913 and the first conductive line 720/755L3/915, the second dielectric material 755L4/914 is between the conductive segment 710/755L5/913 and the second conductive line 720/915, the conductive segment is at least partially over the first conductive line 720/915 and at least partially over the second conductive line 720/915, and the conductive segment is included in a tape (see para. 0042).
Regarding claim 2, Wyland discloses the IC support of claim 1,wherein at least some of the second dielectric material 755L4/914 is included in the tape. See figs. 7, fig. 10.
Regarding claim 3, Wyland discloses the IC support of claim 1, wherein some of the second dielectric material 755L4/914 is included in the tape, and some of the second dielectric material is not included in the tape. See figs. 7, 10.
Regarding claim 4, Wyland discloses the IC support of claim 1,wherein a thickness of the conductive segment is between 5 microns and 20 microns. See paras. 0040-0042.
Regarding claim 5, Wyland discloses the IC support of claim 1,further comprising: a third dielectric material 755L6/912 (fig. 7A/fig. 10) over the conductive segment.
Regarding claim 6, Wyland discloses the IC support of claim 5, wherein the third dielectric material is included in the tape. See figs. 5-10.
Regarding claim 7, Wyland discloses the IC support of claim 1,further comprising:
a third microstrip, wherein the third microstrip includes a third conductive line (in layer 915 of fig. 10) coplanar with the second conductive line such that the second conductive line is between the first conductive line and the third conductive line. See figs. 10.
Regarding claim 8, Wyland discloses the IC support of claim 7, wherein the conductive segment (one of the conductive segments in layer 755L5, fig. 7A) is a first conductive segment, and the IC support further includes:
a second conductive segment (another of the conductive segments in layer 755L5), wherein the second dielectric material 755L4 is between the second conductive segment and the second conductive line, the second dielectric material is between the second conductive segment and the third conductive line, the second conductive segment is at least partially over the second conductive line and at least partially over the third conductive line, and the second conductive segment is included in the tape. See also paras. 0040-0042.
Regarding claim 9, Wyland discloses a tape ((figs. 5-7, 10-12, and para. 0042) for use in an integrated circuit (IC) support, comprising:
a first conductive segment 710 (in layer 755L5 in fig. 7A; or conductive segment in layer 913 in fig. 10), wherein, when the tape is applied to an underlying structure including a first conductive line 720 (in layer 755L3 of fig. 7A, or a first conductive line in layer 915 of fig. 10; see paras. 0041, 0045), a second conductive line 720/915, and a third conductive line 720/915 (See also figs. 6; fig. 6 shows multiple microstrips comprising a plurality of conductive segments and conductive lines formed in substrate 610), the first conductive segment 710/913 is at least partially over the first conductive line 720/915 and at least partially over the second conductive line 720/915; and
a second conductive segment 710/913, wherein, when the tape is applied to the underlying structure, the second conductive segment 710/913 is at least partially over the second conductive line 720/915 and at least partially over the third conductive line 720/915.
Regarding claim 10, Wyland discloses the tape of claim 9, wherein a conductivity of the first conductive segment is less than a conductivity of the first conductive line. See paras. 0040-0042.
Regarding claim 11, Wyland discloses the tape of claim 9, wherein a conductivity of the second conductive segment is less than the conductivity of the first conductive line. See paras. 0040-0042.
Regarding claim 12, Wyland discloses the tape of claim 9, further comprising:
a dielectric material, wherein, when the tape is applied to the underlying structure:
the first conductive segment (in layer 755L5, fig. 7A, or conductive layer in layer 913) is spaced apart from the first conductive line 720 and the second conductive line (see fig. 10) by the dielectric material 755L4/914 (fig. 7A/fig. 10); and
the second conductive segment (other conductive segment in layer 755L5, fig. 7A, or other conductive layer in layer 913) is spaced apart from the second conductive line and the third conductive line by the dielectric material.
Regarding claim 13, Wyland discloses the tape of claim 9, further comprising:
an adhesive surface. See fig. 5-10.
Regarding claim 14, Wyland discloses the tape of claim 9, further comprising:
perforations defining ends of portions of the tape. See figs. 5-10.
Regarding claim 15, Wyland discloses the tape of claim 9, wherein the tape is wound around a core. This is common in the art.
Regarding claim 16, Wyland discloses an electronic device, comprising:
an integrated circuit (IC) device 510 (see figs. 5-7, 10-12); and
an IC support coupled to the IC device, wherein the IC support includes:
a plurality of microstrips (comprising conductive line 720 in layer 755L3 of fig. 7A, or conductive lines in layer 915 of fig. 10; see paras. 0041, 0045; see also fig. 6), and
a plurality of conductive segments 710 (in layer 755L5 in fig. 7A; or conductive segment in layer 913 in fig. 10), wherein individual ones of the conductive segments 710/913 are at least partially over at least two microstrips 720/915 (fig. 10), a dielectric material 755L4 (fig. 7A) or 914 (fig. 10) is between the plurality of microstrips 720/915 and the plurality of conductive segments 710/913, and the plurality of conductive segments are included in a tape (para. 0042).
Regarding claim 17, Wyland discloses the electronic device of claim 16, wherein the IC device 510 is a first IC device , and the plurality of microstrips communicatively couple the first IC device to a second IC device 550. See figs. 5, 8-10.
Regarding claim 18, Wyland discloses the electronic device of claim 17, wherein the first IC device is a processing device. See para. 0006.
Regarding claim 19, Wyland discloses the electronic device of claim 17, wherein the second IC device is a memory device. See paras. 0015-0016.
Regarding claim 20, Wyland discloses the electronic device of claim 16, wherein the tape has a thickness between 25 microns and 250 microns. See para. 0034, paras. 0040-0042.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 November 26, 2025