Detailed Action
This office action is in response to the amendment filed on April 20th, 2026. Claims 1-3, 5-9, 11, and 13-15 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed April 20th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 8-11, “Remarks”) that Zhang fails to teach the limitations presented in amended Claims 1 and 7-8. Applicant argues that Zhang discloses a second channel layer 118b deposited over first channel layer 118a; however, it is the first channel layer 118a that is configured as an electron transfer assist layer. Zhang, par. [0040] ("One advantage of having Ge in first channel layer 118a is that Si-Ge composite layer may have higher electron and/or hole mobility."). Further, Zhang teaches away from using the second channel layer 118b for both purposes, as it teaches the second channel layer 118b having a lower Germanium concentration for the express purpose of "increase[ing] the on-current in the first channel layer 118a, while the higher Si/Poly-Si concentration in the second channel layer 118 b may provide better lattice matching with SEG structure 154 and effective back interface with dielectric filler 120," both of which are benefits provided by a protective layer. Id. at par. [0043]. As such, it cannot be said that Zhang teaches a second channel layer used as both a protection layer and an electron transfer assist layer.
Examiner notes that the applicant’s filed specification has defined that the first channel layer 321-1 may be formed of a material having a higher electron mobility than that of the second channel layer 321-2 ([54]). However, applicant’s arguments assert that the first channel layer 118a of Zhang is configured as an electron transfer assist for the reason of having a higher electron mobility than the second channel layer 118b. Furthermore, applicant’s first channel layer 321-1 is made of poly Si-Ge ([54]) and the second channel layer 321-2 is made of poly Si ([55]) in order to satisfy the above condition. Examiner notes that these are again the same assertions used against the first channel layer 118a and second channel layer 118b of Zhang. It is unclear as to how applicant’s arguments serve to differentiate the claimed invention from the prior art reference of Zhang.
Therefore, applicant’s arguments are not persuasive.
Applicant argues (pgs. 11-14, “Remarks”) that Zhang fails to teach the limitations presented in amended Claims 9 and 14.
However, as seen below, Claim 9 is rejected by the combination of Zhang and Saxler. Claim 14 is rejected by the combination of Zhang, Saxler, and Rabkin.
Therefore, applicant’s arguments are not persuasive and are moot in view the new grounds of rejection.
Applicant’s amendments have overcome the 35 U.S.C 112(b) rejection of the previous office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 7, and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In this instance, Claims 1, 7, and 8 recite the limitation “the second channel is used as a protection layer and an electron transfer assist layer for the first channel layer”. However, applicant’s filed specification only states that the second channel layer may be used as a protection layer or an electron transfer assist layer for the first channel layer ([0020], [0055], [0066], [0076]) and does not go on to describe embodiments where the second channel layer may be both. Therefore, applicant does not have support for the above limitation.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-8, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the second channel layer is used as a protection layer and an electron transfer assist layer for the first channel layer” in lines 11-12. See § 2173.03. “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971); In re Cohn, 438 F.2d 989, 169 USPQ 95 (CCPA 1971); In re Hammack, 427 F.2d 1378, 166 USPQ 204 (CCPA 1970).” In this instance, it is unclear which qualities the second channel layer may have as applicant’s filed specification only recites that the second channel layer may be either a protection layer or an electron transfer assist layer. For the purpose of examination, the limitation will be interpreted as written.
Claim 7 recites the limitation “the second channel layer is used as a protection layer and an electron transfer assist layer for the first channel layer” in lines 15-16. See § 2173.03. “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971); In re Cohn, 438 F.2d 989, 169 USPQ 95 (CCPA 1971); In re Hammack, 427 F.2d 1378, 166 USPQ 204 (CCPA 1970).” In this instance, it is unclear which qualities the second channel layer may have as applicant’s filed specification only recites that the second channel layer may be either a protection layer or an electron transfer assist layer. For the purpose of examination, the limitation will be interpreted as written.
Claim 8 recites the limitation “the second channel layer is used as a protection layer and an electron transfer assist layer for the first channel layer” in lines 18-19. See § 2173.03. “A claim, although clear on its face, may also be indefinite when a conflict or inconsistency between the claimed subject matter and the specification disclosure renders the scope of the claim uncertain as inconsistency with the specification disclosure or prior art teachings may make an otherwise definite claim take on an unreasonable degree of uncertainty. In re Moore, 439 F.2d 1232, 1235-36, 169 USPQ 236, 239 (CCPA 1971); In re Cohn, 438 F.2d 989, 169 USPQ 95 (CCPA 1971); In re Hammack, 427 F.2d 1378, 166 USPQ 204 (CCPA 1970).” In this instance, it is unclear which qualities the second channel layer may have as applicant’s filed specification only recites that the second channel layer may be either a protection layer or an electron transfer assist layer. For the purpose of examination, the limitation will be interpreted as written.
Claim 5 recites the limitation "an electron transfer assist layer" in line 2. It is unclear if this limitation refers to a second, different electron transfer assist layer or the electron transfer assist layer defined in lines 11-12 of Claim 1. For the purpose of examination, the limitation will be interpreted as “the electron transfer assist layer”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-3 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (2017/0263623 A1; hereinafter Zhang).
Regarding Claim 1, Zhang (fig. 2U) teaches a three-dimensional flash memory ([0013]) comprising:
a plurality of word lines ([0047], 122) extending on a substrate ([0024], 102) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U); and
at least one cell string ([0027], 100) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2U), the at least one cell string (100) including
a channel layer ([0043], 118a, 118b) extending in the vertical direction (up and down) and
a charge storage layer ([0038], 114, 116) formed to surround the channel layer (118a, 118b), wherein
the channel layer (118a, 118b) has a double structure including a first channel layer (118a) for improving an electron mobility ([0040], 118a has higher electron mobility) in an inversion area (region where 118a contacts 116, see fig. 2U) that is a contact interface with the charge storage layer (114, 116) while the first channel layer (118a) is formed in contact with the charge storage layer (114, 116) and
a second channel layer (118b) formed on an inner wall of the first channel layer (118a); and wherein
the second channel layer (118b) is used as a protection layer ([0046], 118b is positioned in front of 118a during the deposition of 120) and an electron transfer assist layer ([0040], 118a has a higher electron mobility and may be considered to be the electron transfer layer, therefore 118b may be considered to be an electron transfer assist layer for 118a) for the first channel layer (118a).
Regarding Claim 2, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 1, wherein the first channel layer (118a) is formed of a material having a higher electron mobility ([0040], Si-Ge has higher electron mobility) than that of the second channel layer ([0043], 118b may be Poly-Si) or a higher electron mobility than a threshold value to improve the electron mobility in the inversion area that is a contact interface with the charge storage layer.
Regarding Claim 3, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 2, wherein the first channel layer (118a) is formed of any one of a polycrystalline group 3-5 compound (poly 3-5) or polycrystalline silicon germanium (poly Si-Ge) ([0039], may be silicon germanium and may be polycrystalline).
Regarding Claim 5, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 1, wherein the second channel layer (118b) is an electron transport assist layer formed of a material characterized by greater durability ([0045], 118b may be more resistant to the formation of Ge oxide) and protection in thermal processes (118b is more resistant to the formation of Ge oxide at the temperatures used in the process) than the first channel layer (118a).
Regarding Claim 6, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 5, wherein the second channel layer (118b) is formed of polycrystalline silicon (Poly Si) ([0043], 118b may be Poly-Si).
Regarding Claim 7, Zhang (figs. 2D-2U) teaches a method of manufacturing a three-dimensional flash memory ([0013]), the method comprising:
preparing a semiconductor structure ([0023], memory device) including a plurality of word lines ([0047], 122, see fig. 2U) extending on a substrate ([0024], 102, see fig. 2U) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U) and
at least one hole ([0027], 108, see fig. 2D) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2D);
forming a charge storage layer ([0038], 114, 116, see fig. 2L) including an inner hole (remainder of 108 after the formation of 114, 116, see fig. 2L) in the at least one hole (108) of the semiconductor structure; and
extending a channel layer ([0043], 118a, 118b, see fig. 2Q) having a double structure in the vertical direction (up and down) inside the inner hole (remainder of 108), wherein the extending of the channel layer (118a, 118b) includes:
forming a first channel layer (118a) for improving an electron mobility ([0040], 118a has higher electron mobility) in an inversion area (region where 118a contacts 116, see fig. 2U) that is a contact interface with the charge storage layer (114, 116) such that the first channel layer (118a) is in contact with the charge storage layer (114, 116); and
forming a second channel layer (118b) in an inner wall of the first channel layer (118a), wherein
the second channel layer (118b) is used as a protection layer ([0046], 118b is positioned in front of 118a during the deposition of 120) and an electron transfer assist layer ([0040], 118a has a higher electron mobility and may be considered to be the electron transfer layer, therefore 118b may be considered to be an electron transfer assist layer for 118a) for the first channel layer (118a).
Regarding Claim 8, Zhang (figs. 2D-2U) teaches a method of manufacturing a three-dimensional flash memory ([0013]), the method comprising:
preparing a semiconductor structure ([0023], memory device) including a plurality of sacrificial layers ([0024], 106, see fig. 2D) extending on a substrate ([0024], 102, see fig. 2U) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked and
at least one hole ([0027], 108, see fig. 2D) passing through the plurality of sacrificial layers (106) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2D);
forming a charge storage layer ([0038], 114, 116, see fig. 2L) including an inner hole (remainder of 108 after the formation of 114, 116, see fig. 2L) in the at least one hole (108) of the semiconductor structure; and
extending a channel layer ([0043], 118a, 118b, see fig. 2Q) having a double structure in the vertical direction (up and down) inside the inner hole (remainder of 108);
removing ([0047], see fig. 2U) the plurality of sacrificial layers (106); and
forming a plurality of word lines ([0047], 122, see fig. 2U) in spaces from which the plurality of sacrificial layers (106) are removed, wherein the extending of the channel layer (118a, 118b) includes:
forming a first channel layer (118a) for improving an electron mobility ([0040], 118a has higher electron mobility) in an inversion area (region where 118a contacts 116, see fig. 2U) that is a contact interface with the charge storage layer (114, 116) such that the first channel layer (118a) is in contact with the charge storage layer (114, 116); and
forming a second channel layer (118b) in an inner wall of the first channel layer (118a), wherein
the second channel layer (118b) is used as a protection layer ([0046], 118b is positioned in front of 118a during the deposition of 120) and an electron transfer assist layer ([0040], 118a has a higher electron mobility and may be considered to be the electron transfer layer, therefore 118b may be considered to be an electron transfer assist layer for 118a) for the first channel layer (118a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Saxler (2020/0075617 A1; hereinafter Saxler)
Regarding Claim 9, Zhang (fig. 2U) a three-dimensional flash memory ([0013]) comprising:
a plurality of word lines ([0047], 122) extending on a substrate ([0024], 102) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U); and
at least one string ([0027], 100) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2U), the at least one string (100) including
a channel layer ([0043], 118a, 118b) extending in the vertical direction (up and down) and
a charge storage layer ([0038], 114, 116) formed to surround the channel layer (118a, 118b), wherein
while the channel layer (118a, 118b) has a double structure including an outer first channel layer (118a) and
a second channel layer (118b) formed on an inner wall of the first channel layer (118a),
a heterojunction ([0044], 118c, see fig. 2V) is formed as a junction between the first channel layer (118a) and the second channel layer (118b), wherein
the first channel layer (118a) is formed of a first metal oxide ([0039], 118a may be a conductive oxide) and the second channel layer (118b) is formed of a second metal oxide ([0043], 118b may be formed from similar materials to 118a); and wherein
the first metal oxide and second metal oxide are different metal oxides so that the heterojunction is formed as the junction between the first channel layer and second channel layer.
Zhang doesn’t teach the first metal oxide and second metal oxide are different metal oxides so that the heterojunction is formed as the junction between the first channel layer and second channel layer.
However, Saxler (fig. 2A) teaches the first metal oxide ([0021], 116) and second metal oxide ([0022], 118) are different metal oxides ([0032], channel 116 may be gallium indium oxide, [0030], barrier 118 may be aluminum gallium oxide) so that the heterojunction is formed as the junction ([0021]) between the first channel layer (116) and second channel layer (118). One of ordinary skill in the art would have found it obvious to try and used metal oxides for channel layers and yielded the predictable results of forming a heterojunction between the channel layers
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to metal oxides for channel layers since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 11, Saxler (fig. 2A) teaches the three-dimensional flash memory of claim 9, wherein the first metal oxide (116) and the second metal oxide (118) include at least one of In, Zn, or Ga ([0030], [0032], both 116 and 118 contain Ga) or a metal oxide including a group 4 semiconductor material.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Saxler as applied to Claim 9 above, and further in view of Rabkin et al. (2016/0358933 A1; hereinafter Rabkin).
Regarding Claim 13, Zhang doesn’t teach the three-dimensional flash memory of claim 9, wherein the three-dimensional flash memory implements a quantum well through the heterojunction to improve an electron mobility in the junction between the first channel layer and the second channel layer.
However, Rabkin (figs. 2K and 13) teaches a quantum well ([0130], 540 formed near 520, see fig, 13) through the heterojunction ([0088], 520, see fig. 2K) to improve an electron mobility in the junction between the first channel layer ([0088], 512, see fig. 2K) and the second channel layer ([0088], 514, see fig. 2K). Rabkin also teaches the quantum well increases on-current and increases the signal-to-noise ratio during the read operation ([0135]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the flash memory of Zhang to include the quantum well of Rabkin to increase on-current.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rabkin and Saxler.
Regarding Claim 14, Zhang (figs. 2D-2U) teaches a method of manufacturing a three-dimensional flash memory ([0013]), the method comprising:
preparing a semiconductor structure ([0023], memory device) including a plurality of word lines ([0047], 122, see fig. 2U) extending on a substrate ([0024], 102, see fig. 2U) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U) and
at least one string ([0027], 100, see fig. 2U) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2D), the at least one string (100) including
a channel layer ([0043], 118a, 118b, see fig. 2Q) extending in the vertical direction (up and down) and
a charge storage layer ([0038], 114, 116, see fig. 2L) formed to surround the channel layer (118a, 118b);
forming an N+ doped part at an upper end of the at least one string; and
generating at least one wiring line ([0049], bit-line, see fig. 2Q) in contact with the N+ doped part, wherein the preparing of the semiconductor structure includes:
implementing the channel layer (118a, 118b, see fig. 2Q) having a double structure including an outer first channel (118a) and a second channel layer (118b) formed on an inner wall of the first channel layer (118a) so that
a heterojunction ([0044], 118c) is formed as a junction between the first channel layer (118a) and the second channel layer (118b), wherein
the first channel layer (118a) is formed of a first metal oxide ([0039], 118a may be a conductive oxide) and the second channel layer (118b) is formed of a second metal oxide ([0043], 118b may be formed from similar materials to 118a); and wherein
the first metal oxide and second metal oxide are different metal oxides so that the heterojunction is formed as the junction between the first channel layer and second channel layer.
Zhang teaches a bit-line channel plug ([0049], not shown) at the top of the channel layer (118). Zhang doesn’t teach forming an N+ doped part at an upper end of the at least one string; and generating at least one wiring line in contact with the N+ doped part.
However, Rabkin (fig. 8A) teaches forming an N+ doped part ([0086], 63 may be doped n type) at an upper end (see fig. 8A) of the at least one string ([0103], 55); and generating at least one wiring line ([0094], 88) in contact with the N+ doped part (63). Rabkin also teaches the doped part provides electrical contact from the string to memory contact structures leading externally ([0113]). One of ordinary skill in the art would have found it obvious to try and use an N+ doped part and yielded the predictable results of electrically connecting the string to external features.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use an N+ doped layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Zhang doesn’t teach the first metal oxide and second metal oxide are different metal oxides so that the heterojunction is formed as the junction between the first channel layer and second channel layer.
However, Saxler (fig. 2A) teaches the first metal oxide ([0021], 116) and second metal oxide ([0022], 118) are different metal oxides ([0032], channel 116 may be gallium indium oxide, [0030], barrier 118 may be aluminum gallium oxide) so that the heterojunction is formed as the junction ([0021]) between the first channel layer (116) and second channel layer (118). One of ordinary skill in the art would have found it obvious to try and used metal oxides for channel layers and yielded the predictable results of forming a heterojunction between the channel layers
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to metal oxides for channel layers since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to Claim 1 above, and further in view of Choi et al. (2020/0144284 A1; hereinafter Choi).
Regarding Claim 15, Zhang doesn’t teach the three-dimensional flash memory of claim 1, wherein the channel layer extends from a top of the plurality of word lines to the substrate.
However, Choi (fig. 17) teaches the channel layer ([0018], 153) extends from a top of the plurality of word lines ([0021], 180) to the substrate ([0018], 100). One of ordinary skill in the art would have found it obvious to try and extend the vertical channel to the substrate and yielded the predictable result of a functional vertical memory device.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to extend the channel to the substrate this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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