Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 10th, 2023, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 recites the limitation "more excellent durability and thermal performance" in lines 2-3. It is unclear what attributes of the material are to be considered when comparing materials for durability and thermal performance. It is also unclear as to what standard or numeric value the limitation “excellent durability and thermal performance” requires. For the purpose of examination, the limitation “more excellent durability and thermal performance” will be interpreted as providing an advantage or acting as a physical barrier in thermal processes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (2017/0263623 A1; hereinafter Zhang).
Regarding Claim 1, Zhang (fig. 2U) teaches a three-dimensional flash memory ([0013]) comprising:
a plurality of word lines ([0047], 122) extending on a substrate ([0024], 102) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U); and
at least one cell string ([0027], 100) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2U), the at least one cell string (100) including
a channel layer ([0043], 118a, 118b) extending in the vertical direction (up and down) and
a charge storage layer ([0038], 114, 116) formed to surround the channel layer (118a, 118b), wherein
the channel layer (118a, 118b) has a double structure including a first channel layer (118a) for improving an electron mobility ([0040], 118a has higher electron mobility) in an inversion area (region where 118a contacts 116, see fig. 2U) that is a contact interface with the charge storage layer (114, 116) while the first channel layer (118a) is formed in contact with the charge storage layer (114, 116) and
a second channel layer (118b) formed on an inner wall of the first channel layer (118a).
Regarding Claim 2, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 1, wherein the first channel layer (118a) is formed of a material having a higher electron mobility ([0040], Si-Ge has higher electron mobility) than that of the second channel layer ([0043], 118b may be Poly-Si) or a higher electron mobility than a threshold value to improve the electron mobility in the inversion area that is a contact interface with the charge storage layer.
Regarding Claim 3, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 2, wherein the first channel layer (118a) is formed of any one of a polycrystalline group 3-5 compound (poly 3-5) or polycrystalline silicon germanium (poly Si-Ge) ([0039], may be silicon germanium and may be polycrystalline).
Regarding Claim 4, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 1, wherein the second channel layer (118b) is used as a protection layer ([0046], 118b is positioned in front of 118a during the deposition of 120) or an electron transfer assist layer for the first channel layer.
Regarding Claim 5, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 4, wherein the second channel layer (118b) is formed of a material having more excellent durability ([0045], 118b may be more resistant to the formation of Ge oxide) and thermal performance (118b is more resistant to the formation of Ge oxide at the temperatures used in the process) than those of the first channel layer (118a).
Regarding Claim 6, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 5, wherein the second channel layer (118b) is formed of polycrystalline silicon (Poly Si) ([0043], 118b may be Poly-Si).
Regarding Claim 7, Zhang (figs. 2D-2U) teaches a method of manufacturing a three-dimensional flash memory ([0013]), the method comprising:
preparing a semiconductor structure ([0023], memory device) including a plurality of word lines ([0047], 122, see fig. 2U) extending on a substrate ([0024], 102, see fig. 2U) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U) and
at least one hole ([0027], 108, see fig. 2D) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2D);
forming a charge storage layer ([0038], 114, 116, see fig. 2L) including an inner hole (remainder of 108 after the formation of 114, 116, see fig. 2L) in the at least one hole (108) of the semiconductor structure; and
extending a channel layer ([0043], 118a, 118b, see fig. 2Q) having a double structure in the vertical direction (up and down) inside the inner hole (remainder of 108), wherein the extending of the channel layer (118a, 118b) includes:
forming a first channel layer (118a) for improving an electron mobility ([0040], 118a has higher electron mobility) in an inversion area (region where 118a contacts 116, see fig. 2U) that is a contact interface with the charge storage layer (114, 116) such that the first channel layer (118a) is in contact with the charge storage layer (114, 116); and
forming a second channel layer (118b) in an inner wall of the first channel layer (118a).
Regarding Claim 8, Zhang (figs. 2D-2U) teaches a method of manufacturing a three-dimensional flash memory ([0013]), the method comprising:
preparing a semiconductor structure ([0023], memory device) including a plurality of sacrificial layers ([0024], 106, see fig. 2D) extending on a substrate ([0024], 102, see fig. 2U) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked and
at least one hole ([0027], 108, see fig. 2D) passing through the plurality of sacrificial layers (106) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2D);
forming a charge storage layer ([0038], 114, 116, see fig. 2L) including an inner hole (remainder of 108 after the formation of 114, 116, see fig. 2L) in the at least one hole (108) of the semiconductor structure; and
extending a channel layer ([0043], 118a, 118b, see fig. 2Q) having a double structure in the vertical direction (up and down) inside the inner hole (remainder of 108);
removing ([0047], see fig. 2U) the plurality of sacrificial layers (106); and
forming a plurality of word lines ([0047], 122, see fig. 2U) in spaces from which the plurality of sacrificial layers (106) are removed, wherein the extending of the channel layer (118a, 118b) includes:
forming a first channel layer (118a) for improving an electron mobility ([0040], 118a has higher electron mobility) in an inversion area (region where 118a contacts 116, see fig. 2U) that is a contact interface with the charge storage layer (114, 116) such that the first channel layer (118a) is in contact with the charge storage layer (114, 116); and
forming a second channel layer (118b) in an inner wall of the first channel layer (118a).
Regarding Claim 9, Zhang (fig. 2U) a three-dimensional flash memory ([0013]) comprising:
a plurality of word lines ([0047], 122) extending on a substrate ([0024], 102) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U); and
at least one string ([0027], 100) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2U), the at least one string (100) including
a channel layer ([0043], 118a, 118b) extending in the vertical direction (up and down) and
a charge storage layer ([0038], 114, 116) formed to surround the channel layer (118a, 118b), wherein
while the channel layer (118a, 118b) has a double structure including an outer first channel layer (118a) and
a second channel layer (118b) formed on an inner wall of the first channel layer (118a),
a heterojunction ([0044], 118c, see fig. 2V) is formed as a junction between the first channel layer (118a) and the second channel layer (118b).
Regarding Claim 10, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 9, wherein the first channel layer (118a) and the second channel layer (118b) are formed of a metal oxide ([0039], 118a may be a conductive oxide, [0043], 118b may be formed from similar materials to 118a) so that the heterojunction ([0044], 118c may be from a difference in band structure resulting from different materials) is formed as the junction between the first channel layer (118a) and the second channel layer (118b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to Claim 10 above, and further in view of Huang et al. (2019/0067326 A1; hereinafter Huang).
Regarding Claim 11, Zhang (fig. 2U) teaches the three-dimensional flash memory of claim 10, wherein the first channel layer (118a) and the second channel layer (118b) are formed of a metal oxide ([0039], [0043]). Zhang doesn’t teach a metal oxide including at least one of In, Zn, or Ga or a metal oxide including a group 4 semiconductor material.
However, Huang (fig. 14) teaches a metal oxide including at least one of In, Zn, or Ga or a metal oxide including a group 4 semiconductor material ([0017], channel may be zinc oxide or indium gallium zinc oxide). Huang also teaches that such channel materials may allow for an increase in string current ([0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the flash memory of Zhang to include the zinc oxide of Huang to increase string current.
Regarding Claim 12, the combination Zhang (fig. 2U) and Huang (fig. 14) teaches the three-dimensional flash memory of claim 10, wherein the first channel layer (Zhang, 118a) and the second channel layer (Zhang, 118b) are formed of different materials (Zhang, [0044], to maintain the band structure difference of 118c) among the metal oxides (Huang, one may be formed of zinc oxide and the other indium gallium oxide).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to Claim 9 above, and further in view of Rabkin et al. (2016/0358933 A1; hereinafter Rabkin).
Regarding Claim 13, Zhang doesn’t teach the three-dimensional flash memory of claim 9, wherein the three-dimensional flash memory implements a quantum well through the heterojunction to improve an electron mobility in the junction between the first channel layer and the second channel layer.
However, Rabkin (figs. 2K and 13) teaches a quantum well ([0130], 540 formed near 520, see fig, 13) through the heterojunction ([0088], 520, see fig. 2K) to improve an electron mobility in the junction between the first channel layer ([0088], 512, see fig. 2K) and the second channel layer ([0088], 514, see fig. 2K). Rabkin also teaches the quantum well increases on-current and increases the signal-to-noise ratio during the read operation ([0135]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the flash memory of Zhang to include the quantum well of Rabkin to increase on-current.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Rabkin.
Regarding Claim 14, Zhang (figs. 2D-2U) teaches a method of manufacturing a three-dimensional flash memory ([0013]), the method comprising:
preparing a semiconductor structure ([0023], memory device) including a plurality of word lines ([0047], 122, see fig. 2U) extending on a substrate ([0024], 102, see fig. 2U) in a horizontal direction (in and out of the page, see fig. 2U) and sequentially stacked (see fig. 2U) and
at least one string ([0027], 100, see fig. 2U) passing through the plurality of word lines (122) and extending on the substrate (102) in a vertical direction (up and down, see fig. 2D), the at least one string (100) including
a channel layer ([0043], 118a, 118b, see fig. 2Q) extending in the vertical direction (up and down) and
a charge storage layer ([0038], 114, 116, see fig. 2L) formed to surround the channel layer (118a, 118b); []
generating at least one wiring line ([0049], bit-line, see fig. 2Q) [] wherein the preparing of the semiconductor structure includes:
implementing the channel layer (118a, 118b, see fig. 2Q) having a double structure including an outer first channel (118a) and a second channel layer (118b) formed on an inner wall of the first channel layer (118a) so that
a heterojunction ([0044], 118c) is formed as a junction between the first channel layer (118a) and the second channel layer (118b).
Zhang teaches a bit-line channel plug ([0049], not shown) at the top of the channel layer (118). Zhang doesn’t teach forming an N+ doped part at an upper end of the at least one string; and generating at least one wiring line in contact with the N+ doped part.
However, Rabkin (fig. 8A) teaches forming an N+ doped part ([0086], 63 may be doped n type) at an upper end (see fig. 8A) of the at least one string ([0103], 55); and generating at least one wiring line ([0094], 88) in contact with the N+ doped part (63). Rabkin also teaches the doped part provides electrical contact from the string to memory contact structures leading externally ([0113]). One of ordinary skill in the art would have found it obvious to try and use an N+ doped part and yielded the predictable results of electrically connecting the string to external features.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use an N+ doped layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 19, 2026