Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1,4,9,11,14-15,19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20180138037 A1 (Yan) in view of US 20210057549 A1 (Mo).
Regarding claim 1, Yan shows (Fig. 1) a thin film transistor, comprising:
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a gate (11, para 44) and an active layer (13, para 44) which are located on one side of a base substrate (10);
a gate insulating layer (12, para 44) located between the gate and the active layer; and
a source (14, para 48) and a drain (15, para 48) spaced apart from each other, and both in contact with the active layer,
wherein a first ratio of a thickness of the gate insulating layer (para 47) to a thickness of the active layer (para 49) ranges from 3 to 4 (considering the thickness of gate insulating thickness of 350nm and active layer thickness of 100nm).
Yan does not show wherein the active layer comprises:
a first semiconductor layer which is heavily doped and comprises a first portion and a second portion spaced apart from each other, wherein the first portion is in contact with the source and the second portion is in contact with the drain; and
a second semiconductor layer located between the first semiconductor layer and the gate insulating layer, and in contact with the gate insulating layer.
Mo shows (Fig. 5-8) wherein the active layer comprises:
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a first semiconductor layer (50, para 95) which is heavily doped (Optionally, the doped layer 50 is N-doped in the amorphous silicon layer and is heavily N-doped, para 95) and comprises a first portion (left portion of 50) and a second portion (right portion of 50) spaced apart from each other, wherein the first portion is in contact with the source (610, para 83) and the second portion is in contact with the drain (620, para 83); and
a second semiconductor layer (40, para 94) located between the first semiconductor layer and the gate insulating layer (30, para 94), and in contact with the gate insulating layer.
Mo shows thickness of the gate insulating layer 3700 Å to 4000 Å (Mo, para 76) and a thickness of the first semiconductor layer is 400 Å (Mo, 50, para 95).
However, the thickness of the first semiconductor layer (doped layer 50) may be selected and adjusted according to an actual application situation and product performance and is not further limited herein (Mo, para 95).
Thus, it would have been obvious to have a second ratio of the thickness of the gate insulating layer to a thickness of the first semiconductor layer ranges from 15 to 24 by reducing the thickness of the first semiconductor layer, since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B.
Regarding claim 4, Yan as previously modified by Mo shows thickness of the gate insulating layer 3700 Å to 4000 Å (Mo, para 76) and a thickness of the first semiconductor layer is 400 Å (Mo, 50, para 95).
However, the thickness of the first semiconductor layer (doped layer 50) may be selected and adjusted according to an actual application situation and product performance and is not further limited herein (Mo, para 95).
Thus, it would have been obvious to have a second ratio of the thickness of the gate insulating layer to a thickness of the first semiconductor layer ranges from 18 to 22 by reducing the thickness of the first semiconductor layer, since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B.
Regarding claim 9, Yan as previously modified by Mo shows an insulating protective layer (Mo, Fig. 8, 80, para 98) covering the source (Mo, 610) and the drain (Mo, 620), the insulating protective layer comprising:
a first surface (portion of 80 in contact with the rightmost side of 610) in contact with a first side edge of the source close to the drain;
a second surface (portion of 80 in contact with the leftmost side of 620) in contact with a second side edge of the drain close to the source; and
a third surface (portion of 80 in contact with horizontal portion of 40 between 610 and 6200) in contact with a surface of the second semiconductor layer away from the gate insulating layer and adjacent to the first surface and the second surface, wherein a comprised angle between the third surface and the first surface is a first comprised angle, an a comprised angle between the third surface and the second surface is a second comprised angle, and at least one of the first comprised angle or the second comprised angle is greater than 90 degrees and less than or equal to 110 degrees (portion of 80 contacting the rightmost surface of 610 comprises an angle of 100 degree with the flat portion of 80 on 40).
Regarding claim 11, Yan as previously modified by Mo shows wherein a material of each of the first semiconductor layer (Mo, 40, para 94) and the second semiconductor layer (Mo, 50, para 95) comprises amorphous silicon.
Regarding claim 14, Yan shows (Fig. 1) wherein the first ratio ranges from 3.4 to 3.8 (using values from para 47,49).
Regarding claim 15, Yan shows (Fig. 1) wherein the gate (11) is located between the base substrate (10) and the gate insulating layer (12).
Regarding claim 19, the previously rejected claim 1, teaches the whole limitation.
2. Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Mo as applied to claim 1, further in view of US 20190006525 A1 (Uraoka).
Regarding claim 5, Yan as previously modified by Mo shows the first portion (Mo, left portion of 50) of the first semiconductor layer (Mo, 50) is in contact with a third portion of the second semiconductor layer (left portion of 40 under left 50), and the second portion of the first semiconductor layer (Mo, 50 right portion) is in contact with a fourth portion of the second semiconductor layer (right portion of 40 under right 50), wherein a portion of the second semiconductor layer between the third portion and the fourth portion is a channel (Mo, 70, para 85)
Yan as previously modified by Mo does not specifically show a width-length ratio of the channel ranging from 0.52 to 0.6.
Uraoka shows a width-length ratio of the channel ranging from 0.52 to 0.6 (para 28).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Uraoka, with width-length ratio of the channel, to the invention of Yan as previously modified by Mo.
The motivation to do so is that the selection of an art recognized width-length ratio of the channel of Uraoka is suitable for the intended use of Yan as previously modified by Mo (MPEP §2144.07).
Regarding claim 6, Yan as previously modified by Mo shows the first portion (Mo, left portion of 50) of the first semiconductor layer (Mo, 50) is in contact with a third portion of the second semiconductor layer (left portion of 40 under left 50), and the second portion of the first semiconductor layer (Mo, 50 right portion) is in contact with a fourth portion of the second semiconductor layer (right portion of 40 under right 50), wherein a portion of the second semiconductor layer between the third portion and the fourth portion is a channel (Mo, 70, para 85)
Yan as previously modified by Mo does not specifically show a width-length ratio of the channel ranging from 0.54 to 0.58.
Uraoka shows a width-length ratio of the channel ranging from 0.54 to 0.58 (para 28).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Uraoka, with width-length ratio of the channel, to the invention of Yan as previously modified by Mo.
The motivation to do so is that the selection of an art recognized width-length ratio of the channel of Uraoka is suitable for the intended use of Yan as previously modified by Mo (MPEP §2144.07).
3. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Mo as applied to claim 1, further in view of CN 106298957 A (Bai).
Regarding claim 7, Yan as previously modified by Mo shows the source, the second semiconductor layer, the drain. Mo shows thickness of each of the source and the drain is a first thickness (610,620 3500A to 4000A, para 93) and thickness of second semiconductor layer (40, 700A, para 94)
Yan as previously modified by Mo does not show wherein the source is in contact with a fifth portion of the second semiconductor layer, the drain is in contact with a sixth portion of the second semiconductor layer, a thickness of each of the fifth portion and the sixth portion is a second thickness, wherein a third ratio of the first thickness to the second thickness ranges from 5.2 to 7.
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Bai shows (Fig. 1) wherein the source (201) is in contact with a fifth portion (S2 part or 40 left of 301) of the second semiconductor layer (301), the drain (202) is in contact with a sixth portion (40 right of 301) of the second semiconductor layer.
Bai in combination with Yan as previously modified by Mo shows a thickness of each of the source and the drain is a first thickness shows 4000A), and a thickness of each of the fifth portion and the sixth portion is a second thickness (700A, since extended second semiconductor thick of Mo will be the same), wherein a third ratio of the first thickness to the second thickness ranges from 5.2 to 7 (4000/700 = 5.71).
Regarding claim 8, Yan as previously modified by Mo and Bai shows wherein the third ratio ranges from 5.8 to 6.5 (4000/650=6.15).
3. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Mo as applied to claim 1, further in view of US 20130026574 A1 (Nakanishi).
Regarding claim 10, Yan as previously modified by Mo shows wherein a conductivity type of the first semiconductor layer is n type (Mo, 50, para 95, n-doped), and the second semiconductor layer (Mo, 40).
Yan as previously modified by Mo does not show the second semiconductor layer is an intrinsic semiconductor layer.
Nakanishi shows (Fig. 1) the second semiconductor layer (141, para 64) is an intrinsic semiconductor layer.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Nakanishi, with intrinsic channel, to the invention of Yan as previously modified by Mo.
The motivation to do so is that the selection of an art recognized channel of Nakanishi is suitable for the intended use of Yan as previously modified by Mo (MPEP §2144.07).
4. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Mo as applied to claim 11, further in view of US 20170084642 A1 (Lin).
Regarding claim 12, Yan as previously modified by Mo shows wherein the material of the second semiconductor layer comprises amorphous silicon.
Yan as previously modified by Mo does not show the material of the second semiconductor layer comprises hydrogenated amorphous silicon.
Lin shows the material of a semiconductor layer comprises hydrogenated amorphous silicon (para 16).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Yan as previously modified by Mo, including material of the second semiconductor layer, with the invention of Lin.
The motivation to do so is that the combination produces high charge carrier mobility and high thin film uniformity (para 16).
5. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan as applied to claim 1, in view of US 20090200553 A1 (Yang).
Regarding claim 13, Yan shows the gate insulating layer and the active layer.
Yan does not show the thickness of the gate insulating layer ranges from 4500 angstroms to 5000 angstroms; and the thickness of the active layer ranges from 1000 angstroms to 1500 angstroms.
Yang shows (Fig. 3) the thickness of the gate insulating layer (310, para 35) ranges from 4500 angstroms to 5000 angstroms (1000 Angstroms to 4500 Angstroms); and
the thickness of the active layer ranges from 1000 angstroms to 1500 angstroms (500 to 3000 Angstroms), which overlaps the claimed range.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
The motivation to do so is that the selection of an art recognized gate insulating layer and the active layer thicknesses of Yang are suitable for the intended use of Yan (MPEP §2144.07).
6. Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan as applied to claim 1, in view of US 20180308871 A1 (Wu).
Regarding claim 16, Yan shows at least one of the plurality of thin film transistors comprising the thin film transistor.
Yan does not show a plurality of pixel driving circuits, wherein each of the pixel driving circuits comprises a plurality of thin film transistors.
Wu shows (Fig. 18) a plurality of pixel driving circuits, wherein each of the pixel driving circuits comprises a plurality of thin film transistors (para 161).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Wu, with pixel driving circuits, to the invention of Yan.
The motivation to do so is that the selection of an art recognized pixel driving circuits of Wu is suitable for a display panel (para 161).
Regarding claim 17, Yan as previously modified with Wu shows display panel (Wu, para 161).
Regarding claim 18, Yan as previously modified with Wu shows display device (Wu, para 167).
Response to Arguments
Applicant's arguments filed 3/11/2026 have been fully considered but they are not persuasive. Regarding the argument “Although Mo mentions that the thickness of the first semiconductor layer (doped layer 50) may be selected and adjusted according to an actual application situation and product performance, Mo fails to teach or suggest the on-state current of the thin film transistor can be further increased by adjusting the ratio of the thickness of the gate insulation layer 30 to the thickness of the doped layer 50, and further fails to disclose what kind of range of this ratio can effectively increase the on-state current of the thin film transistor” as presented by the applicant, the examiner states that Mo reference explicitly stated that “It may be understood that the thickness of the doped layer 50 may be selected and adjusted according to an actual application situation and product performance and is not further limited herein” (para 95). Gate insulator thickness, semiconductor layer thickness are adjustable to optimize the current or other parameters. As such, routine optimization according to MPEP 2144.05 II.B can easily satisfy the stated condition by further decreasing the semiconductor layer thickness. As such, the rejection is deemed proper and a final is hereby submitted.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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