DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, 11, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Shinohara; Masato (JP 2020/057689; hereinafter Shinohara) in view of Kanbe; Hideo (JP 2005/167588; hereinafter Kanbe).
Regarding claim 1, Shinohara discloses a photodetector comprising:
a semiconductor layer (110; Fig 4; ¶ [0025]) that has a first surface (upper surface; Fig 4) and a second surface (lower surface; Fig 4) located opposite to each other and is provided with an element isolation region (116; Fig 4; ¶ [0025]) on a side of the first surface;
a photoelectric converter (PD; Figs 3-4; ¶ [0026-27]) provided in the semiconductor layer; and
a transistor (M3; Figs 3-4; ¶ [0035]) provided adjacent to the photoelectric converter on the side of the first surface of the semiconductor layer across the element isolation region,
wherein
the element isolation region includes a dielectric film provided in a groove (shallow trench isolation; Fig 4; ¶ [0025]) on the side of the first surface of the semiconductor layer.
Shinohara does not disclose the element isolation region includes a conductive film provided in the groove with a first insulating film interposed therebetween, and a second insulating film provided on the side of the first surface of the semiconductor layer so as to overlap the conductive film.
In the same field of endeavor Kanbe discloses an element isolation region including a conductive film (22; Fig 1; ¶ [0034-35]) provided in a groove (trench; Fig 1; ¶ [0032]) with a first insulating film (20; Fig 1; ¶ [0032]) interposed therebetween, and a second insulating film (gate insulating film 17; Fig 1; ¶ [0033]) provided on the side of the first surface of the semiconductor layer so as to overlap the conductive film. Kanbe discloses problems associated with a shallow trench isolation structure in a photodetector, including dark current and white spots, and presents the disclosure as a solution (Kanbe; ¶ [0002-29]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the element isolation region of Kanbe with the photodetector of Shinohara. One would have been motivated to do this in order to reduce generation of dark current in the device (Kanbe; ¶ [0024,0028]) while maintaining an increased readout speed (Shinohara; ¶ [0005]). One would have had a reasonable expectation of success because of the similar trench structure of the element isolation regions of Kanbe and Shinohara in the similar photodetectors.
Regarding claim 2, Shinohara in view of Kanbe discloses the photodetector according to claim 1, wherein the second insulating film (Kanbe; 17; Fig 1) covers the conductive film (Kanbe; 22; Fig 1).
Regarding claim 3, Shinohara in view of Kanbe discloses the photodetector according to claim 1, wherein the conductive film (Kanbe; 22; Fig 1) is electrically connected to a wire to which a potential is applied (Kanbe; ¶ [0036-38]).
Regarding claim 4, Shinohara in view of Kanbe discloses the photodetector according to claim 1, wherein the photoelectric converter (Shinohara; PD; Figs 3-4) includes a first semiconductor region of a first conductivity type (Shinohara; n-type region 120; Fig 4; ¶ [0027]; corresponding to Kanbe; 13; Fig 1; ¶ [0031]), and a second semiconductor region of a second conductivity type (Shinohara; p-type region 118,152; Fig 4; ¶ [0027,0035]; corresponding to Kanbe; 14,21; Fig 1; ¶ [0031,0034]) is provided in the semiconductor layer between the element isolation region (Shinohara; 116), and the first semiconductor region.
Regarding claim 7, Shinohara in view of Kanbe discloses the photodetector according to claim 4,
wherein a reference potential is applied to the second semiconductor region (Kanbe; ϕV2 applied to 14; ¶ [0041]), and
a negative potential lower than the reference potential is applied to the conductive film (Kanbe; ϕV1 applied to 22; ¶ [0037-38)].
Regarding claim 8, Shinohara in view of Kanbe discloses the photodetector according to claim 1,
wherein the semiconductor layer (Shinohara; 110; Fig 4) includes an element formation region (Shinohara; 114; Fig 4; ¶ [0025]) defined by the element isolation region (Shinohara; 116; Fig 4; ¶ [0025]) on the side of the first surface,
the transistor (Shinohara; M3; Figs 3-4) includes a gate electrode (Shinohara; 138; Fig 4; ¶ [0031]) provided over the element formation region and the element isolation region, and
the second insulating film (Kanbe; 17; Fig 1) is interposed between the conductive film (Kanbe; 22; Fig 1) and the gate electrode (as applied to claim 1; Shinohara, as ).
Regarding claim 11, Shinohara in view of Kanbe discloses the photodetector according to claim 1, wherein the transistor (Shinohara; M3; Figs 3-4) includes a gate electrode (Shinohara; 138; Fig 4; ¶ [0031]) provided over the element formation region (Shinohara; 114; Fig 4) and the element isolation region (Shinohara; 116; Fig 4), and
the transistor is disposed in an orientation in which a channel formation region (Shinohara; 150; Fig 4; ¶ [0035]) immediately below the gate electrode is adjacent to the photoelectric converter (Shinohara; PD; Fig 4) immediately across the element isolation region.
Regarding claim 14, Shinohara in view of Kanbe discloses the photodetector according to claim 1, further comprising a read circuit (Shinohara; comprising M2,M3,M4; ¶ [0023]) that reads a signal charge photoelectrically converted by the photoelectric converter, wherein
at least one of a plurality of pixel transistors (Shinohara; M3/FD; Fig 2) included in the read circuit is the transistor.
Regarding claim 15, Shinohara in view of Kanbe discloses the photodetector according to claim 1, further comprising a microlens (Kanbe; on-chip lens; ¶ [0011]) provided on a side of the second surface of the semiconductor layer (the lower surface is the light receiving surface {Kanbe; ¶ [0010]} where the microlens would be disposed).
Regarding claim 16, Shinohara in view of Kanbe discloses the photodetector according to claim 1, wherein the transistor includes a field effect transistor (as applied to claim 1; as depicted by the symbol for M3 in Fig 2 of Shinohara).
Regarding claim 17, Shinohara discloses an electronic apparatus (200; Fig 9; ¶ [0064-65]) comprising:
a photodetector (201; Fig 9; ¶ [0064]);
an optical lens (202; Fig 9; ¶ [0064]) that forms an image of image light from a subject on an imaging surface of the photodetector; and
a signal processing circuit (208; Fig 9; ¶ [0065]);that performs signal processing on a signal output from the photodetector, wherein
the photodetector includes a semiconductor layer (110; Fig 4; ¶ [0025]) that has a first surface (upper surface; Fig 4) and a second surface (lower surface; Fig 4) located opposite to each other and is provided with an element isolation region (116; Fig 4; ¶ [0025]) on a side of the first surface;
a photoelectric converter (PD; Figs 3-4; ¶ [0026-27]) provided in the semiconductor layer; and
a transistor (M3; Figs 3-4; ¶ [0035]) provided adjacent to the photoelectric converter on the side of the first surface of the semiconductor layer across the element isolation region,
wherein
the element isolation region includes a dielectric film provided in a groove (shallow trench isolation; Fig 4; ¶ [0025]) on the side of the first surface of the semiconductor layer.
Shinohara does not disclose the element isolation region includes a conductive film provided in the groove with a first insulating film interposed therebetween, and a second insulating film provided on the side of the first surface of the semiconductor layer so as to overlap the conductive film.
In the same field of endeavor Kanbe discloses an element isolation region including a conductive film (22; Fig 1; ¶ [0034-35]) provided in a groove (trench; Fig 1; ¶ [0032]) with a first insulating film (20; Fig 1; ¶ [0032]) interposed therebetween, and a second insulating film (gate insulating film 17; Fig 1; ¶ [0033]) provided on the side of the first surface of the semiconductor layer so as to overlap the conductive film. Kanbe discloses problems associated with a shallow trench isolation structure in a photodetector, including dark current and white spots, and presents the disclosure as a solution (Kanbe; ¶ [0002-29]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the element isolation region of Kanbe with the photodetector of Shinohara. One would have been motivated to do this in order to reduce generation of dark current in the device (Kanbe; ¶ [0024,0028]) while maintaining an increased readout speed (Shinohara; ¶ [0005]). One would have had a reasonable expectation of success because of the similar trench structure of the element isolation regions of Kanbe and Shinohara in the similar photodetectors.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shinohara; Masato (JP 2020/057689; hereinafter Shinohara) in view of Kanbe; Hideo (JP 2005/167588; hereinafter Kanbe) and further in view of Chia; Chun-Wei et al.et al. (US 2017/0084664; hereinafter Chia).
Regarding claim 10, Shinohara in view of Kanbe discloses the photodetector according to claim 1, wherein the transistor (Shinohara; M3; Figs 3-4) includes a gate electrode (Shinohara; 138; Fig 4; ¶ [0031]) provided over the element formation region (Shinohara; 114; Fig 4) and the element isolation region (Shinohara; 116; Fig 4), and
the second insulating film (Kanbe; 17; Fig 1) is provided between the conductive film (Kanbe; 22; Fig 1) the gate electrode (as applied to claim 1).
Shinohara in view of Kanbe does not disclose the transistor including a side wall spacer provided on a sidewall of the gate electrode, and the second insulating film is provided between the conductive film and the side wall spacer.
In the same field of endeavor, Chia discloses an image sensor (photodetector) transistor structure including a side wall spacer (350; Fig 5; ¶ [0029]) provided on a sidewall of a gate electrode (320’; Fig 5; ¶ [0029]), wherein a second insulating film (gate insulating film 310’) is provided beneath the side wall spacer. Accordingly, it would have been obvious to a person having ordinary skill in the art that transistor of Shinohara in view of Kanbe may have a similar side wall spacer, thereby satisfying the limitation of claim 10. One would have been motivated to include such a side wall spacer in order to protect the gate electrode during the manufacturing process (for example, from a wet etchant chemical {Chia; ¶ [0026,35]}). One would have had a reasonable expectation of success because of the similar polysilicon film (Kanbe; ¶ [0035]; Chia; ¶ [0035]) used for the gate electrodes in the similar endeavors.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Shinohara; Masato (JP 2020/057689; hereinafter Shinohara) in view of Kanbe; Hideo (JP 2005/167588; hereinafter Kanbe) and further in view of Yanagita; Takeshi et al. (US 2016/0211288; hereinafter Yanagita).
Regarding claim 13, Shinohara in view of Kanbe discloses the photodetector according to claim 1, but does not disclose wherein the element isolation region further includes a pinning film interposed between the groove and the first insulating film.
In the same field of endeavor, Yanagita discloses a photodetector comprising an element isolation region (19; Fig 2; ¶ [0067]) including a pinning film (fixed charge film 20; Fig 2; ¶ [0067]) interposed between a groove (39; Fig 2; ¶ [0067]) and a first insulating film (21; Fig 2; ¶ [0067]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included a pinning film as disclosed by Yanagita in the photodetector of claim 1. One would have been motivated to do this in order to further suppress the occurrence of dark current (Yanagita; ¶ [0098]), and would have had a reasonable expectation of success because of the similar element isolation region function in the similar groove in the similar endeavor of Yanagita, Shinohara and Kanbe.
Allowable Subject Matter
Claim 5, 6, 9, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the conductive film includes a conductive material having a deeper Fermi level than the second semiconductor region”.
Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the conductive film includes a conductive material having a deeper work function than the second semiconductor region.
Regarding claim 9, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including wherein “the second insulating film is provided in a layer different from the gate insulating film”.
Regarding claim 12, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including wherein “the second insulating film has a larger film thickness than the gate insulating film”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou; Fei (US 2019/0067434; the prior art discloses selection of the material of an isolation material layer in a fin-based transistor based upon its relative Fermi level position to reduce a parasitic channel formation.
Madurawe; Raminda et al. (US 2017/0078539; the prior art discloses biasing a conductive film in the isolation structure of an image sensor to reduce dark current.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817