DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Preliminary Amendment
The Office acknowledges the applicant's 7/19/2023 preliminary amendment to: 1. Amend the instant Specification to correct the priority claim. 2. Amend Claim 19.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claims Status
Claims 1-20 are currently pending. Claim 19 has been amended. No claims have been canceled, and no new claims have been added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-3, 7-9, 17-18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 2 recites the limitations “the pixel unit” in lines 1-2; "a width of the first scanning conductive layer" in line 5 and "a width of the first scanning conductive layer" in line 7. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, “the pixel unit” in lines 1-2; "a width of the first scanning conductive layer" in line 5 and "a width of the first scanning conductive layer" in line 7 will be interpreted to read “each pixel unit” in lines 1-2; "a width of a first scanning conductive layer" in line 5 and "a width of a first scanning conductive layer" in line 7.
In Re claim 3, it is rejected due to its dependence from claim 2.
B. Claim 7 recites the limitations "the pixel unit" in lines 1-2 and "the sub-pixels" in line 3. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, "the pixel unit" in lines 1-2 will be interpreted to read the plurality of pixel units" and "the sub-pixels" in line 3 will be interpreted to read “the plurality of sub-pixels".
C. Claim 8 recites the limitation "the pixel unit" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 1, "the pixel unit" in lines 1-2 will be interpreted to read “the plurality of pixel units".
D. Claim 9 recites the limitations "the pixel unit" in lines 1-2 and "the pixel unit" in line 6. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, "the pixel unit" in lines 1-2 will be interpreted to read the plurality of pixel units" and "the pixel unit" in line 6 will be interpreted to read the plurality of pixel units".
E. Claim 17 recites the limitations "the pixel unit" in lines 1-2 and "of the pixel unit" in each of lines 4; 7; and 11. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, "the pixel unit" in lines 1-2 and "of the pixel unit" in lines 4; 7; and 11 will be interpreted to read “each pixel unit" and “of each pixel unit".
F. Claim 18 recites the limitations "of the pixel unit" in lines 6-7; 9; and 16-17; and “in the pixel unit” in line 12. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes and consistency with claim 1, "of the pixel unit" in lines 6-7; 9; and 16-17 will be interpreted to read “of each pixel unit" and “in the pixel unit” in line 12 will be interpreted to read “in the plurality of pixel units”
G. Claim 20 recites the limitation "the pixel unit" in line 2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes and consistency with claim 20, "the pixel unit" in line 2 will be interpreted to read “each pixel unit".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-9, 19; and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by JO et al (US 2021/0359079 A1, hereafter Jo).
Re claim 1, Joe discloses in FIGS. 1-10 a display substrate, comprising:
a base substrate (110; [0084]) and a plurality of pixel units (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen in FIG. 2; [0068] and [0083]) on the base substrate (110);
wherein each pixel unit (PX1/PX2/PX3 pixel group seen and each PX1/PX2/PX3 pixel group unseen) comprises:
a plurality of sub-pixels (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group left adjacent unseen) arranged sequentially (side-by-side) in a first direction (D2; [0086] and [0109]), wherein each sub-pixel (PX1/PX2/PX3 pixel group seen and each PX1/PX2/PX3 pixel group left adjacent unseen) comprises a sub-pixel driving circuit (T1/T2/T3/Cst in FIG. 1; [0067]-[0068] and [0083]) and a light-emitting element (LED ED; [0068] and [0083]), and the sub-pixel driving circuit (T1/T2/T3/Cst) is coupled (electrically and physically; [0070]) to the light-emitting element (LED ED);
at least one scanning line (151/151a; [0112]-[0113]), wherein each scanning line (151/151a) comprises a first scanning conductive layer (151) and a second scanning conductive layer (151a) arranged in a laminated manner (stacked), the first scanning conductive layer (151) is coupled (connected; [0113]) to the second scanning conductive layer (151a), the first scanning conductive layer (151) comprises at least a portion (all) extending in the first direction (D2), and the first scanning conductive layer (151) is coupled (connected; [0113]) to a plurality (of PX1/PX2/PX3 seen in FIG. 2) of sub-pixel driving circuits (T1/T2/T3/Cst of PX1/PX2/PX3 seen in FIG. 2) in the plurality of sub-pixels (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group left adjacent unseen).
Re claim 2, Jo discloses the display substrate according to claim 1, wherein each pixel unit (each PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group unseen) comprises: a first scanning line (151/151a; [0112]-[0113]) and a second scanning line (152/152a; [0115]);
an orthogonal projection (2D shadow) of the first scanning line (151/151a) onto the base substrate (110) and an orthogonal projection (2D shadow) of the second scanning line (152/152a) onto the base substrate (110) are arranged in a second direction (D1; [0104]-[0105]) crossing (normal to) the first direction (D2);
a width (extension at 151a) of a first scanning conductive layer (151) in the first scanning line (151/151a) in a direction perpendicular (D1) to an extending direction (D2) of the first scanning conductive layer (151) in the first scanning line (151/151a) is greater (wider) than a width (extension adjacent 152a) of a first scanning conductive layer (152) in the second scanning line (152/152a) in a direction perpendicular (D1) to an extending direction (D2) of the first scanning conductive layer (152) in the second scanning line (152/152a).
Re claim 5, Jo discloses the display substrate according to claim 1, wherein the second scanning conductive layer (151a) comprises at least a portion extending in the first direction (D2), an orthogonal projection (2D shadow) of the second scanning conductive layer (151a) onto the base substrate (110) is located within (overlapping) an orthogonal projection (2D shadow) of the first scanning conductive layer (151a) onto the base substrate (110).
Re claim 6, Jo discloses the display substrate according to claim 1, wherein the second scanning conductive layer (151a) comprises a plurality of second scanning patterns (151a for each PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen) independent of (separated from) each other, and the plurality of second scanning patterns (151a for each PX1/PX2/PX3 pixel group seen and each PX1/PX2/PX3 pixel group unseen) is coupled (connected; [0113]) to the first scanning conductive layer (151).
Re claim 7, Jo discloses the display substrate according to claim 2, wherein the plurality of pixel units (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen) further comprises: a plurality of data lines (DL1-178/DL2-178/DL3-178; [0086]) corresponding to the plurality of sub-pixels (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group left adjacent unseen) respectively, wherein each data line (DL1-178/DL2-178/DL3-178) comprises a first data conductive layer (171a/171b/17c; [0086]) and a second data conductive layer (178 of 171a/178 of 171b/178 of 171c; [0125]) arranged in a laminated manner (stacked), the first data conductive layer (171a/171b/17c) is coupled (connected; [0125]) to the second data conductive layer (178 of 171a/178 of 171b/178 of 171c), the second data conductive layer (178 of 171a/178 of 171b/178 of 171c) comprises at least a portion extending in the second direction (D1) crossing (normal to) the first direction (D2), and the second data conductive layer (178 of 171a/178 of 171b/178 of 171c)is coupled (connected; [0125]) to a sub-pixel driving circuit (T1/T2/T3/Cst) in a corresponding sub-pixel (PX1/PX2/PX3).
Re claim 8, Jo discloses the display substrate according to claim 7, wherein the plurality of pixel units (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen) further comprises: a first power source line (170/170a; [0110]) comprising a first power source conductive layer (170; [0110]) and a second power source conductive layer (170a; [0110]) arranged in a laminated manner (stacked), the first power source conductive layer (170) being coupled (connected; [0110]) to the second power source conductive layer (170a), the second power source conductive layer (170a) comprising a portion extending in the second direction (D1), and the second power source conductive layer (170a) being coupled to the sub-pixel driving circuit (T1/T2/T3/Cst) in the corresponding sub-pixel (PX1/PX2/PX3).
Re claim 9, Jo discloses the display substrate according to claim 8, wherein the plurality of pixel units (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen) further comprises: a sensing line (173/173a; [0129]) comprising a first sensing conductive layer (173; [0129]) and a second sensing conductive layer (173a; [0129]) arranged in a laminated manner (stacked) and coupled (connected; [0129]) to each other, the second sensing conductive layer (173a) comprising a portion extending in the second direction (D1), and the second sensing conductive layer (173a) being coupled to each sub-pixel driving circuit (each T1/T2/T3/Cst) in the plurality of pixel units (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen).
Re claim 19, Jo discloses a display device ([0198]) comprising the display substrate according to claim 1 (see above).
Re claim 20, Joe discloses in FIGS. 1-10 a method for manufacturing a display substrate, comprising:
fabricating (forming) a plurality of pixel units (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen in FIG. 2; [0068] and [0083]) on a base substrate (110; [0084]), each pixel unit comprising:
a plurality of sub-pixels (PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group left adjacent unseen) arranged sequentially (side-by-side) in a first direction (D2; [0086] and [0109]), wherein each sub-pixel (each PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group left adjacent unseen) comprises a sub-pixel driving circuit (T1/T2/T3/Cst in FIG. 1; [0067]-[0068] and [0083]) and a light-emitting element (LED ED; [0068] and [0083]), and the sub-pixel driving circuit (T1/T2/T3/Cst) is coupled (electrically and physically; [0070]) to the light-emitting element (LED ED);
at least one scanning line (151/151a; [0112]-[0113]), wherein each scanning line (151/151a) comprises a first scanning conductive layer (151) and a second scanning conductive layer (151a) arranged in a laminated manner (stacked), the first scanning conductive layer (151) is coupled (connected; [0113]) to the second scanning conductive layer (151a), the first scanning conductive layer (151) comprises at least a portion (all) extending in the first direction (D2), and the first scanning conductive layer (151) is coupled (connected; [0113]) to a plurality (of PX1/PX2/PX3 seen in FIG. 2) of sub-pixel driving circuits (T1/T2/T3/Cst of PX1/PX2/PX3 seen in FIG. 2) in the plurality of sub-pixels (each PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel group left adjacent unseen).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of GANG et al (US 2018/0033850 A1, hereafter Gang).
Re claim 3, Jo discloses the display substrate according to claim 2.
But, fails to disclose wherein the first scanning conductive layer (151) in the first scanning line (151/151a) comprises a first hollowed-out region.
However,
Gang discloses in FIGS. 5 and 8 a display substrate, comprising: wherein a first scanning conductive layer (GL1a; [0056]) in a first scanning line (GL1a) comprises a first hollowed-out region (RDD; [0073]-[0074]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Jo by using the first hollowed-out region of Gang with the first scanning conductive layer (151) in the first scanning line (151/151a) to comprises a first hollowed-out region, to create short circuit repair locations for regions of conductive lines overlapped by the first scanning conductive layer (Gang; [0073]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jo and Gang as applied to claim 3 above, and further in view of Cheng et al (US 2018/0157099 A1, hereafter Cheng).
Re claim 4, Jo discloses the display substrate according to claim 2, wherein the first scanning conductive layer (152) in the second scanning line (152/152a) comprises: a first scanning sub-pattern (152 over 152a) and a second scanning sub-pattern (152 beyond 152a) arranged alternately (periodically), a width (extension) of the first scanning sub-pattern (152 over 152a) in a direction perpendicular (D1) to the first direction (D2) is greater (more) than a width (extension) of the second scanning sub-pattern (152 beyond 152a) in the direction perpendicular (D1) to the first direction (D2).
But, fails to disclose the width of the first scanning sub-pattern (152 over 152a) in the direction perpendicular (D1) to the first direction (D2) is less than the width (extension at 151a) of the first scanning conductive layer (151) in the first scanning line (151/151a) in the direction perpendicular (D1) to the extending direction (D2) of the first scanning conductive layer (151) in the first scanning line (151/151a), and the first scanning sub-pattern (152 over 152a) comprises a second hollowed-out region.
However, Gang would render the first scanning sub-pattern (152 over 152a) comprises a second hollowed-out region by forming the second scanning conductive layer as discussed for the first scanning conductive layer in claim 3.
Further,
Cheng discloses in FIG. 1A a display device comprising scanning lines (120; [0022]) of variable widths ([0022]), and it would have been obvious to form the width of the first scanning sub-pattern (152 over 152a) in the direction perpendicular (D1) to the first direction (D2) to be less than the width (extension at 151a) of the first scanning conductive layer (151) in the first scanning line (151/151a) in the direction perpendicular (D1) to the extending direction (D2) of the first scanning conductive layer (151) in the first scanning line (151/151a), and the first scanning sub-pattern (152 over 152a) comprises a second hollowed-out region, to provide specific electrical characteristics to its corresponding active device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of PARK et al (US 2022/0199677 A1, hereafter Park) and KITABAYASHI et al (US 2010/0096988 A1, hereafter Kitabayashi).
Re claim 10, Jo discloses the display substrate according to claim 9.
But, fail to disclose wherein the first scanning conductive layer (151), the first data conductive layer (171a/171b/17c), the first power source conductive layer (170) and the first sensing conductive layer (173) are arranged at a same layer and made of a same material; the second scanning conductive layer (151a), the second data conductive layer (178 of 171a/178 of 171b/178 of 171c), the second power source conductive layer (170a) and the second sensing conductive layer (173a) are arranged at a same layer and made of a same material.
However,
A. Park discloses in FIGS. 5, 7 and 9 a display device comprising: wherein a first scanning conductive layer (CL1; [0227]), a first data conductive layer (D1/D2/D3; [0227]), a first power source conductive layer (PL1a/PL2a; [0227]) and the first sensing conductive layer (IPL; [0227]) are arranged at a same layer ([0227]) and made of a same material ([0197]; [0207] and [0227]).
And,
B. Kitabayashi discloses in FIGS. 8B and 9C a display device comprising: wherein a first scanning conductive layer (31; [0125]) and a first data conductive layer (41; [0125]) are arranged at a same layer ([0125]) and made of a same material (Al; [0125], and wherein a second scanning conductive layer (31c; [0127]) is coupled (at 14g; [0127]) to the first scanning conductive layer (31).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Jo by using the simultaneous conductive layer formation of Park and Kitabayashi, and the coupling technique of Kitabayashi for overlapping lines, wherein the first scanning conductive layer (151), the first data conductive layer (171a/171b/17c), the first power source conductive layer (170) and the first sensing conductive layer (173) are arranged at a same layer and made of a same material; and the second scanning conductive layer (151a), the second data conductive layer (178 of 171a/178 of 171b/178 of 171c), the second power source conductive layer (170a) and the second sensing conductive layer (173a) are arranged at a same layer and made of a same material, to form thinner displays with fewer materials.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of TANG et al (US 2020/0227499 A1, hereafter Tang).
Re claim 11, Jo discloses the display substrate according to claim 9, wherein the sub-pixel driving circuit (T1/T2/T3/Cst) comprises a storage capacitor (Cst; [0068] and [0083]).
But, fails to disclose the storage capacitor (Cst) comprising a first transparent plate and a second transparent plate arranged opposite to each other, and the first transparent plate is located between the second transparent plate and the base substrate.
However,
Tang discloses in FIG. 11 a display device comprising: a storage capacitor (layer laminate 16/20/24/30/32; [0091] and [0109]), the storage capacitor (layer laminate 16/20/24/30/32) comprising a first transparent plate (16) and a second transparent plate (24) arranged opposite to each other, and the first transparent plate (16) is located between the second transparent plate (24) and a base substrate (10; [0077]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Jo by forming the storage capacitor of Jo as a transparent capacitor, as disclosed by Tang, to form bottom-emitting displays with a plurality of capacitor structures connected in series to increase the capacitance of the OLED panel and eliminate the pressure drop phenomenon (Tang; [0091] and [0109]).
Re claim 12, Jo discloses the display substrate according to claim 11, wherein the sub-pixel driving circuit (T1/T2/T3/Cst) further comprises:
a driving transistor (T1; [0070]), wherein a gate electrode (FIG. 1; [0070]) of the driving transistor (T1) is coupled (connected; [0070]) to the second plate (terminal; [0070]), a first electrode (FIG. 1; [0070]) of the driving transistor (T1) is coupled (connected; [0070]) to a first power source line (ELVDD; [0070]), and a second electrode of the driving transistor (T1) is coupled to the first plate (other terminal; [0070]) and the light-emitting element (LED ED); the driving transistor (T1) comprises a driving active layer (channel; [0069]).
Jo fails to disclose the gate electrode of the driving transistor (T1) is coupled to the second transparent plate, and the second electrode of the driving transistor (T1) is coupled to the first transparent plate; and the second transparent plate is arranged at a same layer and made of a same material as the driving active layer (channel).
However, Tang discloses the second transparent plate (24), the first transparent plate (16); and the second transparent plate (24) is arranged at a same layer ([0086]) and made of a same material (same process; [0080] and [0102]) as a driving active layer (24; [0080] and [0102]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the structure of Jo by forming the second transparent plate arranged at a same layer and made of a same material as a driving active layer, as part of the series capacitors discussed for claim 11.
Re claim 13, Jo and Tang disclose the display substrate according to claim 12, wherein the driving active layer (Tang: 24) comprises a driving channel portion (Tang: unlabeled portion of 24 between unlabeled source/drain regions); the sub-pixel (Jo: PX1/PX2/PX3) further comprises a first conductive connection member (Tang: unlabeled horizontal portion of right 32; [0106]) through which the second electrode (Jo: FIG. 1) of the driving transistor (Jo: T1) is coupled to the first transparent plate (16) and the light-emitting element (Jo: LED ED), an orthogonal projection (2D shadow) of the first conductive connection member (Tang: unlabeled horizontal portion of right 32) onto the base substrate (Tang: 10) at least partially overlaps an orthogonal projection (2D shadow) of the driving channel portion (unlabeled portion of 24 between unlabeled source/drain regions) onto the base substrate (10), as part of the series capacitors discussed for claim 11.
Re claim 14, Jo discloses the display substrate according to claim 13, wherein the sub-pixel driving circuit (T1/T2/T3/Cst) further comprises:
a written-in transistor (T2; [0071]), wherein a gate electrode (FIG. 1; [0071]) of the written-in transistor (T2) is coupled (connected; [0071]) to the first scanning line (151/151a), a first electrode (FIG. 1; [0071]) of the written-in transistor (T2) is coupled (connected; [0071]) to a corresponding data line (DL1-178/DL2-178/DL3-178), and a second electrode (FIG. 1; [0071]) of the data written-in transistor (T2) is coupled to the gate electrode (FIG. 1; [0071]) of the driving transistor (T1);
a sensing transistor (T3; [0072]), wherein a gate electrode (FIG. 1; [0072]) of the sensing transistor (T3) is coupled to the second scanning line (152/152a), a first electrode (FIG. 1; [0072]) of the sensing transistor (T3) is coupled to the light-emitting element (LED ED), and a second electrode (FIG. 1; [0072]) of the sensing transistor (T3) is coupled to the sensing line (173/173a).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jo and Tang as applied to claim 14 above, and further in view of CHOI (US 2019/0131369 A1, hereafter Choi).
Re claim 15, Jo discloses the display substrate according to claim 14, wherein the sensing transistor (T2) comprises a sensing active layer (channel; [0069]), the written-in transistor (T2) comprises a written-in active layer (channel; [0069]), and the sensing active layer (channel; [0069]), the second plate (terminal) and the written-in active layer (channel) are arranged sequentially (stacked) in the second direction (D1), and the driving active layer (channel) and a part of the second plate (terminal) are arranged in the first direction (D2).
Jo fails to disclose the second transparent plate and the written-in active layer are arranged sequentially in the second direction, and the second transparent plate and the written-in active layer are formed as one piece.
However,
A. Tang discloses the second transparent plate above (see claim 11).
And,
B. Choi discloses in FIGS. 3, 8 and 15 a display substrate comprising: a second plate (SWACT of Cst; [0085] and [0092]) and a written-in active layer (DACT of SW; [0085] and [0091]) are formed as one piece (FIG. 8).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify the structure of Jo and Tang by using the second plate and the written-in active layer are formed as one piece, as disclosed by Choi, such that the second transparent plate and the written-in active layer are arranged sequentially in the second direction, and the second transparent plate and the written-in active layer are formed as one piece, forming the pixel circuit with fewer patterning steps.
Re claim 16, Jo discloses the display substrate according to claim 15.
But, fails to disclose wherein the first transparent plate comprises a first transparent portion and a second transparent portion arranged in the second direction (D1), and a width of the first transparent portion in the first direction is less than a width of the second transparent portion in the first direction (D1);
the first transparent portion is coupled to the first electrode of the sensing transistor (T3), an orthogonal projection of the first transparent portion onto the base substrate (110) does not overlap an orthogonal projection of the second transparent plate onto the base substrate (110);
an orthogonal projection of the second transparent portion onto the base substrate (110) at least partially overlaps the orthogonal projection of the second transparent plate onto the base substrate (110), and the orthogonal projection of the second transparent portion onto the base substrate at least partially overlaps an orthogonal projection of the driving active layer (channel of T1) onto the base substrate (110).
However,
A. Tang discloses the first transparent plate and the second transparent plate as discussed above (see claim 11).
And,
B. Choi discloses wherein the first plate (LS of Cst; [0080]) comprises a first portion (lower part at SSD1; [0078]) and a second portion (upper part at Cst) arranged in a second direction (vertically), and a width (extension) of the first portion (lower part at SSD1) in a first direction (horizontally) is less (narrower) than a width (extension) of the second portion (upper part at Cst) in the first direction (horizontally);
the first portion (lower part at SSD1) is coupled (connected) to the first electrode (SSD1; [0086]) of the sensing transistor (ST; [0061]), an orthogonal projection (2D shadow) of the first portion (lower part at SSD1) onto a base substrate (SUB1; [0069]) does not overlap (not covering) an orthogonal projection (2D shadow) of the second plate (SWACT of Cst) onto the base substrate (SUB1);
an orthogonal projection (2D shadow) of the second portion (upper part at Cst) onto the base substrate (SUB1) at least partially overlaps (at SW) the orthogonal projection (2D shadow) of the second plate (SWACT of Cst) onto the base substrate (SUB1), and the orthogonal projection (2D shadow) of the second portion (upper part at Cst) onto the base substrate (SUB1) at least partially overlaps (at DR) an orthogonal projection (2D shadow) of the driving active layer (channel of DR; [0089]) onto the base substrate (SUB1).
Thus, it would have been obvious that the transparent plates of Tang combined with Choi would render the deficiencies of Jo obvious, as part of the pixel circuit discussed for claim 15.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jo and Tang and Choi as applied to claim 15 above, and further in view of BEAK et al (US 2015/0187854 A1, hereafter Beak).
Re claim 17, Jo discloses the display substrate according to claim 15, wherein the pixel unit comprises a first color filter layer (450a/450b/450c; [0219]); the written-in active layer (metal oxide semiconductor of T2) comprises a written-in channel portion (channel of T2; [0069]),
But, fails to discloses and an orthogonal projection of the first color filter layer (450a/450b/450c) onto the base substrate (110) at least partially overlaps the orthogonal projection of the driving channel portion (channel of T1) in each sub-pixel of the plurality of pixel units onto the base substrate (110);
the orthogonal projection of the first color filter layer (450a/450b/450c) onto the base substrate (110) at least partially overlaps an orthogonal projection of the written-in channel portion (channel) in each sub-pixel of the plurality of pixel units onto the base substrate (110);
the sensing active layer (metal oxide semiconductor of T3) comprises a sensing channel portion (Channel; [0069]), and the orthogonal projection of the first color filter layer (450a/450b/450c) onto the base substrate (110) at least partially overlaps an orthogonal projection of the sensing channel portion (channel) in each sub-pixel of the plurality of pixel units onto the base substrate (110).
However,
Beak discloses in FIG. 3M a display device comprising: a color filter layer (180/190; [0062]-[0063]), an orthogonal projection (2D shadow) of the first color filter layer (180/190) onto the base substrate (110) at least partially overlaps an orthogonal projection (2D shadow) of a driving channel portion (214 of DR-TFT; [0050]) a sub-pixel (R, G or B) of a plurality of pixel units (R/G/B; [0063]) onto a base substrate (100; [0062]);
the orthogonal projection (2D shadow) of the first color filter layer (180/190) onto the base substrate (110) at least partially overlaps an orthogonal projection (2D shadow) of a written-in channel portion (114 of SW-TFT; [0050]) in the sub-pixel (R, G or B) of the plurality of pixel units (R/G/B) onto the base substrate (110).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Jo by forming its color filter layer as disclosed by Beak, such that an orthogonal projection of the first color filter layer (450a/450b/450c) onto the base substrate (110) at least partially overlaps the orthogonal projection of the driving channel portion (channel of T1) in each sub-pixel of the plurality of pixel units onto the base substrate (110); the orthogonal projection of the first color filter layer (450a/450b/450c) onto the base substrate (110) at least partially overlaps an orthogonal projection of the written-in channel portion (channel) in each sub-pixel of the plurality of pixel units onto the base substrate (110); the sensing active layer (metal oxide semiconductor of T3) comprises a sensing channel portion (Channel; [0069]), and the orthogonal projection of the first color filter layer (450a/450b/450c) onto the base substrate (110) at least partially overlaps an orthogonal projection of the sensing channel portion (channel) in each sub-pixel of the plurality of pixel units onto the base substrate (110), for more planar surfaces for the bottom-emitting devices discussed for claim 11.
Re claim 18, Jo and Beak disclose the display substrate according to claim 17, and would render obvious the limitations of wherein the first color filter layer (Beak: 180/190) comprises: a first color filter pattern (for R), a second color filter pattern (for G) and a third color filter pattern (for B);
at least a part of the first color filter pattern (for R) extends in the first direction (laterally);
an orthogonal projection (2D shadow) of the first color filter pattern (for R) onto the base substrate (100) at least partially overlaps the orthogonal projection (2D shadow) of the written-in channel portion (channel of SW-TFT) in each sub-pixel (R, G or B) of each pixel unit (R/G/B) onto the base substrate (100);
the orthogonal projection (2D shadow) of the first color filter pattern (for R) onto the base substrate (100) at least partially overlaps the orthogonal projection (2D shadow) of the driving channel portion (channel of DR-TFT) in each sub-pixel (R, G or B) of each pixel unit (R/G/B) onto the base substrate (100);
at least a part of the second color filter pattern (for G) extends in the second direction (into the page);
an orthogonal projection (2D shadow) of the second color filter pattern (for G) onto the base substrate (100) at least partially overlaps an orthogonal projection of a pixel opening region (at OLED) of a first sub-pixel (G) in the plurality of pixel units (R/G/B) onto the base substrate (100) as part of the planar filters discussed for claim 17.
With regard to the limitations of at least a part of the third color filter pattern extends in the first direction, an orthogonal projection of the third color filter pattern onto the base substrate at least partially overlaps the orthogonal projection of the sensing channel portion in each sub-pixel of each pixel unit onto the base substrate, as discussed for claim 17, the color filter layer (180/190) for the blue sub-pixel would be formed overlapping the sensing channel portion of Jo, in each sub-pixel (R, G or B) of each pixel unit (R/G/B), such that at least a part of the third color filter pattern (for B) extends in the first direction (laterally), an orthogonal projection (2D shadow) of the third color filter pattern (for B) onto the base substrate (100) at least partially overlaps the orthogonal projection (2D shadow) of the sensing channel portion (channel of T3 of Jo) of in each sub-pixel (PX1, PX2 or PX3 pixel) of each pixel unit (each PX1/PX2/PX3 pixel group seen and PX1/PX2/PX3 pixel groups unseen) onto the base substrate, as would be part of the planar surfaces for the bottom-emitting devices discussed for claims 11 and 17.
Conclusion
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/ERIC W JONES/Primary Examiner, Art Unit 2892