DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title include the phrase “compensating electrostatic discharge events.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 & 2 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. to Ka et al. (hereinafter “Ka”) in view of Chinese Pat. Pub. No. CN 108550584 A to Zhou et al. (hereinafter “Zhou”).
Regarding claim 1, Ka et al. teaches a display substrate (SUB; fig. 1B) [0046], comprising:
a display region (pixel areas PXA, may be any of PXA1, PXA2, etc.; fig. 1B) [0051] and a peripheral region (PPA, may be any of PPA1, PPA2, etc.; fig. 1B) [0051] surrounding the display region (PXA), the peripheral region (PPA) comprising a bonding region (area of data driver DDV and power source supply line ELVDD, hereinafter “bonding area”; fig. 1B) [0073] & [0082] and a profiled region (additional peripheral region APA in contact with peripheral region PPA2; fig. 1B) [0058] & [0067], at least part of the display region (PXA) being located between the bonding region (bonding area) and the profiled region (APA);
wherein the display substrate (SUB) further comprises a plurality of compensation scanning lines (scan lines S21, S22, S31, and S32 in addition to at least one of the lines ES/EE, each of the lines fulfilling a load compensation role, hereinafter “compensation lines”; figs. 6 & 15) [0232]-[0236] & [0242]-[0243] and a plurality of data lines (D1, D2, D3, etc., hereinafter “Dm”; fig. 6) [0089], at least one of the compensation scanning lines (compensation lines) comprises a portion (at least a portion of lines ES/EE; fig. 15) located in the profiled region (APA), and at least one of the data lines (Dm) comprises a portion (portion which connects to ELVSS) located in the display region (PXA, see figs. 1B and 6) and a portion located in the profiled region (APA, at least data line D4 being connected to second power source supply line ELVSS {fig. 6}, the element ELVSS being located in profile area APA {fig. 15});
a loading compensation structure (dummy unit DU; fig. 15) [0224] are arranged in the profiled region (APA).
an electrostatic discharge circuit (electrostatic protection parts; claim 31) wherein at least part of the electrostatic discharge circuit is located between the display region and the loading compensation structure; the electrostatic discharge circuit (electrostatic protection parts) being coupled to the plurality of data lines (Dm; referred to in claim 31 as first to third lines which are connected to the first to third pixels; see claim 1).
Ka does not teach an electrostatic discharge circuit wherein at least part of the electrostatic discharge circuit is located between the display region and the loading compensation structure.
Zhou, however, teaches a display substrate (fig. 1) comprising an electrostatic discharge circuit (1214; fig. 3) [0041] wherein at least part of the electrostatic discharge circuit (1214) is located between the display region (1100; fig. 3) [0037] and the loading compensation structure (compensation capacitors placed between gate drive circuits 1212; fig. 3) [0040]; the electrostatic discharge circuit (1214) being coupled (through electrostatic interaction) to the plurality of data lines (data driving lines as part of display area 1110) [0046].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the substrate of Ka to comprise an ESD circuit between the compensation structure and the display region to protect surrounding components as taught by Zhou [0041].
Regarding claim 2, Ka in view of Zhou teaches the display substrate according to claim 1, wherein the display substrate (SUB) further comprises a common signal line (ELVSS and AUP, fig. 17) [0082] & [0239], an orthogonal projection of the common signal line onto a base substrate (portion of SUB in the profile region, hereinafter “base substrate,” see fig. 14) of the display substrate (SUB) at least partially overlaps an orthogonal projection of the plurality of compensation scanning lines (compensation lines) onto the base substrate (base substrate), and the common signal line serves as the loading compensation structure (parasitic capacitance used in load compensation) [0227] & [0241].
Claims 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ka in view of Zhou as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20210325751 A1 to Zhang et al. (hereinafter “Zhang”).
Regarding claim 15, Ka in view of Zhou teaches a display panel, comprising the display substrate according to claim 1,
Ka in view of Zhou does not teach wherein the display panel further comprises an opposing substrate arranged opposite to the display substrate; the opposing substrate comprises: a black matrix layer, wherein the black matrix layer comprises a display region pattern and a non-display region pattern, an orthogonal projection of the display region pattern onto the display substrate is located in the display region of the display substrate, and an orthogonal projection of the non-display region pattern onto the display substrate is located in the peripheral region of the display substrate; a black matrix hollowed-out region is provided between the display region pattern and the non-display region pattern.
Zhang, however, teaches a display panel (fig. 2A) wherein the display panel further comprises an opposing substrate (second substrate 40; fig. 2A) [0041] arranged opposite to the display substrate (display substrate 10; fig. 2A) [0042]; the opposing substrate (40) comprises: a black matrix layer (30; fig. 2A) [0041], wherein the black matrix layer (30) comprises a display region pattern (pattern with gaps near center; fig. 2A)) and a non-display region pattern (31 near peripheral of fig. 2A), an orthogonal projection of the display region pattern (center pattern 30) onto the display substrate (10) is located in the display region (near center) of the display substrate (10), and an orthogonal projection of the non-display region pattern (peripheral) onto the display substrate (10) is located in the peripheral region (peripheral in fig. 2A) of the display substrate (10); a black matrix hollowed-out region (31; fig. 2A) is provided between (see fig. 10) the display region pattern (center 30) and the non-display region pattern (peripheral 30).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention to modify the display panel of Ka to include the limitations of claim 15 to reduce signal interference (i.e., crosstalk) as taught by Zhang (for the hollowed-out region) [0044] & [0075].
It further would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention to modify the display panel of Ka to include the limitations of claim 15 to enhance display effect as taught by Zhang (for the black-matrix material limitations) [0075].
Regarding claim 17, Ka in view of Zhou and Zhang, as currently modified, does not teach the display panel according to claim 15, wherein the opposing substrate further comprises a support layer, and at least part of the support layer is located in the black matrix hollowed-out region.
Zhang, however, teaches wherein the opposing substrate (second substrate 40; fig. 7) [0041] further comprises a support layer (second black matrix material, filling the hollow out area 31; compare figs. 2A & 7) [0069], and at least part of the support layer (second black matrix material) is located in the black matrix hollowed-out region (hollow area; fig. 2A) [0042].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the display panel of Ka in view of Zhang to comprise a support layer in the hollow out region to further reduce signal feedback i.e., crosstalk as taught by Zhang [0069].
Regarding claim 20, Ka in view of Zhou and Zhang teaches a display device (fig. 1B) comprising the display panel according to claim 15.
Allowable Subject Matter
Claims 3-14, 16, 18, & 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, it is not found a teaching or a motivation to modify the width of the compensation part when compared to the non-compensation part in a direction perpendicular to an extending direction of the non-compensation portion. Chinese Pat. Pub. No. CN 113270045 A to Huang, which is of record, teaches that the width of compensation parts allows for consistent capacitance compensation, but this reference is not considered to teach the person of ordinary skill in the art enough to allow for them to reach the relationship of claim 3 through routine experimentation under M.P.E.P. 2144.05 II (A). Claims 4-10 are allowable only by nature of their dependence on claim 3.
Regarding claim 11, it is not found an electro discharge sub-circuit requiring the limitations of claim 11 and further comprising a gate electrode of the second transistor is coupled to the output electrode of the second transistor. The closest are found is CN 108492761 A to Jin, which is of record, which teaches an electro discharge sub-circuit in fig. 9 but this circuit does not teach the limitations of claim 11. Claims 11-14 are allowable only by nature of their dependence on claim 11.
Regarding claim 16, it is not found a reference which reasonably reads on the positioning of the electrostatic discharge circuit being disposed between the loading compensation structure and black matrix hollowed-out region.
Regarding claim 18, there exist references which teach blue filter patterns in a black matrix pattern with a hollowed-out region, but there is not found such blue filters being located with a portion in the hollowed-out region of the black matrix and a portion at the periphery of the black matrix hollowed-out region.
Regarding claim 19, Chinese Pat. Pub. No. CN 110703492 A to Yu teaches a display panel meeting most limitations of claim 19, but does not teach partial overlap between the sealant, the base substrate, and a hollowed-out region of a common signal line.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Pat. Pub. No. US 20180231827 A1 to Choi et al. teaches opposing substrates with black matrix patterns and blue filters therein.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892