DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 17 February 2026 of Applicant’s amendments in which claims 1-7, 9, and 10 are amended. The claim objections identified in the Office Communication dated 18 November 2025 are withdrawn in view of the amendments.
Response to Arguments
Applicant’s arguments with respect to independent claim(s) 1, 9, and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues, in the paragraph bridging pages 11 and 12 and with respect to claim 7, that the rationale proffered to combine the teachings of Yoshimochi, Lee, Ritenour, and Nihei is based on hindsight, and is thus improper {see, e.g., last sentence of first paragraph of page 12}. Claim 7 is rejected over the combined teachings of Yoshimochi, Miura, Lee, and Nihei and recites, in relevant part, “the source electrode includes a metal material same as that of the first low thermal resistance material section, the source electrode is integral with the first low thermal resistance material section, the drain electrode includes a metal material same as that of the second low thermal resistance material section, and the drain electrode is integral with the second low thermal resistance material section.” Any judgment on obviousness is in a sense necessarily a reconstruction based on hindsight reasoning, but so long as it takes into account only knowledge which was within the level of ordinary skill in the art at the time the claimed invention was made and does not include knowledge gleaned only from applicant’s disclosure, such a reconstruction is proper. MPEP 2145(X)(A). As this principle applies to the present circumstance, Yoshimochi teaches in Fig. 9 the source electrode (9) includes a metal material (Cu/Ti) same as that (Cu/Ti) of the first low thermal resistance material section (section of 42/44) {¶0082, 0138}. In an embodiment illustrated by Fig. 1, Yoshimochi teaches a drain electrode (10) includes a metal material (Cu/Ti) same as that (Cu/Ti) of a second low thermal resistance material section (section of 22/24) {¶0092, 0093}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura and Lee based on the further teachings of Yoshimochi – such that the drain electrode includes a metal material same as that of the second low thermal resistance material section – to electrically/thermally connect … the source electrode … to the back surface. Yoshimochi ¶0007. Moreover, all the claimed elements (e.g., low thermal resistance material section, metal, drain electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yoshimochi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. And in an analogous art, Nihei teaches in Fig. 1G and paragraph [0073] an electrode (10) is formed in a hole (9) – passing through a top surface of a semiconductor device and a channel layer (5) and down into a semiconductor substrate – so as to be directly connected to a heat conductor (4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device based on the teachings of Nihei – such that each of: (1) Yoshimochi’s second low thermal resistance material section and drain electrode are integrally formed and (2) Yoshimochi’s first low thermal resistance material section and source electrode are integrally formed – so heat generated in the HEMT becomes easy to escape to the heat conductor … and it becomes further easier to prevent the temperature increase in the HEMT. Nihei ¶0073. Moreover, all the claimed elements (e.g., source electrode, low thermal resistance material section, drain electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Nihei) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim Objections
Applicant is advised that should claim 9 be found allowable, claim 10 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Independent claim 10 differs from independent claim 9 only in the label within the preamble identifying the claimed subject matter. Claim 9 recites a semiconductor module whereas claim 10 recites an electronic apparatus. These labels do not change the claimed structure in any way.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimochi (US20190296112A1) in view of Miura et al. (US20150221758A1) and Lee et al. (US20050029506A1).
Regarding claim 1, Yoshimochi teaches in Fig. 9 a semiconductor device comprising:
a semiconductor layer (2) {¶0164};
a channel layer (4) stacked on the semiconductor layer (2) {¶0078};
wherein the channel layer (4) includes a semiconductor material (GaN) different from that (Si) of the semiconductor layer (2) {¶0078, 0183};
a buffer layer (3) between the semiconductor layer (2) and the channel layer (4) {¶0072};
a barrier layer (5) on the channel layer (4) {¶0079; barrier layer (5) made of AlGaN, same as Applicants’ barrier layer};
a recess section (41) from the barrier layer (5) to the buffer layer (3) {¶0137};
a gate electrode (11) on the barrier layer (5) {¶0074};
a source electrode (9) on the barrier layer (5) {¶0073};
a drain electrode (10) on the barrier layer (5), wherein the source electrode (9) and the drain electrode (10) are at positions sandwiching the gate electrode (11) {¶0073};
a low resistance material section (section of 5a) in contact with the barrier layer (5), the channel layer (4), and one of the source electrode (9) or the drain electrode (unselected alternative) {¶0136}; and
a low thermal resistance material section (section of 42/44) in contact with the channel layer (4), the buffer layer (3), and one of the source electrode (9) or the drain electrode (unselected alternative) {¶0138};
wherein the low thermal resistance material section (section of 42/44, e.g., Cu) has a thermal resistance lower than a thermal resistance of the channel layer (4, which is GaN) {¶0138 Cu has a lower thermal resistance than GaN}; and
the low thermal resistance material section (section of 42/44) is in the recess section (41) {¶0138}.
Yoshimochi does not teach the buffer layer is on a bottom surface of the recess section.
In an analogous art, Miura teaches in Fig. 5 and paragraph [0067] a recess section (TH) from a barrier layer (BA) to a buffer layer (BU1), wherein the buffer layer (Bu1) is on a bottom surface of the recess section (TH). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device based on the teachings of Miura – such that Yoshimochi’s recess section extends from the barrier layer to the buffer layer, and the buffer layer is on a bottom surface of the recess section – to bring the potential of the buffer layer … close to a source potential (for example, ground potential)[,] … enable[] production of a two-dimensional electron gas 2DEG2 at the interface between the [first] buffer layer …and the [second] buffer layer[, and/or achieve an] … increase in threshold voltage and improvement in normally-off characteristics. Miura [0067]. Moreover, all the claimed elements (e.g., buffer layer, bottom surface, recess section) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Miura) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Yoshimochi does not teach expressly the low resistance material section has a resistance lower than a resistance of the channel layer.
Yoshimochi characterizes section (section of 5a) as a low resistance region 5a in which Al is diffused [in GaN]. In an analogous art, Lee teaches in Fig. 2 and paragraph [0037] an AlGaN layer having a lower electrical resistance than a GaN layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura based on the teachings of Lee – such that Yoshimochi’s AlGaN low resistance material section has a lower resistance than Yoshimochi’s GaN channel layer – for reducing an electric resistance {Lee ¶0037} and the reduction of the driving voltage {Lee ¶0038}. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 2, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 1, and Yoshimochi further teaches wherein the low thermal resistance material section (section of 42/44) includes a metal material (Cu/Ti) {¶0138}, and
the low thermal resistance material section (section of 42/44) is configured to penetrate the barrier layer (5) and the channel layer (4) {Fig. 1; ¶0138}.
Regarding claim 3, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 2, and Yoshimochi further teaches wherein
the low thermal resistance material section (section of 42/44) is in contact (e.g., electrical/thermal contact) with one of the source electrode (9) or the drain electrode (unselected alternative) {¶0138; see Examiner’s Note below}, and
the low thermal resistance material section (section of 42/44) is directly below one of the source electrode (9) or the drain electrode (unselected alternative) {Fig. 1; ¶0138 }.
Examiner’s Note: The American Heritage College Dictionary, fourth edition, defines the fourth sense (i.e., most common usage) of “contact” to mean ‘[a] connection between two conductors that permits a flow of current or heat.”
Regarding claim 4, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 2, and Yoshimochi further teaches wherein the low thermal resistance material section (section of 42/44) is ohmic bonded to the low resistance material section (section of 5a) {the interface between the low thermal resistance material section made of Cu and the low resistance material section made of AlGaN is Ohmic bonded because both materials have low electrical resistance and, therefore, have a linear current-voltage curve}.
Regarding claim 6, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 3, and Yoshimochi further teaches wherein the low thermal resistance material section (section of 42/44) includes a first low thermal resistance material section (section of 42/44) in contact with the source electrode (9) and directly below the source electrode (9) {¶0138}.
Yoshimochi does not teach in the embodiment illustrated by Fig. 9 a second low thermal resistance material section in contact with the drain electrode and directly below the drain electrode.
However, in an embodiment illustrated by Fig. 1, Yoshimochi teaches a second low thermal resistance material section (section of 22/24) in contact (electrical/thermal contact) with a drain electrode (10) and directly below the drain electrode (10) {¶0092, 0093}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura and Lee based on the further teachings of Yoshimochi – to include a second low thermal resistance material section in contact with the drain electrode and directly below the drain electrode – to electrically/thermally connect … the source electrode … to the back surface. Yoshimochi ¶0007. Moreover, all the claimed elements (e.g., low thermal resistance material section, drain electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yoshimochi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Examiner’s Note: The American Heritage College Dictionary, fourth edition, defines the fourth sense (i.e., most common usage) of “contact” to mean ‘[a] connection between two conductors that permits a flow of current or heat.”
Regarding claim 9, Yoshimochi teaches in Fig. 9 a semiconductor module comprising:
a semiconductor device (1A; ¶0119) that comprises:
a semiconductor layer (2) {¶0164};
a channel layer (4) stacked on the semiconductor layer (2) {¶0078},
wherein the channel layer (4) includes a semiconductor material (GaN) different from that (Si) of the semiconductor layer (2) {¶0078, 0183};
a buffer layer (3) between the semiconductor layer (2) and the channel layer (4) {¶0072};
a barrier layer (5) on the channel layer (4) {¶0079; barrier layer (5) made of AlGaN, same as Applicants’ barrier layer};
a recess section (41) from the barrier layer (5) to the buffer layer (3) {¶0137};
a gate electrode (11) on the barrier layer (5) {¶0074};
a source electrode (9) on the barrier layer (5) {¶0073}; and
a drain electrode (10) on the barrier layer (5), wherein the source electrode (9) and the drain electrode (10) are at positions sandwiching the gate electrode (11) {¶0073};
a low resistance material section (section of 5a) in contact with the barrier layer (5), the channel layer (4), and one of the source electrode (9) or the drain electrode (unselected alternative) {¶0136}; and
a low thermal resistance material section (section of 42/44) in contact with the channel layer (4), the buffer layer (3), and one of the source electrode (9) or the drain electrode (unselected alternative) {¶0138};
wherein the low thermal resistance material section (section of 42/44, e.g., Cu) has a thermal resistance lower than a thermal resistance of the channel layer (4, which is GaN) {¶0138 Cu has a lower thermal resistance than GaN}; and
the low thermal resistance material section (section of 42/44) is in the recess section (41) {¶0138}.
Yoshimochi does not teach the buffer layer is on a bottom surface of the recess section.
Miura teaches in Fig. 5 and paragraph [0067] a recess section (TH) from a barrier layer (BA) to a buffer layer (BU1), wherein the buffer layer (Bu1) is on a bottom surface of the recess section (TH). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor module based on the teachings of Miura – such that Yoshimochi’s recess section extends from the barrier layer to the buffer layer, and the buffer layer is on a bottom surface of the recess section – to bring the potential of the buffer layer … close to a source potential (for example, ground potential)[,] … enable[] production of a two-dimensional electron gas 2DEG2 at the interface between the [first] buffer layer …and the [second] buffer layer[, and/or achieve an] … increase in threshold voltage and improvement in normally-off characteristics. Miura [0067]. Moreover, all the claimed elements (e.g., buffer layer, bottom surface, recess section) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Miura) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Yoshimochi does not expressly teach the low resistance material section has a resistance lower than a resistance of the channel layer.
Yoshimochi characterizes section (section of 5a) as a low resistance region 5a in which Al is diffused [in GaN]. In an analogous art, Lee teaches in Fig. 2 and paragraph [0037] an AlGaN layer having a lower electrical resistance than a GaN layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor module as modified by Miura based on the teachings of Lee – such that Yoshimochi’s AlGaN low resistance material section has a lower resistance than Yoshimochi’s GaN channel layer – for reducing an electric resistance {Lee ¶0037} and the reduction of the driving voltage {Lee ¶0038}. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 10, Yoshimochi teaches in Fig. 9 an electronic apparatus comprising:
a semiconductor device (1A; ¶0119) that comprises:
a semiconductor layer (2) {¶0164};
a channel layer (4) stacked on the semiconductor layer (2) {¶0078},
wherein the channel layer (4) includes a semiconductor material (GaN) different from that (Si) of the semiconductor layer (2) {¶0078, 0183};
a buffer layer (3) between the semiconductor layer (2) and the channel layer (4) {¶0072};
a barrier layer (5) on the channel layer (4) {¶0079; barrier layer (5) made of AlGaN, same as Applicants’ barrier layer};
a recess section (41) from the barrier layer (5) to the buffer layer (3) {¶0137};
a gate electrode (11) on the barrier layer (5) {¶0074};a source electrode (9) on the barrier layer (5) {¶0073}; and
a drain electrode (10) on the barrier layer (5), wherein the source electrode (9) and the drain electrode (10) are at positions sandwiching the gate electrode (11) {¶0073};
a low resistance material section (section of 5a) in contact with the barrier layer (5), the channel layer (4), and one of the source electrode (9) or the drain electrode (unselected alternative) {¶0136}; and
a low thermal resistance material section (section of 42/44) in contact with the channel layer (4), the buffer layer (3), and one of the source electrode (9) or the drain electrode (unselected alternative) {¶0138};
wherein the low thermal resistance material section (section of 42/44, e.g., Cu) has a thermal resistance lower than a thermal resistance of the channel layer (4, which is GaN) {¶0138 Cu has a lower thermal resistance than GaN}; and
the low thermal resistance material section (section of 42/44) is in the recess section (41) {¶0138}.
Yoshimochi does not teach the buffer layer is on a bottom surface of the recess section.
In an analogous art, Miura teaches in Fig. 5 and paragraph [0067] a recess section (TH) from a barrier layer (BA) to a buffer layer (BU1), wherein the buffer layer (Bu1) is on a bottom surface of the recess section (TH). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s electronic apparatus based on the teachings of Miura – such that Yoshimochi’s recess section extends from the barrier layer to the buffer layer, and the buffer layer is on a bottom surface of the recess section – to bring the potential of the buffer layer … close to a source potential (for example, ground potential)[,] … enable[] production of a two-dimensional electron gas 2DEG2 at the interface between the [first] buffer layer …and the [second] buffer layer[, and/or achieve an] … increase in threshold voltage and improvement in normally-off characteristics. Miura [0067]. Moreover, all the claimed elements (e.g., buffer layer, bottom surface, recess section) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Miura) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Yoshimochi does not teach expressly the low resistance material section has a resistance lower than a resistance of the channel layer.
Yoshimochi characterizes section (section of 5a) as a low resistance region 5a in which Al is diffused [in GaN]. In an analogous art, Lee teaches in Fig. 2 and paragraph [0037] an AlGaN layer having a lower electrical resistance than a GaN layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s electronic apparatus as modified by Miura based on the teachings of Lee – such that Yoshimochi’s AlGaN low resistance material section has a lower resistance than Yoshimochi’s GaN channel layer – for reducing an electric resistance {Lee ¶0037} and the reduction of the driving voltage {Lee ¶0038}. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimochi in view of Miura and Lee as applied to claim 2 above, and further in view of Simin et al. (US20080203430A1).
Regarding claim 5, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 2, and Yoshimochi further teaches the low thermal resistance material section (section of 42/44) penetrates the buffer layer (3) and the channel layer (4) {¶0138}.
Yoshimochi does not teach a back barrier layer between the channel layer and the buffer layer, wherein the back barrier layer has a bandgap wider than a bandgap of the channel layer, and the low thermal resistance material section penetrates the back barrier layer.
In an analogous art, Simin teaches in Fig. 5 and paragraph [0025] a back barrier layer (18) between a channel layer (16) and a buffer layer (30), wherein the back barrier layer (18) has a bandgap wider than a bandgap of the channel layer (16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura and Lee based on the teachings of Simin – such that a back barrier layer is between the channel layer and the buffer layer, wherein the back barrier layer has a bandgap wider than a bandgap of the channel layer – so the channel layer is substantially depleted at zero gate bias. Simin ¶0012. Moreover, all the claimed elements (e.g., channel layer, buffer layer, back barrier layer, bandgap) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Simin) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. A consequence of this modification is that Yoshimochi’s low thermal resistance material section (section of 42/44) will penetrate Simin’s back barrier layer, which is disposed (in the modified structure) between Yoshimochi’s buffer layer (3) and channel layer (4).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimochi in view of Miura and Lee as applied to claim 6 above, and further in view of Nihei et al. (US20050067693A1).
Regarding claim 7, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 6, and Yoshimochi further teaches does not teach wherein the source electrode (9) includes a metal material (Cu/Ti) same as that (Cu/Ti) of the first low thermal resistance material section (section of 42/44) {¶0082, 0138}.
Yoshimochi does not teach in the embodiment illustrated by Fig. 9 the drain electrode includes a metal material same as that of the second low thermal resistance material section.
However, in an embodiment illustrated by Fig. 1, Yoshimochi teaches a drain electrode (10) includes a metal material (Cu/Ti) same as that (Cu/Ti) of a second low thermal resistance material section (section of 22/24) {¶0092, 0093}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura and Lee based on the further teachings of Yoshimochi – such that the drain electrode includes a metal material same as that of the second low thermal resistance material section – to electrically/thermally connect … the source electrode … to the back surface. Yoshimochi ¶0007. Moreover, all the claimed elements (e.g., low thermal resistance material section, metal, drain electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yoshimochi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Yoshimochi does not teach the source electrode is integral with the first low thermal resistance material section, and the drain electrode is integral with the second low thermal resistance material section.
In an analogous art, Nihei teaches in Fig. 1G and paragraph [0073] an electrode (10) is formed in a hole (9) – passing through a top surface of a semiconductor device and a channel layer (5) and down into a semiconductor substrate – so as to be directly connected to a heat conductor (4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura and Lee based on the teachings of Nihei – such that each of: (1) Yoshimochi’s second low thermal resistance material section and drain electrode are integrally formed and (2) Yoshimochi’s first low thermal resistance material section and source electrode are integrally formed – so heat generated in the HEMT becomes easy to escape to the heat conductor … and it becomes further easier to prevent the temperature increase in the HEMT. Nihei ¶0073. Moreover, all the claimed elements (e.g., source electrode, low thermal resistance material section, drain electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Nihei) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimochi in view of Miura and Lee as applied to claim 1 above, and further in view of Takeuchi et al. (US20190035922A1).
Regarding claim 8, Yoshimochi as modified by Miura and Lee teaches the semiconductor device according to claim 1, and Yoshimochi further teaches wherein the channel layer (4) includes GaN {Fig. 1; ¶0078}.
Yoshimochi does not teach the barrier layer includes Al1-x-yGaxInyN, where 0≤x<1 and 0≤y<1.
In an analogous art, Takeuchi teaches in Fig. 1 and paragraph [0065] a barrier layer (310) includes Al1-x-yGaxInyN, where 0≤x<1 and 0≤y<1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshimochi’s semiconductor device as modified by Miura and Lee based on the teachings of Takeuchi – such that the barrier layer includes Al1-x-yGaxInyN, where 0≤x<1 and 0≤y<1 – to inhibit carrier scattering caused by impurities in the channel layer. Takeuchi ¶0065. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID WARD whose telephone number is (703)756-1382. The examiner can normally be reached 6:30-3:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891