DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species E (claims 1-6, 9, 10, 13, and 15) in the reply filed on 6/16/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5, 6 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification fails to explain why the conditional expression in claim 5 is appropriate. The specification merely presents the formula without explaining its origin or applicability. Claim 6 is rejected as being dependent on claim 5.
Claims 5, 6 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 5 covers every possible coefficient, but only recites working values in claim 6. Can an appropriate coefficient be determined outside of 15-20? There is no teaching in the specification how to select the coefficient. Does the invention work for coefficients of 5, 50, 100? Accordingly, claim 5 is broader than the enabling disclosure.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2, 5, 9, 10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the opening" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation “coefficient” but does not specify what the coefficient is. Claim 5 covers any coefficient since there is no explanation how the coefficient is selected. Accordingly, the scope is uncertain. Also, regarding the terminology “potential difference”, is this: the design operating voltage, the maximum rated voltage, RMS voltage, peak voltage, transient voltage?
Claim 9 recites “the first distance provided in the first opening”. Between what two points is the “first distance” measured? Is it: the distance from the terminal to the edge of the opening? the width of the opening? the exposed conductor length? the creepage distance? Likewise, what exactly is the “second distance”? Without reference points, it is difficult to determine the metes and bounds of the claim. Also, the phrase “obtained by adding” leaves unanswered what is being added.
Claim 10 recites “directions of the lead wires are staggered” which is relative terminology that lacks an established meaning by itself. Staggered relative to what? Different angles? Different orientations? Different longitudinal positions? Alternative left and right? Offset in the X or Y direction? The term “staggered” is a relative term whose scope is unclear because the claims fails to specify the reference by which the directions are considered staggered. Also, the phrase “the first terminal includes lead wires” is unclear whether a “terminal” is intended to encompass multiple lead wires. The terminal and the wire appear to be separate elements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9, 10, 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP Publication No. 2010-027856 (Fujitani), cited by Applicant.
Fujitani discloses
1. (Original) A semiconductor device, comprising:
a chip 103;
a wiring substrate 101; and
a wire 802 connecting the chip 103 and the wiring substrate 101, wherein a first opening (close to chip) and a second opening (close to edge of substrate) to which the wire 802 is connected (to pattern 104) are formed on at least one side of the wiring substrate 101, the one side being on a surface (top) of the wiring substrate 101 on which an insulating film 106 is formed.
Fujitani discloses, to the extent taught and understood
2. (Original) The semiconductor device according to claim 1, wherein a first terminal 104 formed in the first opening (close to chip) and a second terminal 104 formed in the second opening (close to edge of substrate) are arranged at positions separated by a predetermined distance in the opening.
Fujitani discloses
3. (Original) The semiconductor device according to claim 2, wherein on a straight line on which the first terminal 104 and the second terminal 104 are arranged, a distance between the first terminal 104 and the second terminal 104 is separated by the predetermined distance except for a distance of the insulating film 106 between the first terminal 104 and the second terminal 104.
Fujitani discloses, to the extent taught and understood
9. (Original) The semiconductor device according to claim 2, wherein the predetermined distance is a distance obtained by adding a first distance provided in the first opening (close to chip) and a second distance provided in the second opening (close to edge of substrate).
Fujitani discloses, to the extent taught and understood
10. (Original) The semiconductor device according to claim 2, wherein the first terminal 104 includes lead wires, and is arranged in the first opening (close to chip) in such a manner that directions of the lead wires are staggered.
Fujitani discloses
13. (Original) The semiconductor device according to claim 2, wherein the second terminal 104 is formed as a single terminal in the second opening (close to edge of substrate).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujitani as applied to claim 2 above, and further in view of WO Publication No. 2021-140920 (Suzuki).
Fujitani fails to disclose
4. (Original) The semiconductor device according to claim 2, wherein the wire set to a low potential is connected to the first terminal, and the wire set to a high potential with respect to the low potential is connected to the second terminal.
Fujitani fails to disclose
15. (Original) The semiconductor device according to claim 1, wherein the chip is an image sensor.
Suzuki teaches
A semiconductor device comprising:
wherein the wire 55 set to a low potential (predetermined potential) is connected to the first terminal 38 (in hole H1), and the wire 54 set to a high potential (predetermined potential) with respect to the low potential (predetermined potential) is connected to the second terminal 38 (in hole H2); and
wherein the chip 1 is an image sensor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use predetermined potentials and an image sensor in Fujitani. The motivation would be to inhibit a deterioration in image quality as taught by Suzuki. Further, selecting an image sensor would be based on suitability for the intended purpose. See MPEP 2144.07.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2015/0021749 (Ohashi), 2013/0134579 (Howard), 2011/0180940 (Oikawa), CN Publication No. 116195062 (Tanaka).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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