DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1 – 5, 35 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MATSUEDA (2017/0236886).
With regard to claim 1, MATSUEDA discloses a display substrate (for example, see figs. 3, 7), comprising:
a base substrate (11), and a gate driving circuit (a scan driver 21 functioning as a gate driving circuit) and a plurality of sub-pixels (15, for example, see paragraph [0080]) arranged on the base substrate (11);
wherein the display substrate further comprises a heat dissipation hole structure (a structure comprising conductive layers 19, 342, made of a metal material and having at least some heat dissipation based on the metal material and forming in the hole, functioning as a heat dissipation hole structure; for example, see paragraph [0056]) and at least part of an orthographic projection (an orthographic projection forming in the region E) of the heat dissipation hole structure (as shown in fig. 3 below) onto the base substrate (11) is located between an orthographic projection (an orthographic projection forming in the region C) of the gate driving circuit (21) onto the base substrate (11) and an orthographic projection (an orthographic projection forming in the region F) of the sub-pixels (15, for example, see paragraph [0080]) onto the base substrate (11).
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With regard to claim 2, MATSUEDA discloses the display substrate comprises a display area (a region F) and a border area (regions D, C, fig. 2) surrounding the display area (the region F, fig. 2), the plurality of sub-pixels (15) are located in the display area (the region F), and the gate driving circuit (the scan driver 21functioning as the gate driving circuit) and the heat dissipation hole structure (19, 342) are located in the border area (regions D, C, fig. 2).
With regard to claim 3, MATSUEDA discloses the display substrate further comprises a cathode layer (a portion of the conductive layer 19 or a conductive layer 342 functioning as a cathode layer), the cathode layer (the portion of the conductive layer 19 or the conductive layer 342 functioning as a cathode layer) is located on a side of the gate driving circuit (21) facing away from the base substrate (11), and a part of the cathode layer (19) is located in the heat dissipation hole structure.
With regard to claim 4, MATSUEDA discloses the part of the cathode layer (19) located in the heat dissipation hole structure (as shown in figs. 3, 7 above) is indirectly contact with the base substrate (11).
With regard to claim 5, MATSUEDA discloses the display substrate further comprises a heat conduction pattern (a conductive layer 342 functioning as a heat conduction pattern), the heat conduction pattern (342) is located in the heat dissipation hole structure (as shown in figs. 3, 7 above), the heat conduction pattern (342) is located between the cathode layer (19) and the base substrate (11), and the heat conduction pattern (342) is in contact with the cathode layer (19) and is indirectly contact with the base substrate (11).
With regard to claim 35, MATSUEDA discloses a display device (for example, see figs. 3, 7), comprising the display substrate.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over MATSUEDA (2017/0236886) in view of Oh (7701132).
With regard to claim 6, MATSUEDA does not clearly disclose the heat conduction pattern includes at least two heat conduction sub-patterns that are stacked, one of the heat conduction sub-patterns closest to the base substrate is in contact with the base substrate, and one of the heat conduction sub-patterns farthest from the base substrate is in contact with the cathode layer.
However, Oh discloses the heat conduction pattern (a conductive line 273 having some heat dissipation, functioning as the heat conduction pattern) includes at least two heat conduction sub-patterns (371, 347) that are stacked, one (347) of the heat conduction sub-patterns (371, 347) closest to the base substrate (300) is in contact with the base substrate (300), and one (371) of the heat conduction sub-patterns (371, 347) farthest from the base substrate (300) is in contact with the cathode layer (390). (for example, see fig. 2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MATSUEDA’s device to have the heat conduction pattern includes at least two heat conduction sub-patterns that are stacked, one of the heat conduction sub-patterns closest to the base substrate is in contact with the base substrate, and one of the heat conduction sub-patterns farthest from the base substrate is in contact with the cathode layer as taught by Jeon et al. in order to enhance a high heat dissipation efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
6. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over MATSUEDA (2017/0236886) in view of Jeon et al. (11844243).
With regard to claim 9, MATSUEDA discloses a buffer layer (a layer 42 functioning as a buffer layer), an interlayer insulating layer (42), a passivation layer (an inorganic layer 44, inherently made of silicon oxide or silicon nitride material, functioning as a passivation layer), an organic insulating layer (45) and a pixel definition layer (46) that are stacked and arranged on the base substrate (11) in sequence in a direction away from the base substrate (11).
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MATSUEDA does not disclose the heat dissipation hole structure penetrates through the buffer layer, the interlayer insulating layer, the passivation layer, the organic insulating layer and the pixel definition layer
However, Jeon et al. disclose the heat dissipation hole structure (a structure including a conductive layer 223 functioning as the heat dissipation hole structure) penetrates through the buffer layer (201), the interlayer insulating layer (203, 205), the passivation layer (an inorganic layer 207, inherently made of silicon oxide or silicon nitride material, functioning as a passivation layer), the organic insulating layer (209) and the pixel definition layer (215).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MATSUEDA’s device to have the heat dissipation hole structure penetrates through the buffer layer, the interlayer insulating layer, the passivation layer, the organic insulating layer and the pixel definition layer as taught by Jeon et al. in order to enhance a high heat dissipation efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 10, MATSUEDA does not disclose a metal encapsulation layer, wherein the metal encapsulation layer is located on a side of the cathode layer facing away from the base substrate, and a part of the metal encapsulation layer is located in the heat dissipation hole structure.
However, Jeon et al. disclose the heat dissipation hole structure (a structure including a conductive layer 223 functioning as the heat dissipation hole structure) penetrates through the buffer layer (201), the interlayer insulating layer (203, 205), the passivation layer (an inorganic layer 207, inherently made of silicon oxide or silicon nitride material, functioning as a passivation layer), the organic insulating layer (209) and the pixel definition layer (215). a metal encapsulation layer (a cap layer 230 having a lithium material functioning as a metal encapsulation layer; for example, see column 15, lines 5, 6), wherein the metal encapsulation layer (230) is located on a side of the cathode layer (223) facing away from the base substrate (100), and a part of the metal encapsulation layer (230) is located in the heat dissipation hole structure (a structure including a conductive layer 223 functioning as the heat dissipation hole structure).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the MATSUEDA’s device to have a metal encapsulation layer, wherein the metal encapsulation layer is located on a side of the cathode layer facing away from the base substrate, and a part of the metal encapsulation layer is located in the heat dissipation hole structure as taught by Jeon et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
7. Claims 11, 13, 16, 18, 21, 22, 23, 25, 28, 31, 32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11, 13, 16, 18, 21, 22, 23, 25, 28 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a first low-level signal line and a second low-level signal line, the first low-level signal line comprises at least a portion extending along a first direction, the second low-level signal line comprises at least a portion extending along the first direction, and an orthographic projection of the second low-level signal line onto the base substrate is located between the display area and an orthographic projection of the first low-level signal line onto the base substrate; the heat dissipation hole structure comprises a plurality of first heat dissipation holes, and at least part of an orthographic projection of the first heat dissipation hole onto the base substrate is located between the orthographic projection of the gate driving circuit onto the base substrate and the orthographic projection of the first low-level signal line onto the base substrate; wherein the display substrate further comprises a plurality of first signal transmission lines, a plurality of second signal transmission lines and a plurality of first scanning lines, the first signal transmission line comprises at least a portion extending along a second direction, the second signal transmission line comprises at least a portion extending along the second direction, the first scanning line comprises at least a portion extending along the second direction, and the second direction intersects with the first direction; the first signal transmission line is coupled to a corresponding one of the gate driving circuit and the first low-level signal line, and the second signal transmission line is coupled to a corresponding one of the gate driving circuit and a corresponding one of the first scanning lines; the orthographic projection of the first heat dissipation hole onto the base substrate is located between orthographic projections of one of the first signal transmission lines and one of the second signal transmission lines that are adjacent onto the base substrate as recited in claim 11,
Claim 31 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the gate driving circuit comprises a first output transistor and a first capacitor, a first plate of the first capacitor is coupled to a gate electrode of the first output transistor, and a second plate of the first capacitor is coupled to a second electrode of the first output transistor; the heat dissipation hole structure comprises a plurality of sixth heat dissipation holes, and the sixth heat dissipation hole penetrates through the first plate and the second plate as recited in claim 31.
Claim 32 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the gate driving circuit comprises a second output transistor and a second capacitor, a third plate of the second capacitor is coupled to a gate electrode of the second output transistor, and a fourth plate of the second capacitor is coupled to a second electrode of the second output transistor; the heat dissipation hole structure comprises a plurality of seventh heat dissipation holes, and the seventh heat dissipation hole penetrates through the third plate and the fourth plate; wherein the gate driving circuit comprises a first output transistor and a first capacitor, a first plate of the first capacitor is coupled to a gate electrode of the first output transistor, and a second plate of the first capacitor is coupled to a second electrode of the first output transistor; a first boundary of the cathode layer is between an orthographic projection of the first plate onto the base substrate and an orthographic projection of the third plate onto the base substrate; and/or wherein an orthographic projection of the first capacitor onto the base substrate and an orthographic projection of the second capacitor onto the base substrate are located between an orthographic projection of the first output transistor onto the base substrate and an orthographic projection of the second output transistor onto the base substrate as recited in claim 32.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812