DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4-9 objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim should refer to other claims in the alternative only, and/or, cannot depend from any other multiple dependent claim. See MPEP § 608.01(n). Accordingly, the claims 4-9 not been further treated on the merits.
Claim 3 objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim should refer to other claims in the alternative only. See MPEP § 608.01(n). Accordingly, the claim 3 not been further treated on the merits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuramata et al (US 2020/0168460) in view of Brailove et al (US 20100317140).
Kuramata et al teaches a single crystal Ga2O3 based substrate 12 ([0006]), bonding a polycrystalline Si substrate 11; single crystal Ga2O3-based substrate 10 alone is cleaved and broken along a cleavage plane such as a (100) plane or a (001) plane; a hydrogen ion implanted layer 12a is formed in the single crystal Ga2O3-based substrate 12 by implanting hydrogen ions to a portion with a predetermined depth from the bonding surface; a layer split from the single crystal Ga2O3-based substrate 12 at the hydrogen ion implanted layer 12a serving as a splitting plane is to be the single crystal Ga2O3-based substrate 10 of the semiconductor substrate 1; with a heat treatment at not less than 800°C and not more than 1100°C, it is possible to break the single crystal Ga2O3-based substrate 12 at the hydrogen ion implanted layer 12a. ([0020]-[0052]; Fig 2A-2E). Kuramata et al also teaches the process shown in FIGS. 2A to 2E is repeated, while each time using the portion of the single crystal Ga2O3-based substrate 12 separated from the polycrystalline substrate 11 as the single crystal Ga2O3-based substrate 12 shown in FIG. 2A to form plural single crystal Ga2O3 based substrates 10 of the semiconductor substrates 1 from one single crystal Ga2O3-based substrate 12 ([0052]).
Kuramata et al does not explicitly teach implanting ions at a temperature below 500° C., making an ion beam strike along a non-parallel direction to the referred cleavage plane, with an energy in the range of 10-4000 keV, a flux in the range of 1 x1012-1 x1014 ions/ cm2s and a fluence in the range of 1 x1013-1 x1016ions/ cm2
In a method of separating a thin film from a bulk substrate, Brailove et al teaches performing a controlled cleaving process along a cleave region formed by particles implanted from the beam (abstract; [0129], [0154]-[0156]). Brailove et al teaches variation in dosage may be accomplished either by controlling the dwell time of the beam in a particular region, by controlling the number of times a particular region is exposed to the beam, or by some combination of these two approaches. Brailove et al teaches an explicit embodiment, a beam of 20 mA of H+ ions may provide a flux of 1.25x1017H atom/(cm2 sec), with a minimum dwell time of 200 ps, resulting from a scan speed of 2.5 km/sec (corresponding to a scan frequency of 1.25 KHz within a 1 meter tray width using a 5 cm beam diameter), resulting in a per-pass minimum dose of 2.5 x1013 H atom/cm2. ([0156]). Brailove et al teaches the implantation process is performed using a specific set of conditions, including an implantation dose (fluence) ranges of hydrogen from about 1 x1015 to about 1 x1016 atoms/cm2, and preferably the dose of implanted hydrogen is less than about 8 x1016 atoms/cm2; implantation energy ranges from about 1 MeV and greater to about 2 MeV or even 5 MeV and greater, for the formation of thick films useful for photovoltaic applications; implantation temperature may between about 100-250°C, and is preferably less than about 400°C to prevent a possibility of hydrogen ions from diffusing out of the implanted wafer, and the hydrogen ions can be selectively introduced into the wafer to the selected depth at an accuracy of about .+-.0.03 to .+-.1.5 microns ([0098]). Brailove et al teaches the method can be applied successively to cleaving multiple free-standing films wherein, the method can be repeated to successively cleave slices according to a specific embodiment ([0225]).
Brailove et al clearly teaches the energy, a flux and a fluence of the ion implantation process are result effective variables that depth of the cleave region. Therefore, It would have been obvious to one of ordinary skill in the art at the time of filing to modify Kuramata et al by implanting ions at a temperature below 500° C to prevent diffusion, making an ion beam strike along a non-parallel direction to the referred cleavage plane, with an energy in the range of 10-4000 keV, a flux in the range of 1 x1012-1 x1014 ions/ cm2s and a fluence in the range of 1 x1013-1 x1016ions/ cm2, by conducting routine experimentation of result effective variables, as taught by Brailove et al, to form a cleave region at a desired depth to for Ga2O3 layer having a desired thickness.
Referring to claim 2, the combination of Kuramata et al and Brailove et al teaches the process shown in FIGS. 2A to 2E is repeated, while each time using the portion of the single crystal Ga2O3-based substrate 12 separated from the polycrystalline substrate 11 as the single crystal Ga2O3-based substrate 12 shown in FIG. 2A to form plural single crystal Ga2O3 based substrates 10 of the semiconductor substrates 1 from one single crystal Ga2O3-based substrate 12 (Kuramata [0052]).
Referring to claim 3, the combination of Kuramata et al and Brailove et al teaches after implantation (step a) and before annealing (step b), forming an amorphous layer 12b on the Ga2O3 and 11b on the substrate 11 (stable substrate), bonding and then breaking the single crystal at the hydrogen ion implanted layer 12a (Kuramata [0040]-[0052], Fig 2A-2E), which clearly suggests an intermediate step. It is noted that claim 3 is interpreted as depending from claim 1 to expediate examination.
Referring to claim 4, the combination of Kuramata et al and Brailove et al teaches a polycrystalline Si substrate (Kuramata [0028]). Furthermore, the selection of a known material based on its suitability for its intended purpose is prima facie obvious (MPEP 2144.07).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuramata et al (US 2020/0168460) in view of Brailove et al (US 20100317140), as applied to claims 1-4 above, and further in view of Morimoto et al (US 2008/0124897).
The combination of Kuramata et al and Brailove et al teaches all of the limitations of claim 5, as discussed above, except a step prior to step a), wherein at least one additional conductive, semiconducting or insulating layer is deposited on the surface of the monocrystal of Ga2O3. It is noted that claim 5 is interpreted as depending from claim 1 to expediate examination.
In a method of smart cutting a substrate, Morimoto et al teaches a smart cut method comprising the steps of subjecting at least one surface of a wafer 1 for active layer to a thermal oxidation to form an insulating film 3 (silicon oxide film) on such a surface (FIG. 2(a)), implanting ions of a light element such as hydrogen or helium to a predetermined depth position of the wafer 1 for active layer (FIG. 2(b)), bonding the wafer 1 for active layer to a wafer for support substrate (FIGS. 2(c) and (d)), and then exfoliating the ion implanted portion through a heat treatment (FIG. 2(e)) ([0019]-[0022]; Fig 1-2; Abstract).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kuramata et al and Brailove et al by forming an insulating layer is deposited on the surface of the monocrystal of Ga2O3 prior to implanting ion, as taught by Morimoto et al, to form a buried oxide layer for device manufacturing (Morimoto [0005]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuramata et al (US 2020/0168460) in view of Brailove et al (US 20100317140), as applied to claims 1-4 above, and further in view of Schulze et al (US 2018/0082898).
The combination of Kuramata et al and Brailove et al teaches all of the limitations of claim 6, as discussed above, except the ion beam is selected from the group of ions comprising Chromium (Cr), Iron (Fe), Nitrogen (N), Carbon (C) and Tungsten (W) ions. The combination of Kuramata et al and Brailove et al teaches implanting H ions (Kuramata [0042]). It is noted that claim 6 is interpreted as depending from claim 1 to expediate examination.
In a method of splitting a semiconductor wafer, Schulze et al teaches implanting hydrogen atoms or ions and nitrogen atoms or ions in a splitting region, and incorporating of the nitrogen atoms may enable splitting of the semiconductor wafer at a reduced implantation dose of hydrogen atoms, and hydrogen and nitrogen are incorporated in the splitting region to lattice vacancies required for the creation of cavities ([0013]-[0038]). Schulze et al teaches the semiconductor wafer may be split at least by heating the semiconductor wafer to a temperature higher than 700° C so that the semiconductor material of the semiconductor wafer breaks apart due to bubbles growing together within the implant zone ([0038]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kuramata et al and Brailove et al teaches implanting N ions, as taught by Schulze et al, to reduced implantation dose of hydrogen atoms and combining equivalents known for the same purpose is prima facie obvious (MPEP 2144.06 I).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuramata et al (US 2020/0168460) in view of Brailove et al (US 20100317140), as applied to claims 1-4 above, and further in view of Yamazaki et al (US 2010/0248444) and Kirscht et al (US 2008/0157241).
The combination of Kuramata et al and Brailove et al teaches all of the limitations of claim 7, as discussed above, except the thermal treatment of step b) is performed at an annealing temperature of 700°C for 30 second and with a heating rate of 1°C per second. It is noted that claim 7 is interpreted as depending from claim 1 to expediate examination.
In a method of wafer separation, Yamazaki et al teaches a single crystal semiconductor substrate 101 can be separated along the fragile layer 103 because microvoids are formed in the fragile layer 103 change in volume due to temperature increase caused by the heat treatment, and a crack is generated in the fragile layer 103, wherein an RTA apparatus is used, the single crystal semiconductor substrate 101 can be separated at a heating temperature of 550°C to 730°C. inclusive, within a process time of 0.5 minutes to 60 minutes inclusive ([0092]). Overlapping ranges are prima facie obvious (MPEP 2144.05)
In a method of RTA, Kirscht et al teaches annealing a semiconductor wafer using rapid thermal annealing (RTA) with ramp-up rates in the range 1-80 K/sec and ramp-down rates in the range 1-80 K/sec in the temperature range 400 and 1300°C (claim 15).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kuramata et al and Brailove et al by annealing temperature of 700°C for 30 second, as taught by Yamazaki et al using RTA, and RTA with a heating rate of 1°C per second, as taught by Kirscht et al, which is within the conventionally known heating ramp rates, to improve productivity.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuramata et al (US 2020/0168460) in view of Brailove et al (US 20100317140), as applied to claims 1-4 above, and further in view of Shen et al (US 2012/0196047).
The combination of Kuramata et al and Brailove et al teaches all of the limitations of claim 8, as discussed above, except the ion beam implantation is performed in stationary mode. It is noted that claims 8-9 are interpreted as depending from claim 1 to expediate examination.
In a method of ion beam implantation, Shen et al teaches an ion implant beam may be kept stationary while the work piece is moved, the ion implant beam may be moved while the work piece is kept stationary, or a combination of moving the work piece and moving the ion implant beam may be used to scan (sweeping) the work piece (abstract; [0061]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kuramata et al and Brailove et al by performing the ion beam implantation is in stationary mode, as taught by Shen et al, because providing a stationary beam with a moving substrate is conventionally known to be used to implant ions across a substrate.
Referring to claim 9, the combination of Kuramata et al and Brailove et al teaches all of the limitations of claim 9, as discussed above, except the ion beam implantation is performed in sweeping mode. It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Kuramata et al and Brailove et al by performing the ion beam implantation is in sweeping mode, as taught by Shen et al, because sweeping (scanning) beam with a stationary substrate is conventionally known to be used to implant ions across a substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ou et al (CN 111312852A), an English computer translation (CT) is provided, teaches providing gallium oxide single crystal wafer; performing ion implantation on surface of the gallium oxide single crystal wafer to form a defect layer at a predetermined depth of the gallium oxide single crystal wafer; bonding the surface of the gallium oxide single crystal wafer to the surface of a silicon layer to prepare a composite structure; annealing to peel off the gallium oxide single crystal wafer along the defect layer to obtain a composite structure, which includes a bottom silicon, an insulating oxide layer, a top silicon and gallium oxide thin film stacked in sequence, wherein the ion implantation includes one or a combination of H ion implantation and He ion implantation; the ion implantation energy is 65 KeV to 150 KeV, the dose is 5 ×1017 ions/cm2 to 5 × 1018 ions/cm2, and the temperature is 100 °C to 200 °C (Fig 2-7; CT [0010]-[0021], [0060]-[0070]). Overlapping ranges are prima facie obvious (MPEP 2144.05). Ou et al also teaches depth of the defect layer 110 is determined by the energy of ion implantation, and whether the defect density required for separation can be formed is determined by the dose of ion implantation (CT [0067]), which clearly suggest energy and dose of ion implantation are result effective variables. Ou et al also teaches an explicit example of ion implantation energy was 120 KeV, the implantation dose was 5 × 10 ions/cm², and the implantation temperature was 120 °C (CT [0090]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW J SONG whose telephone number is (571)272-1468. The examiner can normally be reached Monday-Friday 10AM-6PM.
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/Primary Examiner, Art Unit 1714
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