Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
“Group I” has been elected without traverse. Currently, claims 1-11 and 23-24 are pending, and claims 12-22 have been withdrawn from further consideration.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6-11 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (Pub. No. US 2018/0096896 A1) in view of Xie et al. (Pub. No. US 2022/0199785 A1, herein Xie).
Regarding claims 1 and 23, Zhu discloses a vertical MOSFET device, comprising: a substrate 1001 (Zhu: paragraph [0028]); an active region comprising a first source/drain layer 1003, a channel layer 1005 and a second source/drain layer 1007 vertically stacked on the substrate in sequence, wherein an outer periphery of the channel layer 1005 is recessed with respect to an outer periphery of the first source/drain layer and an outer periphery of the second source/drain layer (Zhu: Fig. 24 and paragraph [0028]); and a gate stack 1029-1031 formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the second and first source/drain (Zhu: Fig. 24 and paragraph [0059]).
Zhu does not specifically show a spacing layer comprising an upper spacing layer and a lower spacing layer, wherein the upper spacing layer is formed on a lower surface of the second source/drain layer exposed by a recess of the channel layer, the lower spacing layer is formed on an upper surface of the first source/drain layer exposed by the recess of the channel layer, and the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.
In the same field of endeavor, Xie teaches disclose a spacing layer comprising an upper spacing layer 126 and a lower spacing layer 118, wherein the upper spacing layer is formed on a lower surface of the second source/drain layer 202 exposed by a recess of the channel layer 112, the lower spacing layer is formed on an upper surface of the first source/drain layer 106 exposed by the recess of the channel layer, and the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack 120 formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer (Xie: Figs. 10A-10B and paragraphs [0036], [0053]) to achieve the desired contact dimensions and ensure good contact landing (Xie: paragraphs [0003]-[0006]).
Therefore, given the teachings of Xie, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Zhu in view of Xie by employing the spacing layers.
Regarding claim 2, Zhu in view of Xie teaches the vertical MOSFET device according to claim 1, wherein each of the first source/drain layer, the channel layer and the second source/drain layer has a thickness of 10 nm to 100 nm (Zhu: paragraphs [0029]-[0030]).
Regarding claim 3, Zhu in view of Xie teaches the vertical MOSFET device according to claim 1, wherein the gate stack comprises a gate dielectric layer 1029 and a gate conductor layer 1031, and the gate conductor layer comprises a work function adjusting metal and a gate conductive metal disposed on the work function adjusting metal (Zhu: paragraph [0059]).
Regarding claim 4, Zhu in view of Xie teaches the vertical MOSFET device according to claim 1, further comprising a first dielectric layer 1027 disposed on the first source/drain layer 1003 (Zhu: paragraph [0057]).
Regarding claim 6, Zhu in view of Xie teaches the vertical MOSFET device according to claim 4, wherein the gate dielectric layer and the gate conductor layer are further partially disposed on the first dielectric layer (Zhu: Fig. 24 and paragraph [0057]).
Regarding claim 7, Zhu in view of Xie teaches the vertical MOSFET device according to claim 6, wherein the gate conductor layer is exposed at a portion outside the groove space, and is exposed at another portion outside the groove space (Zhu: Fig. 24 and paragraphs [0057]-[0058]).
Regarding claim 8, Zhu in view of Xie teaches the vertical MOSFET device according to claim 4, further comprising: a second dielectric layer 1033 disposed on an upper surface of the gate dielectric layer and an upper surface of the gate conductor layer, wherein the second dielectric layer has a same material as the first dielectric layer (Zhu: Fig. 24 and paragraph [0064]).
Regarding claim 9, Zhu in view of Xie teaches the vertical MOSFET device according to claim 1, wherein the spacing layer is aligned with a lateral outer edge of the first source/drain layer and a lateral outer edge of the second source/drain layer (Xie: Figs. 10A-10B and paragraphs [0036], [0053]).
Regarding claim 10, Zhu in view of Xie teaches the vertical MOSFET device of according to claim 1, further comprising: metal contact portions 1051 respectively embedded in the first source/drain layer, the gate conductor layer, and the second source/drain layer (Zhu: Fig. 24 and paragraphs [0073]-[0074]).
Regarding claim 11, Zhu in view of Xie teaches the vertical MOSFET device according to claim 1, wherein the substrate is a crystal plane, and the channel layer is a crystal plane (Zhu: Fig. 24 and paragraphs [0016], [0028], and Xie: paragraphs [0038], [0040], [0053]).
Regarding claim 24, Zhu in view of Xie teaches the electronic device according to claim 23, wherein the electronic device comprises a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a portable power source (Zhu: paragraph [0077]).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
With respect to claim 5, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein a height of the first dielectric layer is higher than a bottom surface of the channel layer and lower than a top surface of the lower spacing layer immediately adjacent the bottom surface of the channel layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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January 30, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813