DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim 1 filed on 01/26/2026 has been fully considered for examination based on their merits. The original claim(s) 2-7 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 4-12, filed 01/26/2026, with respect to the rejection(s) of claim(s) 1-7 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KIM.
Regarding Independent Claim 1. The Applicant argues (see Remarks, page 7) that neither NAKANISHI nor LEE teaches the amended limitations to claim 1, now recites, “a three-dimensional flash memory…remaining areas are recessed, and… wherein protruding areas…memory cells are formed of a same material as recessed regions of the channel layer.” The Examiner agrees with the arguments are persuasive, and therefore the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KIM. For instance, KIM teaches a three-dimensional flash memory (Figs. 1-2, non-volatile memory device, [0012-0013], [0027]) having a structure (three-dimensional structure, memory cell transistor, MCs, [0026]) with an extended memory cell area (Fig. 4, 132, extended portions, [0042]), the three-dimensional flash memory (three-dimensional structure, memory cell transistor, MCs, [0026]) comprising: wherein the at least one memory cell string has a structure in which areas (annotated Figure 10) corresponding to the plurality of memory cells (m memory cells, [0027]) protrude in the horizontal direction (annotated Figure 10) and in which remaining areas are recessed (annotated Figure 10), and wherein protruding areas of the channel layer (annotated Figure 10, 146) corresponding to the plurality of memory cells (m memory cells, [0027]) are formed of a same material (Fig. 10, 146, channel semiconductor layers may be made of a polycrystalline semiconductor, [0051]) and are formed through a same manufacturing process (chemical vapor deposition process, [0051]) as recessed regions (annotated Figure 10, 146) of the channel layer (Fig. 10, 146).
Applicant further argues (see Remarks, pages 7-10) that, in contrast to NAKANISHI, the instant application, wherein protruding areas of the channel layer corresponding to the plurality of memory cells are formed through “a same manufacturing process” as recessed regions of the channel layer. The Examiner respectfully disagrees that the arguments are not persuasive since the instant application, wherein the claims are drawn towards a product or “device” and not related to “method of manufacturing the device.” Additionally, the KIM art mentioned above, now reads the claim limitation that the chemical vapor deposition as a single manufacturing method was used in fabricating the protruding areas of the channel layer as the recessed regions [0051].
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Regarding Claim(s) 2-7. The dependent claims 2-7 similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toshiro Nakanishi et al, (hereinafter NAKANISHI), US 20110294290 A1 (prior art used in the previous OA), in view of Young-Hoo Kim et al, (hereinafter KIM), US 20100181610A1.
Regarding Claim 1, NAKANISHI teaches in Figures 1-2, a three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]) having a structure (Fig. 2, 130, thin layer structure, [0057]) with an extended memory cell area (Fig. 1, MCT, memory cell transistor, [0050]; annotated Figure 1), the three-dimensional flash memory comprising:
a plurality of word lines (Figs. 1/2, WL0-WL3, [0050]; horizontal structures, 130 in contact with the vertical structures, AP (active pillar) may correspond to the plurality of word lines, WL0-WL3; annotated Figure 2) stacked in a vertical direction (Fig. 2, AP, active pillar in Y-direction) while extending on a substrate (Fig. 2, 100) in a horizontal direction (Fig. 2, 130, thin layer structure in X-direction); and
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at least one memory cell string (Figs. 2/3, AP [162, first semiconductor pattern, 165, second semiconductor pattern] and 150, data storage layer) passing through the plurality of word lines (Figs. 2/3, 123 to 126 (conductive patterns), [0059]; annotated Figure 2) and extending on the substrate (Fig. 2, 100) in the vertical direction (Fig. 2, Y-direction), the at least one memory cell string constituting a plurality of memory cells corresponding to the plurality of word lines (annotated Figure 2) while including a channel layer (Figs. 3, 162, first semiconductor pattern, [0074]) extending in the vertical direction (Fig. 2, Y-direction) and a charge storage layer (Fig. 3, 150, data storage pattern, [0082]) formed to surround the channel layer (annotated Figure 3),
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NAKANISHI does not explicitly disclose a three-dimensional flash memory having a structure with an extended memory cell area, the three-dimensional flash memory comprising: wherein the at least one memory cell string has a structure in which areas corresponding to the plurality of memory cells protrude in the horizontal direction and in which remaining areas are recessed, and wherein protruding areas of the channel layer corresponding to the plurality of memory cells are formed of a same material and are formed through a same manufacturing process as recessed regions of the channel layer.
KIM teaches a three-dimensional flash memory (Figs. 1-2, non-volatile memory device, [0012-0013], [0027]) having a structure (three-dimensional structure, memory cell transistor, MCs, [0026]) with an extended memory cell area (Fig. 4, 132, extended portions, [0042]), the three-dimensional flash memory (three-dimensional structure, memory cell transistor, MCs, [0026]) comprising: wherein the at least one memory cell string has a structure in which areas (annotated Figure 10) corresponding to the plurality of memory cells (m memory cells, [0027]) protrude in the horizontal direction (annotated Figure 10) and in which remaining areas are recessed (annotated Figure 10), and wherein protruding areas of the channel layer (annotated Figure 10, 146) corresponding to the plurality of memory cells (m memory cells, [0027]) are formed of a same material (Fig. 10, 146, channel semiconductor layers may be made of a polycrystalline semiconductor, [0051]) and are formed through a same manufacturing process (chemical vapor deposition process, [0051]) as recessed regions (annotated Figure 10, 146) of the channel layer (Fig. 10, 146).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified NAKANISHI to incorporate the teachings of KIM, such that a three-dimensional flash memory having a structure with an extended memory cell area, the three-dimensional flash memory comprising: wherein the at least one memory cell string has a structure in which areas corresponding to the plurality of memory cells protrude in the horizontal direction and in which remaining areas are recessed, and wherein protruding areas of the channel layer corresponding to the plurality of memory cells are formed of a same material and are formed through a same manufacturing process as recessed regions of the channel layer. The above architecture thus enable the NAND-type flash memory devices with three-dimensional structure having high integration and fast update speed used efficiently in memory cell transistors for device applications in digital camera, and an MP3 player (KIM, [0004-0006]).
Regarding Claim 2, NAKANISHI as modified by KIM teaches the three-dimensional flash memory of claim 1.
NAKANISHI further teaches in Figures 1-2, the three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]), wherein the at least one memory cell string (Figs. 2/3, AP [162, first semiconductor pattern, 165, second semiconductor pattern] and 150, data storage layer) has a structure (Figs. 2/13, 130, thin layer structure, [0057]) in which areas of the channel layer (Figs. 2/13, 162, first semiconductor pattern in vertical direction; conductive patterns in horizontal direction, 121 to 128 functions as a channel region, [0070]), which correspond to the plurality of memory cells (annotated Figure 13), and areas of the charge storage layer (Figs. 2/13, 150, data storage pattern, [0082]), which correspond to the plurality of memory cells, protrude (annotated Figure 13; [0069]).
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Regarding Claim 3 NAKANISHI as modified by KIM teaches the three-dimensional flash memory of claim 2.
NAKANISHI further teaches in Figures 1-2, the three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]), wherein the at least one memory cell string (Figs. 2/3, AP [162, first semiconductor pattern, 165, second semiconductor pattern] and 150, data storage layer) has a structure (Figs. 2/13, 130, thin layer structure, [0057]) in which remaining areas of the charge storage layer (Figs. 2/13, 150, data storage pattern, [0082]) other than the areas corresponding to the plurality of memory cells (Fig. 13, 111-119, interlayer dielectric patterns, [0057], annotated Figure 13) are recessed (Figs. 8/9/14, 140/142/141a, first penetration region/ first recess region, [0094-0107], [0128-0129])
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Regarding Claim 4, NAKANISHI as modified by KIM teaches the three-dimensional flash memory of claim 3.
NAKANISHI further teaches in Figures 1-2, the three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]), wherein the areas of the charge storage layer (Figs. 2/13, 150, data storage pattern, [0082]), which correspond to the plurality of memory cells (annotated Figure 13), are connected to each other by the remaining areas of the charge storage layer (annotated Figure 13).
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Regarding Claim 5, NAKANISHI as modified by KIM teaches the three-dimensional flash memory of claim 3.
NAKANISHI further teaches in Figures 1-2, the three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]), wherein the areas of the channel layer (Figs. 2/13, 162, first semiconductor pattern in vertical direction; conductive patterns in horizontal direction, 121 to 128 functions as a channel region, [0070]), which correspond to the plurality of memory cells (annotated Figure 13), are areas of the channel layer, which correspond to the plurality of word lines (Figs. 2/3, 123 to 128 (conductive patterns), [0059]), and
the areas of the charge storage layer (Figs. 2/13, 150, data storage pattern, [0082]), which correspond to the plurality of memory cells (annotated Figure 13), are areas of the charge storage layer, which correspond to the plurality of word lines (Figs. 2/3, 123 to 128 (conductive patterns), [0059]).
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Regarding Claim 6, NAKANISHI as modified by KIM teaches the three-dimensional flash memory of claim 5.
NAKANISHI further teaches in Figures 1-2, the three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]), wherein the remaining areas of the channel layer (Figs. 2/13, 162, first semiconductor pattern in vertical direction; conductive patterns in horizontal direction, 121 to 128 functions as a channel region, [0070]) are areas of the channel layer, which correspond to a plurality of interlayer insulating layers (Figs. 2/13, 111 to 119, interlayer dielectrics, [0107]) interposed between the plurality of word lines (Figs. 2/3, 123 to 128 (conductive patterns), [0059]), and
the remaining areas of the charge storage layer (Figs. 2/13, 150, data storage pattern, [0082]) are areas of the charge storage layer, which correspond to the plurality of interlayer insulating layers (Figs. 2/13, 111 to 119, interlayer dielectrics, [0107]).
Regarding Claim 7, NAKANISHI as modified by KIM teaches the three-dimensional flash memory of claim 6.
NAKANISHI further teaches in Figures 1-2, the three-dimensional flash memory (Fig. 2, three-dimensional semiconductor memory device, [0031]), wherein a cross-sectional size of areas of the at least one memory cell string (annotated Figure 13), which correspond to the plurality of word lines (Figs. 2/3, 123 to 128 (conductive patterns); annotated Figure 13, [0059]), is greater than a cross-sectional size of areas of the at least one memory cell string (Figs. 2/3, AP [162, first semiconductor pattern, 165, second semiconductor pattern] and 150, data storage layer), which correspond to the plurality of interlayer insulating layers (Figs. 2/13, 111 to 119, interlayer dielectrics, [0107]).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160225786 A1 – Figure 14B
STATEMENT OF RELEVANCE – Protrusion towards active pillar, 130 may include channel regions for the MOS transistors of the strings.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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