DETAILED ACTION
This Office action is in response to the amendment filed 30 December 2025. By this amendment, claims 16-17 are amended, claims 19-20 are new. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 30 December 2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues (1) the modification of Nakamura as set forth in the rejection is “physically incompatible with Nakamura’s principle of operation” because “making sheet 3 smaller than substrate 7 necessarily means base 2 would fail to support the periphery of substrate 7” and “[i]f the rigid base 2 is smaller than the substrate 7 it is meant to reinforce, the warpage suppression effect - the primary objective of Nakamura - would be lost or significantly reduced at the edges.” (Remarks, pp. 6-7.) Applicant further argues (2) base 2 remains a part of the final product of Nakamura, thus if the base were smaller than the substrate, the individual pieces cut from the periphery of the substrate would suffer from uneven coverage and lack the necessary reinforcement provided by the base. (Remarks, p. 7.)
Examiner respectfully disagrees. As an initial matter, the rejection of claim 1 does not expressly call for base 2 of Nakamura to be smaller in size than the substrate 7, nor does the rejection reference base 2 to disclose any of the recited elements; rather, the proposed modification is regarding the size of the thermosetting sheet 3 in relation to the substrate 7. Examiner notes that in the discussion of suppressing warpage, Nakamura contemplates the thickness of base 2, balancing the rigidity associated with increased thickness (thus inhibiting deformation) of the base with the desire to minimize resultant electronic component thickness. (Nakamura, ¶¶ 0043-44.) As to (1), the proposed modification would not necessarily require base 2 to be smaller, and further, even if base 2 were smaller than substrate 7, Nakamura explicitly discloses base 2 having sufficient rigidity to suppress warpage (see, e.g., Nakamura, ¶¶ 0025, 43). Since the proposed modification does not require nor suggest base 2 be smaller, (2) is also found unpersuasive. One of ordinary skill in the art would have been motivated to provide the dimensional relationship as recited in claim 1, as disclosed by Toyoda (see rejection of claim 1 below), for the purpose of preventing leakage of the melted sheet and avoiding filling failure of an underfill (Toyoda, ¶ 0039). Thus, the prior art reads on the claims as currently drafted.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 19 recites “after step (c) the release treatment film is peeled off” in line 3; this subject matter was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventors had possession of the claimed invention. Formation of the thermosetting sheet on a release treatment film is disclosed in at least ¶ 0081 of the instant specification, however a disclosure for the recited limitation above could not be located.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0141268 A1 to Nakamura et al. (hereinafter “Nakamura”) in view of US 2012/0055015 A1 to Toyoda et al. (hereinafter “Toyoda”).
Regarding independent claim 1, Nakamura (Fig. 1) discloses a method for sealing an electronic component mounting substrate, the method comprising steps of:
(a) preparing an electronic component mounting substrate 7/5 (¶ 0032) including a substrate 7 (¶ 0032) and a plurality of electronic components 5 (¶ 0032) mounted on the substrate and having a space between an electronic component 5 and the substrate 7 (Fig. 1A);
(b) placing a thermosetting sheet 3 (¶ 0037) on the electronic component mounting substrate 7/5 so as to be in contact with the electronic components 5 (Fig. 1A-1B); and
(c) heat-molding the placed thermosetting sheet 3, to allow a melt of the thermosetting sheet to fill the space between the electronic component 5 and the substrate 7 and be cured (¶¶ 0100, 0105).
Nakamura does not expressly disclose: the thermosetting sheet to be smaller in size than the substrate, wherein when a distance between a center of the substrate and an optional point P on a frame line that surrounds all of the plurality of electronic components and minimizes a surrounded area is denoted by Lp, a distance Lq between the center of the substrate and a point Q at which a straight line passing through the point P and the center of the substrate intersects with an outer periphery of the thermosetting sheet is 0.9Lp or more and 1.1Lp or less. In the same field of endeavor, Toyoda (Figs. 1-2) discloses a method for sealing an electronic component mounting substrate 3/5 (Fig. 1D, ¶ 0048) including using a thermosetting sheet 8 (¶ 0047) smaller in size than the substrate 3 (Figs. 2A-2B; ¶ 0047), and wherein when a distance between a center of the substrate 5 and an optional point P on a frame line (Fig. 1D, dotted line with dimensions labelled P, Q, ¶ 0047 - “electronic parts-mounting area”) that surrounds all of the plurality of electronic components 5 and minimizes a surrounded area is denoted by Lp, a distance Lq between the center of the substrate 5 and a point Q at which a straight line passing through the point P and the center of the substrate intersects with an outer periphery of the thermosetting sheet is 0.9Lp or more and 1.1Lp or less (¶ 0047 - disclosing the dimension Bx of 8 along the x-axis [i.e., width] is greater than dimension Q x 0.8 [i.e., width of the electronic parts-mounting area x 0.8], a range with overlap of the claimed range). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Nakamura with the dimension relationship between the thermosetting sheet and substrate, as disclosed by Toyoda, for the purpose of preventing leakage of the melted sheet and avoiding filling failure of an underfill (Toyoda, ¶ 0039).
Regarding claim 2, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, wherein the distance Lq between the point Q and the center of the substrate is 1.05Lp or less (Toyoda, ¶ 0047 - disclosing the dimension Bx of 8 along the x-axis [i.e., width] is greater than dimension Q x 0.8 [i.e., width of the electronic parts-mounting area x 0.8], a range with overlap of the claimed range).
Regarding claim 3, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Toyoda (Figs. 1-2) discloses further wherein an outer shape of the substrate 3 (Fig. 1D) and an outer shape of the thermosetting sheet 8 (Fig. 1B) are similar to each other (Figs. 1B, 1D, 2B).
Regarding claim 4, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Nakamura (Fig. 1) discloses wherein a height of each of the electronic components 5 is 5 μm to 800 μm (¶ 0126), and a distance of a gap between the electronic components is 5 μm to 2000 μm (¶ 0126).
Regarding claim 5, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Nakamura (Fig. 1) discloses wherein a height of the space between the electronic component and the substrate is 5 μm to 100 μm (¶ 0091).
Regarding claim 6, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, and contemplate various materials for use in the thermosetting sheet (see, e.g. Nakamura ¶ 0047) however fail to expressly disclose wherein the thermosetting sheet has a layer A constituted of a resin composition A having a maximum value of tan δ (loss tangent) of 3 or more as measured at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a material having the recited maximum value of tan δ (loss tangent) of 3 or more as measured at a measurement temperature of 125° C. for a measurement time of 0 to 100 seconds, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the loss tangent is considered a result effective variable because it affects the physical properties of the material, e.g., the ability of the material to absorb shock and vibration. Thus the ordinary artisan would have been motivated to select a material providing the recited loss tangent range for the purpose of obtaining desired physical properties of the material to form a functional device.
Regarding claim 7, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 6, wherein the thermosetting sheet further has a layer B 2 (Nakamura, ¶ 0043, Fig. 1A) composed of a resin composition B (¶ 0043), however fail to expressly disclose: the layer B satisfying a formula: 40,000≤α×E′≤250,000 [Pa/K], where α represents a thermal expansion coefficient [ppm/K] at 80° C. of a cured product obtained by heating and curing the resin composition B at 175° C. for 1 hour, and E′ represents a storage modulus [GPa] at 25° C. of the cured product.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a resin composition satisfying a formula: 40,000≤α×E′≤250,000 [Pa/K], where α represents a thermal expansion coefficient [ppm/K] at 80° C. of a cured product obtained by heating and curing the resin composition B at 175° C. for 1 hour, and E′ represents a storage modulus [GPa] at 25° C. of the cured product, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the range of thermal expansion coefficient and storage modulus satisfying the recited formula is considered a result effective variable because it affects the physical properties of the material, e.g., the rigidity of the layer and how the size of the layer will change with temperature. Thus the ordinary artisan would have been motivated to select a material providing the above properties satisfying the recited formula for the purpose of obtaining desired physical properties of the layer to successfully manufacture a functional device.
Regarding claim 8, Nakamura (Fig. 1) and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 7, however fail to expressly disclose wherein a ratio B/A of a thickness of the layer B to the layer A is 0.1 to 80. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited thickness ratio, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the thickness ratio is considered a result effective variable because the layer thicknesses affect the ability of the thermosetting sheet comprised of layer A and layer B to effectively cover the electronic components (see, e.g., Nakamura, ¶¶ 0044, 46). Thus the ordinary artisan would have been motivated to modify the thicknesses and their ratio for the purpose of ensuring successful underfill of the electronic component mounting substrate.
Regarding claim 9, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Nakamura (Fig. 1) discloses wherein the thermosetting sheet 3 contains a filler (¶ 0086).
Regarding claim 10, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 9, Nakamura discloses wherein a maximum particle diameter of the filler is 35 μm or less (¶¶ 0090-91).
Regarding claim 11, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 9, Nakamura discloses wherein a content of the filler in the thermosetting sheet is 30 to 85 mass % (¶ 0093).
Regarding claim 12, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, however fail to expressly disclose wherein the thermosetting sheet is circular in shape. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a thermosetting sheet circular in shape since it has been held by the courts that a change in shape or configuration, without any criticality, is nothing more than one of numerous shapes that one of ordinary skill in the art will find obvious to provide based on the suitability for the intended final application. See In re Dailey, 149 USPQ 47 (CCPA 1976). It appears that the disclosed thermosetting sheet would perform equally well shaped as disclosed by Nakamura and Toyoda, and one of ordinary skill in the art would appreciate that the shape of thermosetting sheet provided will vary based on the particular arrangement of electronic components mounted on the substrate.
Regarding claim 13, Nakamura and Toyoda disclose a thermosetting sheet for use in the method for sealing an electronic component mounting substrate according to claim 6 (see above rejection of claim 6).
Regarding claim 14, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Nakamura discloses wherein a height of the space between the electronic component and the substrate is 5 μm to 40 μm (¶ 0091).
Regarding claim 15, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 9, Nakamura discloses wherein an average particle diameter of the filler is 10 μm or less (¶ 0089).
Regarding claim 16, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Toyoda discloses wherein the distance Lq between the point Q and the center of the substrate is 0.91Lp or more (Toyoda, ¶ 0047 - disclosing the dimension Bx of 8 along the x-axis [i.e., width] is greater than dimension Q x 0.8 [i.e., width of the electronic parts-mounting area x 0.8], a range with overlap of the claimed range).
Regarding claim 17, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 16, Toyoda discloses wherein the distance Lq between the point Q and the center of the substrate is 0.93Lp or more (Toyoda, ¶ 0047 - disclosing the dimension Bx of 8 along the x-axis [i.e., width] is greater than dimension Q x 0.8 [i.e., width of the electronic parts-mounting area x 0.8], a range with overlap of the claimed range).
Regarding claim 18, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to claim 1, Nakamura (Fig. 1) discloses wherein in the step (c), in a pressure atmosphere lower than atmospheric pressure, the placed thermosetting sheet is heated to allow a melt of the thermosetting sheet to fill the space between the electronic component and the substrate and be cured (Nakamura, ¶¶ 0099-0100).
Regarding claim 20, the method for sealing an electronic component mounting substrate according to any one of claims 1 to 15, wherein the distance Lq between the point Q and the center of the substrate is less than Lp (Toyoda, ¶ 0047 - disclosing the dimension Bx of 8 along the x-axis [i.e., width] is greater than dimension Q x 0.8 [i.e., width of the electronic parts-mounting area x 0.8], a range with overlap of the claimed range).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura and Toyoda as applied to claims 1-14 above, and further in view of US 2015/0179482 A1 to Mitani et al. (hereinafter “Mitani”).
Regarding claim 19, Nakamura and Toyoda disclose the method for sealing an electronic component mounting substrate according to any one of claims 1 to 14, however fail to expressly disclose: wherein the thermosetting sheet is adhered to a release treatment film, and, after the step (c), the release treatment film is peeled off.
In the same field of endeavor, Mitani (Figs. 1A-1D) discloses a method for sealing an electronic component mounting substrate including a thermosetting sheet 6 (¶ 0097) adhered to a release treatment film 5 (¶ 0097), and after heat-molding the thermosetting sheet (¶ 0097), the release treatment film is peeled off (¶ 0103; Fig. 1C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Nakamura and Toyoda to include a release treatment film as taught by Mitani for the purpose of facilitating the removal of rigid base 2 of Nakamura from thermosetting sheet 3 after step (c) (Nakamura, ¶ 0020), for the purpose of reducing the thickness of the final electronic component produced, while reducing warpage during the underfill and encapsulation process (see Nakamura, ¶ 0025).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
27 May 2026
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights