DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment and Arguments
Applicant’s amendment filed on July 20, 2026 has been entered and made of record. Claims 17-26 are pending and are being examined in this application.
Applicant’s arguments with respect to the 102 rejection have been fully considered, but are directed to a newly added limitation, which is addressed in the updated mappings provided below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-36 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Brady et al. (US Pub. 20190392296).
Referring to claim 17, Brady discloses A model compiling method, comprising:
acquiring a model file corresponding to a machine learning model comprising a plurality of computation layers in response to a running indication [fig. 10; pars. 46-49; a neural network graph is received (for compiling a neural network for consumption by target hardware); note that a neural network, by definition, comprises a plurality of neural network layers, each layer comprising a plurality of neurons (i.e., operations) and data flowing between layers];
parsing the model file to obtain a first computational graph executable by hardware, wherein the first computational graph comprises a plurality of first operators, and each of the first operators corresponds to at least one of the computation layers [fig. 10 and 11A; pars. 46-49; the neural network graph is parsed to obtain an intermediate representation (i.e., computation graph) executable by the target hardware, where the intermediate representation includes an operator model identifying operations and corresponding tensors and data flows of the neural network; by definition, each operation, tensor, and data flow (i.e., operator) corresponds to at least one neural network layer of operations];
determining runtime information of a first set of first operators according to an input from a user and the first computational graph [figs. 10 and 11A-11C; pars. 46-54 and 74; the intermediate representation also includes a data model and a control model, which are generated according to the operator model and a target descriptor file provided as input by a user; the data model serves as a resource sub-model that models available resources that can be allocated to the tensors, where each type of resource (e.g., memory resources) has a dedicated view; the control model implements a portion of the resource sub-model (e.g., a view of the resource sub-model related to computation resources vs. memory resources) by defining a runtime order of the operations based on native ordering expressed in the neural network and hardware resource limitations of the target hardware], wherein the first set of first operators comprises at least a subset of the plurality of first operators [figs. 11A-11C; pars. 49-54; the data model includes the tensors, which are a subset of the operators; the control model includes the operations, which are a subset of the operators; and the tensors and operations combined are also a subset of the operators];
determining hardware configuration information corresponding to each first operator in the first set of first operators according to the runtime information of each first operator in the first set of first operators [fig. 10; pars. 46-49; a binary executable is generated from the intermediate representation (according to the operator model, the data model, and the control model)], wherein the hardware configuration information corresponding to the first operator comprises values of configuration parameters required for configuring hardware to perform computation corresponding to the first operator [pars. 32, 53, 54, 65, 66, and 72-79]; the binary executable is a serial binary (e.g., a binary serially streamed out one byte at a time) optimized for implementing the neural network on the target hardware in accordance with compilation descriptor and target descriptor files; the target descriptor file describes attributes and resource constraints of the target hardware; e.g., “target descriptors may be accepted and consumed by example compilers and the compiler may use the information within the target descriptor to flexibly tune the compilation process to the specific hardware architecture of potentially any one of multiple different devices. For instance, the target descriptor may specify which computations resources of a device are comparable performing which types of neural network operations (e.g., specifying that a convolution can be executed on either a SHAVE processor or a hardware accelerator). Example target descriptors may further specify the parameters of the operation (e.g., kernel size) that the particular computation resource can support (e.g., specifying that a particular hardware accelerator is limited to kernel sizes of 11×11)”]; and
sending the hardware configuration information corresponding to each of the plurality of first operators to a streaming-based execution device, to cause the execution device to perform computation corresponding to each first operator [fig. 10; pars. 32, 33, and 46-49; the binary executable is sent to the target hardware (e.g., Streaming Hybrid Architecture Vector Engine processors) for execution (according to the operator model, the data model, and the control model)].
Referring to claim 18, Brady discloses The method according to claim 17, wherein static data required for performing the computation corresponding to each of the plurality of first operators is obtained through the parsing [fig. 11B; pars. 50-52; note the resource sub-model modeling the available resources that can be allocated to the tensors]; and determining runtime information of the first set of first operators according to the input from the user and the first computational graph comprises: determining output information of each first operator in the first set of first operators according to the input, the at least one computation layer corresponding to the first operator, and the static data of the first operator [figs. 10, 11A-11C; pars. 48-54; outputs of the operators in the data model and control model are determined according to the target descriptor file describing the available resources, the at least one neural network layer of operations, and the resource sub-model], wherein the runtime information of the first operator comprises the output information of the first operator [figs. 11B and 11C; pars. 46, 47, 50-54; the outputs are included in the data model and the control model].
Referring to claim 19, Brady discloses The method according to claim 17, wherein the plurality of first operators comprises the first set of first operators and a second set of first operators other than the first set of first operators, and the method further comprises: acquiring hardware configuration information corresponding to each first operator in the second set of operators [figs. 10 and 11A-11C; pars. 46-54; note the multiple possible subsets (i.e., the tensors of the data model, the operations of the control model, and combination thereof); also note that the binary executable is generated from the intermediate representation (according to the operator model, the data model, and the control model)].
Referring to claim 20, Brady discloses The method according to claim 17, further comprising: receiving structural information of the machine learning model input by the user, wherein the structural information comprises types, numbers, and connection manners of the plurality of computation layers [fig. 10 and 11A; pars. 48, 49, and 58; the neural network graph is generated by the user, provided as input, then parsed to generate the operator model, which provides a configurable representation of a mathematical structure of the neural network (e.g., DNN) in the form of a computation graph; the operations serve as building blocks of the neural network; the tensors represent products (e.g., multidimensional arrays) of the operations; and the data flows of the neural network represent data dependencies between operations that refer to tensors]; generating a second computational graph corresponding to the machine learning model according to the structural information, wherein the second computational graph comprises a plurality of second operators one-to-one corresponding to the plurality of computation layers [fig. 11A; pars. 46-49; note the operator model comprising the operators of the neural network]; converting the second computational graph into the first computational graph, wherein each of the plurality of first operators corresponds to at least one second operator [figs. 10 and 11A-11C; pars. 46-54; the operator model is used to obtain the data model and the control model, which are all encapsulated in the intermediate representation]; and obtaining the model file according to the first computational graph [fig. 10; pars. 46 and 47; note the intermediate representation].
Referring to claim 21, Brady discloses The method according to claim 20, wherein the structural information further comprises layer parameters of each of the plurality of computation layers, and the method further comprises: determining static data of the second operator corresponding to each computation layer according to the layer parameters of the computation layer [fig. 11B; pars. 50-52; note the resource sub-model modeling the available resources that can be allocated to the tensors]; and obtaining, according to the static data of at least one second operator corresponding to each of the plurality of first operators, static data required for performing the computation corresponding to the first operator [fig. 11B; pars. 50-52; note the resource sub-model modeling the available resources that can be allocated to the tensors]; and obtaining the model file according to the first computational graph comprises: serializing the first computational graph and the static data required for performing the computation corresponding to each of the plurality of first operators to obtain the model file [figs. 10 and 11C; pars. 47, 53, and 54; note the control model defining a runtime order of the operations based on native ordering expressed in the neural network and hardware resource limitations of the target hardware; the control model is encapsulated in the intermediate representation]; and obtaining the model file according to the first computational graph [fig. 10; pars. 46 and 47; note the intermediate representation].
Referring to claim 22, Brady discloses The method according to claim 20, wherein at least one of the plurality of first operators corresponds to a plurality of second operators [figs. 10 and 11A; pars. 46-49; note the operator model comprising the operators and the intermediate representation including the operator model comprising the operators].
Referring to claim 23, Brady discloses The method according to claim 20, wherein the second computational graph comprises a computational sub-graph [fig. 10; par. 46; the operator model is a sub-model of the intermediate representation], and the computational sub-graph is generated in advance based on types, numbers, and connection manners of at least two computation layers [fig. 11A; par. 49; note that the operator model provides a configurable representation of a mathematical structure of the neural network (e.g., DNN) in the form of a computation graph; the operations serve as building blocks of the neural network; the tensors represent products (e.g., multidimensional arrays) of the operations; and the data flows of the neural network represent data dependencies between operations that refer to tensors].
Referring to claim 24, Brady discloses The method according to claim 20, wherein the running indication is received via a first application programming interface, the structural information is received via a second application programming interface, and the first application programming interface and the second application programming interface are located in a same user interface [fig. 12; pars. 56, 58, and 59; note the compilation API for providing the neural network graph as input and the configuration API for providing the target descriptor file as input; both API are provided via a middle-end interface of a compiler].
Referring to claim 25, Brady discloses The method according to claim 17, wherein the execution device comprises an artificial intelligence accelerator [par. 32; note the machine learning accelerator].
Referring to claim 26, Brady discloses The method according to claim 17, wherein the machine learning model is a neural network model [pars. 46 and 47; note the neural network model].
Referring to claim 27, see at least the rejection for claim 1. Brady further discloses A model compiling apparatus, comprising: a memory; and a processor, coupled to the memory, and configured to perform the claimed steps based on instructions stored in the memory [fig. 2; pars. 26-28; computing system 206 comprises memory 215 and processor 210 for executing compiler 105].
Referring to claim 28, see the rejection for claim 18.
Referring to claim 29, see the rejection for claim 19.
Referring to claim 30, see the rejection for claim 20.
Referring to claim 31, see the rejection for claim 21.
Referring to claim 32, Brady discloses A model running system, comprising: a compiler, wherein the compiler comprises the model compiling apparatus according to claim 27; and an execution device configured to make a configuration according to hardware configuration information corresponding to each of the plurality of first operators sent by the compiler, to perform computation corresponding to each first operator [fig. 2; pars. 26-28; computing system 206 comprises memory 215 and processors 210 for executing compiler 105 and machine learning processor 125 for executing the executable binary (i.e., the operations of the neural network)].
Referring to claim 33, see the rejection for claim 22.
Referring to claim 34, see the rejection for claim 23.
Referring to claim 35, see the rejection for claim 24.
Referring to claim 36, see the rejection for claim 25.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE PARK whose telephone number is (571)270-7727. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TAMARA KYLE can be reached at (571)272-4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Grace Park/Primary Examiner, Art Unit 2144
