Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claims 11-22 and 31-33 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections from the prior office action. Hence, 35 U.S.C. 112(b) rejection is withdrawn.
Applicant's arguments filed on 04/20/2026 have been fully considered but they are not persuasive. Applicant argues that Wu merely discloses an internal interface between insulating layers, not a bottom surface exposed through a cavity. However, the rejection does not rely on a buried internal interface. Rather, Wu teaches that cavity C exposes second inner surface 122b of inner dielectric layer 122. Thus, Wu’s second inner surface 122b is an actual exposed surface of a remaining insulating portion of the second insulating layer, corresponding to the claimed bottom surface exposed through the cavity.
Further, regarding the amended limitation that an inclined bottom surface whose height decreases toward the circuit pattern, Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant argues that Wu does not teach an inclined bottom surface whose height decreases toward the circuit pattern. The office now relies on Boyko that teaches a printed circuit board cavity having a concaved smooth/filleted bottom transition as explained in the rejection below.
Applicant’s argument regarding a V-shaped surface, continuous gradual slope, absence of a stop layer, molding-layer contact area, and improved bonding strength are not commensurate with amended claim 11, which does not recite those features. Accordingly, Wu in view of Chang and Boyko teaches the limitations of amended claim 1, and the rejection is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180153036 A1) in view of Chang (US 20110284267 A1) further in view of Boyko (US 6214525 B1).
Re: Independent Claim 11 (Currently Amended), Wu discloses a circuit board comprising:
a first layer (Wu, Figs. 1A-1D, ¶ [0034], core layer 112 in inner circuit structure 110);
a second insulating layer disposed on the first layer and including a cavity (Wu, ¶ [0035], inner dielectric layer 122 disposed on core layer 112) and including a cavity (Wu, first build up circuit structure 120 includes cavity C); and
a circuit layer disposed between the first layer and the second insulating layer (Wu, Fig. 1D, first patterned circuit layer 114 disposed between core layer 112 and inner dielectric layer 122),
wherein the second insulating layer forming the cavity includes a bottom surface exposed through the cavity and an inner wall surface exposed through the cavity and extending from the bottom surface toward an upper surface of the second insulating layer (Wu, Fig. 1D, ¶ [0038], cavity C extends from the first surface 121 of build-up structure 120 down to inner dielectric layer 122, and the cavity exposes the second inner surface 122b of inner dielectric layer 122, which corresponds to the claimed exposed bottom surface of the second insulting layer, and necessarily includes side/inner wall surface through the removed build-up material),
wherein the circuit layer includes a circuit pattern that overlaps the cavity in a vertical direction and protrudes from the bottom surface (Wu, Fig 1D, cavity C exposes a portion of first patterned circuit layer 114 (pad P/circuit T) so it overlaps the cavity footprint; Wu further teaches the top surface 114a of the exposed portion is higher than the cavity-exposed second inner surface 122b, i.e., the circuit pattern protrudes upward relative to the cavity bottom surface),
wherein the bottom surface is located between upper and lower surfaces of the circuit pattern (Wu, Fig 1D, cavity C exposes second inner surface 122b and teaches top surface 114a of the exposed circuit portion is higher than 122b; Wu also teaches, in Fig. 4B, bottom surface 114b of the exposed circuit portion is aligned with the upper surface 111 of the core layer (i.e., the circuit has upper and lower surfaces 114a/114b), and the cavity bottom surface (122b) is at an intermediate height relative to 114a/114b.
Wu is silent regarding core layer 112 being "insulating". However, Chang teaches, in ¶ [0040], Fig. 2B, first core layer 210 includes a core dielectric layer 212 (explicit insulating core).
Both Wu and Chang disclose printed circuit board with cavity, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Wu's core layer 112 as a dielectric/insulating core as taught by Chang, because both references relate to multilayer/buildup circuit boards and using a dielectric core is a predictable design choice for electrical isolation and board fabrication.
Regarding the limitation “the bottom surface is inclined such that a height of the bottom surface decreases with respect to an upper surface of the first insulating laver along a direction from the inner wall surface of the cavity toward the circuit pattern”, Although Wu teaches, in Fig 1D, ¶ [0038] that the cavity C exposes a first inner surface 122a and a second inner surface 122b of the inner dielectric layer 122, where the first inner surface 122a is higher than the second inner surface 122b, which necessarily provides a cavity bottom profile having a decreasing height toward the region of the exposed circuit layer portion (pad P/circuit T), Wu is silent regarding continuously inclined bottom surface.
However, Boyko teaches, in Figs. 4-5 and column 6 lines 63-68, a printed circuit board having cavity with a smooth/filleted concave bottom transition rather than a sharp right-angle cavity bottom. This fillet has a smooth and concave surface, which minimizes stress concentrations and the tendency to trap fluids or contaminants during subsequent processing. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu’s cavity bottom/inner-wall transition to include the inclined/filleted profile taught by Boyko so that the cavity-bottom height decreases from the inner wall surface toward the circuit pattern, in order to reduce sharp-corner stress concentration, reduce trapping of contamination or processing fluids, and facilitate formation/carcinization of the cavity.
Re Claim 12 (Currently Amended), Wu, Chang and Boyko disclose all the limitations of claim 11 on which this claim depends.
Wu further teaches,
wherein the bottom surface includes a first contact portion in contact with the inner wall surface (Wu, Fig. 1D, cavity C formed to expose the second inner surface 122b of inner dielectric layer 122, wherein the cavity bottom surface (e.g., 122b) necessarily meets the cavity side/inner wall surface at the perimeter/corner region) and a second contact portion in contact with a side surface of the circuit pattern (Wu, Fig., 1D, cavity C exposes a portion of the first patterned circuit 114, specifically including pad P and circuit T, and exposes second inner surface 122b; thus the cavity bottom surface portion (e.g., 112b) contacts the side surface of the exposed circuit pattern 114 (pad P/circuit T) at their interface), and
wherein the first contact portion and the second contact portion are positioned between the upper and lower surfaces of the circuit pattern (Wu, Fig. 1D, top surface 114a of the exposed portion of the first patterned circuit layer 114 is higher than the cavity-bottom surface (second inner surface 122b), and Wu further teaches, in Figs 1A-1B, the first patterned circuit layer 114 is disposed on the upper surface 111 of the core layer 112, thereby defining the lower surface of the circuit pattern 114 at the interface with surface 111; thus, the cavity bottom surface (112b) and the claimed first/second contact portions on that cavity bottom are located between the circuit pattern's upper surface 114a and its lower surface at the 114/111 interface).
Re Claim 13 (Currently Amended), Wu, Chang and Boyko disclose all the limitations of claim 11 on which this claim depends.
Wu further teaches,
wherein the circuit pattern includes a plurality of pads spaced apart in a horizontal direction (Wu, Fig. 1D/1E, the cavity C exposes a portion of the first patterned circuit layer 114 including pads P, and these pads P are arranged horizontally along layer 114);
wherein the bottom surface includes a first portion positioned between a side surface of one of the plurality of pads and the inner wall surface (Wu, Figs., 1C-1E, the cavity C includes inner wall surface (sidewall) and exposes an inner dielectric "bottom" surface; Wu teaches the inner dielectric layer 122 has a first inner surface 122a (exposed by opening O) and a second inner surface 122b (exposed by cavity C). The first portion of the cavity bottom corresponds to the region at/along the exposed inner dielectric surface (e.g., 122a) that lies between a pad P side surface (of the circuit layer 114) and the cavity inner wall surface), and a second portion positioned between the plurality of pads (Wu, Fig 1D-1E, the cavity C exposes the second inner surface 122b of the inner dielectric layer 122 in the region associated with the exposed pads P, including the region between laterally spaced pads on the first patterned circuit layer 114; the second portion corresponds to this exposed recessed dielectric surface 122b between the pads), and
wherein a height of the second portion is lower than a height of the first portion (Wu, Fig 1E, Wu teaches the inner dielectric layer 122 has first inner surface 122a and second inner surface 122b, and the first inner surface 122a is higher than the second inner surface 122b).
Re Claim 22 (Currently Amended), Wu, Chang and Boyko disclose all the limitations of claim 11 on which this claim depends.
Boyko further teaches wherein the second insulating layer forming the cavity includes a curved transition surface provided between the inner wall and the bottom (Boyko teaches, in Figs. 4-5 and column 6 lines 63-68, a printed circuit board having cavity with a smooth/filleted concave bottom transition rather than a sharp right-angle cavity bottom. This fillet has a smooth and concave surface, which minimizes stress concentrations and the tendency to trap fluids or contaminants during subsequent processing. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu’s cavity bottom/inner-wall transition to include curved transition profile taught by Boyko, in order to reduce sharp-corner stress concentration, reduce trapping of contamination or processing fluids, and facilitate formation/carcinization of the cavity).
Claims 14-17, 19 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180153036 A1) in view of Chang (US 20110284267 A1) further in view of Boyko (US 6214525 B1) and further in view of Booth (US 20140262477 A1).
Re Claim 14 (Currently Amended), Wu, Chang and Boyko disclose all the limitations of claim 11 on which this claim depends.
Wu, Chang and Boyko are silent regarding the circuit board comprising an electronic device disposed in the cavity.
However, Booth teaches including an electronic device disposed in the cavity (Booth, ¶ [0037], Figs 7-9, printed circuit board 100 having cavity 300, and electronic component 701 installed/positioned such that the electronic component 701 is at least partially disposed within the cavity 300).
Wu, Chang, Boyko and Booth disclose printed circuit board with cavity, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the cavity-bearing circuit board of Wu to dispose an electronic device within the cavity as taught by Booth, in order to reduce overall assembly height of the combined structure compared to a surface-mounted component (Booth, ¶ [0016]).
Re Claim 15 (Previously Presented), Wu, Chang, Boyko and Booth disclose all the limitations of claim 14 on which this claim depends.
Wu and Booth further teach,
wherein the electronic device overlaps the inner wall surface along a horizontal direction (Booth discloses, in Figs. 6-7, a printed circuit board 100 having a cavity 300 with side walls 301 (i.e., inner wall surfaces) and bottom 401. Booth further discloses electronic component 701 mounted to substrate 702, where the assembly is positioned such that the electronic component 701 is at least partially disposed within cavity 300. Booth additionally teaches, in Fig 7 and ¶ [0037] an electrically-conductive foam 703 disposed around the electronic component 701, and the assembly is juxtaposed to the PCB so the component is placed in the cavity. Because Booth places the electronic component 701 into the cavity 300 defined by inner wall surfaces 301, the electronic component is positioned in the cavity such that it laterally overlaps (in horizontal direction) the region defined by cavity's inner wall surfaces).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the circuit board of Wu (as modified by Chang and Booth to include an electronic device disposed in the cavity) such that the electronic device is positioned to overlap the cavity's inner wall surface along a horizontal direction, in order to achieve the predictable benefit taught by Booth of integrating electronic component into the cavity footprint for use of one or more electronic components in conjunction with a given printed circuit board in an application where space limitations might otherwise forbid such a combination (Booth ¶ [0039]).
Re Claim 16 (Previously Presented), Wu, Chang, Boyko and Booth disclose all the limitations of claim 14 on which this claim depends.
Wu and Booth further teach,
the circuit board comprising: an upper circuit layer embedded in the second insulating layer (Wu, Fig. 1D and ¶ [0035], Wu teaches an embedded circuit layer- the first patterned conductive layer 124 positioned within the build-up dielectric stack i.e., layer 124 disposed between dielectric layers 122 and 126, thereby teaching an "upper circuit layer embedded" in an insulating layer), and
wherein the upper circuit layer overlaps the electronic device along the horizontal direction (Booth teaches an electronic device disposed in the cavity, which creates a predictable need to route signals/power in the board stack in the same lateral footprints as the recessed device (e.g., to connect to or route past the device without increasing overall board height). Wu teaches how to realize such routing using an embedded (buried) patterned conductive layer 124 within the dielectric build-up. Thus, when Wu's embedded upper circuit layer is incorporated into the cavity board with Booth's cavity mounted device, it would have been obvious layout choice to position at least part of that embedded upper circuit layer in the region laterally corresponding to the cavity/device footprint, i.e., to overlap the electronic device along a horizontal direction, to achieve routing/connection while maintaining a low-profile cavity structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Wu's circuit board (as supplemented by Booth to place an electronic device in the cavity) by implementing Wu's embedded build-up circuit layer (patterned conductive layer 124 buried within dielectric layers 122/126) as an upper circuit layer embedded in the second insulating layer, in order to provide additional routing/interconnection capability in the build-up dielectric while preserving the low-profile benefit of Booth's cavity-mounted device. Further, it would have been obvious to located that embedded upper circuit layer in the same lateral region as the cavity-mounted device (i.e., overlapping in the horizontal direction) because routing over/within the footprint of a recessed device is a predictable and commonly required PCB layout solution to connect to the device and/or route signals across the cavity region without increasing thickness.
Re Claim 17 (Previously Presented), Wu, Chang, Boyko and Booth disclose all the limitations of claim 16 on which this claim depends.
Wu and Booth further teach,
wherein the upper circuit layer includes: an upper circuit pattern (Wu teaches that the build-up structure 120 includes at least one patterned conductive layer 124 (i.e., a circuit pattern/routing metal) stacked with dielectric layers 122 and 126) overlapping the electronic device and the inner wall surface along the horizontal direction (Wu is silent regarding an electronic device being disposed in the cavity, however Booth (as applied in claim 14) teaches placing an electronic component 701 at least partially within a cavity 300 of a circuit board. Once Booth's cavity-mounted device is used in Wu's cavity bearing board, it would be obvious to implement Wu's embedded routing pattern 124 in the dielectric region surrounding/adjacent the cavity footprint so that its lateral (horizontal) projection overlaps the device footprint, in order to route signals/powers to/from the cavity mounted device while maintaining the low-profile cavity integration taught by Booth and using the embedded routing capability of Wu. Further, Wu teaches formation of the cavity C in the build-up dielectric, the cavity C exposes a portion of the inner dielectric layer 122. including the second inner surface 122b. The cavity C necessarily has an inner wall surface (sidewall) extending from the cavity bottom toward the upper surface of the build-up structure. Placing the patterned conductive layer 124 laterally within the build-up region at/near the cavity boundary (a typical routing location proximate a cavity-mounted device) causes the horizontal projection of the circuit pattern to overlap the inner wall surface region (i.e., the cavity sidewall location); and an upper via electrode connected to the upper circuit pattern (Wu teaches, in Fig. 1D, ¶ [0035], a first conductive via structure 128 and that the first patterned conductive layer 124 is electrically connected to the first patterned circuit layer 114 via the first conductive via structure 128, i.e., 128 is a via electrode connected to the circuit pattern 124) and overlapping the electronic device and the inner wall surface along the horizontal direction ( Wu is silent regarding positioning a via relative to a cavity-mounted device. However, once Booth's device is disposed in the cavity (claim 14 context), it would have been obvious to locate at least one such via electrode 128 (connected to the embedded routing pattern 124) in the same lateral region as the cavity/device footprint and cavity boundary, in order to provide the predictable vertical interconnection from the embedded routing layer to other circuitry (or to interconnects serving the cavity-mounted device) proximate the cavity region).
Hence, Wu provides the claimed upper circuit pattern (124) and upper via electrode connected thereto (128) in a cavity-bearing build-up structure, but is silent on the specific "horizonal overlap" placement relative to a cavity-mounted device; Booth supplies the cavity-mounted device context, and it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to position Wu's embedded routing layer/via in the cavity footprint/boundary region so their horizontal projections overlap the device and the cavity inner wall region, to achieve predictable routing/interconnection for the embedded device.
Re Claim 19 (Previously Presented), Wu, Chang and Boyko disclose all the limitations of claim 11 on which this claim depends.
Wu, Chang and Boyko are silent regarding,
wherein a width of the cavity at an upper end of the inner wall is equal to a width of the cavity at a lower end of the inner wall.
However, Booth teaches wherein a width of the cavity at an upper end of the inner wall is equal to a width of the cavity at a lower end of the inner wall (Although Wu teaches cavity C formed from opening O in the first build-up circuit structure, providing the claimed "inner wall" surface extending from the cavity bottom toward the upper surface/first surface pf the build-up structure; Wu is silent regarding an express requirement that the cavity's width at the upper end equals the width at the lower end. However, Booth, Figs. 2-4 and ¶ [0024], teaches a printed circuit board 100 having cavity 300 with sidewalls 301 and bottom 401, and expressly state that the cavity 300 comprises a rectangular cuboid, which indicates straight/parallel sidewalls such that the cavity width at the upper end of the sidewall is equal to the width at the lower end of the sidewall).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Wu's cavity C with a constant-width inner wall as taught by Booth's rectangular-cuboid cavity in order to achieve a predictable cavity geometry that facilitates manufacturability (Booth, ¶ [0039]).
Re Claim 31 (Previously Presented), Wu, Chang, Boyko and Booth disclose all the limitations of claim 15 on which this claim depends.
Wu and Booth further teach,
a protective layer disposed on the second insulating layer (Wu, in Fig. 1E and ¶ [0039], teaches forming a first patterned solder mask layer 140 (i.e., a protective layer) on the first surface 121 of the first build-up circuit structure 120), and wherein the electronic device overlaps the protective layer along the horizontal direction (Booth, in Fig 7, teaches that the electronic component 701 is at least partially disposed within cavity 300, and 701 is not fully nested such that it extends above the first side 101 of the printed circuit board 100. Under a plan view understanding of "overlaps along the horizontal direction", a device located within the cavity opening necessarily has a footprint that overlaps the board surface region where the protective (solder mask) layer is disposed).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide Wu's protective solder mask layer (protective layer 140) on the insulating surface of a cavity-bearing board that includes Booth's cavity mounted device, in order to cover/protect surface circuitry (Wu, ¶ [0025]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180153036 A1) in view of Chang (US 20110284267 A1) further in view of Boyko (US 6214525 B1) and further in view of Hofmann (US 20070163887 A1).
Re Claim 18 (Previously Presented), Wu, Chang and Boyko disclose all the limitations of claim 13 on which this claim depends.
Wu, Chang and Boyko are silent regarding,
wherein a vertical cross- sectional shape combining the first and second portions of the bottom surface has a V- shape.
However, Hofmann teaches wherein a vertical cross- sectional shape combining the first and second portions of the bottom surface has a V- shape (Hofmann teaches, in ¶ [0060], that dielectric recesses (trenches and vias produced by laser ablation) are configured in an approximately V-shape, like notches, and explains this profile facilitates the electrolytic deposition of metal).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the cavity bottom profile of Wu in view of Chang and Boyko with a V-shaped vertical cross section as taught by Hofmann, in order to implement a known recess sidewall/bottom profile that improves manufacturability by facilitating the electrolytic deposition of metal in the recesses dielectric features (Hofmann, ¶ [0060]) while maintaining the same functional cavity and pad arrangement of Wu in view of Chang.
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180153036 A1) in view of Chang (US 20110284267 A1) further in view of Boyko (US 6214525 B1) and further in view of Kaneko (US 20150009645 A1).
Re Claim 20 (Previously Presented), Wu, Chang and Boyko disclose all the limitations of claim 11 on which this claim depends.
Wu, Chang and Boyko are silent regarding,
wherein a thickness of the second insulating layer is in a range of 5µm to 20µm.
However, Kaneko teaches wherein a thickness of the second insulating layer is in a range of 5µm to 20µm (Kaneko teaches, in ¶ [0039] and Fig. 1A, insulating layer 14 has thickness between about 15 μm and about 35 μm) which is includes the range 15-20 µm).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form Wu's second insulating layer with thickness within the claimed 5-20 µm range, as taught by Kaneko's thin insulating layer (e.g., 15-35 µm, which includes 15-20 µm), in order to achieve a thinner build-up insulating structure suitable for miniaturized, high density circuit boards.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180153036 A1) in view of Chang (US 20110284267 A1) further in view of Boyko (US 6214525 B1) and further in view of Kaneko (US 20150009645 A1) and further in view of Jeon (US 20220141953 A1).
Re Claim 21 (Previously Presented), Wu, Chang and Kaneko disclose all the limitations of claim 20 on which this claim depends.
Wu, Chang, Boyko and Kaneko are silent regarding,
wherein the second insulating layer includes RCC (Resin Coated Copper).
However, Jeon teaches wherein the second insulating layer includes RCC (Resin Coated Copper) (Jeon, ¶ [0065] and Fig. 3, teaches insulating layer 115 includes resin coated copper (RCC)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Jeon's insulating layer that includes RCC material to form Wu's insulating layer in order to form insulating layer with relatively small modulus material (Jeon, ¶ [0065]).
Claims 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20180153036 A1) in view of Chang (US 20110284267 A1) further in view of Boyko (US 6214525 B1) further in view of Booth (US 20140262477 A1) and further in view of Baek (US 20170094797 A1).
Re Claim 32 (Previously Presented), Wu, Chang, Boyko and Booth disclose all the limitations of claim 15 on which this claim depends.
Wu, Chang, Boyko and Booth are silent regarding,
comprising a burying insulating layer disposed in the cavity and embedding the electronic device.
However, Baek teaches comprising a burying insulating layer disposed in the cavity and embedding the electronic device (Baek teaches, in Fig. 11, ¶ [0054], that after an electronic component 140 is mounted in cavity 122, a third insulating layer 130 is formed on the second insulating layer 120, the cavity 122 may be filled with the material of the third insulating layer 130, thereby embedding the electronic component 140).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide, in the Wu cavity-mounted-device structure in view of Booth, a burying insulating layer that fills the cavity around the electronic device and embeds the device, as taught by Baek (e.g., insulating/resin layer 130 filling cavity 122 around device 140), in order to securely fix/protect the cavity-mounted device and improve board integrity/reliability using a known, predictable embedded-component construction (Baek, ¶ [0054]).
Re Claim 33 (Previously Presented), Wu, Chang, Boyko, Booth and Baek disclose all the limitations of claim 32 on which this claim depends.
Baek further teaches wherein the burying insulating layer contacts the inner wall surface and the bottom surface (Baek, Fig. 11 and ¶ [0054], the cavity 122 is filled with the material of the third insulating layer 130 such that the resin/insulating material fills the cavity around the electronic component 140; as a result, the burring insulating material 130 necessarily contacts the inner wall surface of cavity 122 and the bottom surface of the cavity 122 while embedding the electronic component).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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