Prosecution Insights
Last updated: July 17, 2026
Application No. 18/263,960

METHOD FOR MANUFACTURING SILICON WAFER AND SILICON WAFER

Non-Final OA §103§112
Filed
Aug 02, 2023
Priority
Feb 25, 2021 — JP 2021-028234 +1 more
Examiner
WILCZEWSKI, MARY A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Global Wafers Japan Co. Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 835 resolved
+16.9% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
34 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
64.6%
+24.6% vs TC avg
§102
11.4%
-28.6% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 835 resolved cases

Office Action

§103 §112
DETAILED ACTION This Office action is in response to the Request for Continued Examination (RCE) and the Amendment submitted on 23 June 2026. Claims 1, 2, and 6-7 are pending in the application. Claim 3-5 have been cancelled. This application is a US national stage application under 35 USC 371 of PCT/JP2022/005929, filed on 15 February 2022. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 23 June 2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 2, 6, and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Independent claim 1 has been amended to require “configuring the RTP device to have a thermal budget”. It is unclear what this limitation actually requires. Does “configuring the RTP device to have a thermal budget” merely require providing power to the RTP device, heating the RTP device to the highest temperature of the range of heating temperature, or loading the silicon wafer into the device? Moreover, in Applicant’s specification it is disclosed that “the method performs the rapid thermal process with a thermal budget”. Hence, it is unclear what “configuring the RTP device to have a thermal budget” actually requires in the context of independent claim 1. It is also unclear what is meant by the thermal budget having “an exposure area”. Applicant’s specification does not use the phrase “an exposure area”, so it is unclear what this means in the claim. Does “an exposure area” refer to an area of the silicon wafer that is thermally processed? Since thermal budget is total quantity of thermal process, does the limitation “the thermal budget having an exposure area” refer to the total quantity of thermal process performed on an area of the silicon wafer? The language of a claim must clearly and precisely define the metes and bounds of the claimed invention, since patented claims place the public on notice of the scope of the patentee's right to exclude. It is important that a person of ordinary skill in the art be able to interpret the metes and bounds of the claims so as to understand how to avoid infringement of the patent that ultimately issues from this application. Claims 2 and 6-7 are rejected, since these claims inherit the indefiniteness of claim 1, from which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Senda et al., WO 2010/0140323, of record. With respect to claim 1, Senda et al. disclose a method for manufacturing a silicon wafer, for performing a rapid thermal process (RTP) on a silicon wafer under an atmosphere (inert gas and an oxidizing gas) by which vacancies are introduced into a silicon wafer in a chamber of an RTP device (see the Abstract and Figs. 7-9), the method comprising: configuring the RTP device (shown in Fig. 4) to have a thermal budget, the thermal budget having an exposure area which specifies heating temperatures being applied within a range of 1300 oC to 1350 oC and specifies holding time at which a highest temperature of the range is applied, wherein applying the heating temperature of 1350 oC at a maximum holding time of 20s, corresponds to 100% of the thermal budget 20s (Senda et al. disclose a holding time t at 1350 oC of not less than 1 second and not more than 60 seconds, and, more specifically, teach performing the rapid thermal process for 5 seconds in Example 1 and for 15 seconds in Example 2. Therefore, Senda et al. clearly teach a rapid thermal process in Examples 1 and 2 performed in the rapid thermal device of Fig. 4 that corresponds to 100% of the thermal budget, as required in amended claim 1, see Figs.4 and 5 and Examples 1 and 2.), performing the rapid thermal process at 53% to 65% of the thermal budget. Senda et al. disclose in Example 1 a holding time t of 5 seconds at 1350 oC, which is less than a predetermined longest holding time of 20s, see Fig. 5 and Example 1. Therefore, when the RTP is performed with a holding time less than the maximum holding time of 5 seconds, for example, 3 seconds, the rapid thermal process is performed at 60% of the thermal budget. Similarly, with respect to Example 2, which has a holding time t of 15 seconds at 1350 oC, if the rapid thermal process is performed with a holding time of less than the maximum holding time of 15 seconds, for example, 8.5 seconds, the rapid thermal process is performed at 57% of the thermal budget. The claim requires 100% of the thermal budget corresponds to applying the heating temperature of 1350 oC at a maximum holding time of 20s. In Examples 1 and 2, Senda et al. heat the silicon wafer to 1350 oC for 5 seconds and 15 seconds, respectively. Both holding times of Senda et al. are within a maximum holding time of 20s, as required in claim 1. Hence, Examples 1 and 2 of Senda correspond to 100% of the thermal budget. Hence, performing the RTP of Senda et al., for a holding time of 3 seconds in Example 1 and 8.5 seconds in Example 2, as outlined above (both holding times clearly within the range of holding times disclosed by Senda et al.) would obviously result in performing the rapid thermal process at 53% to 65% of the thermal budget. With respect to claim 2, Senda et al. disclose controlling, during the rapid thermal process, an oxygen concentration of the wafer to be 0.6 x 1018 atoms/cm3 or more and 1.0 x 1018 atoms/cm3 or less (ASTM '79) for the silicon wafer to be used in the rapid thermal process, see Example 1 Senda et al. disclose the oxygen concentration is more preferably 0.8 × 1018 atoms/cm3 or more in terms of maintaining strength as a silicon wafer, such as suppression of slip generation in RTP.. Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Senda et al., as applied to claim 1 above, in view of Park, JP 2009-016864, of record. With respect to claim 6, in the method for manufacturing a silicon wafer disclosed by Senda et al., setting for the rapid thermal process performed with the thermal budget of 53% or more and 65% or less, the holding time at 1350 °C is 0 s to 6 s (Senda et al. disclose in Example 1: “FIG. 4 shows a silicon wafer (diameter 300 mm, thickness 775 μm, oxygen concentration 1.1 × 10 .sup.18 atoms / cm3 ) obtained by slicing a silicon single crystal ingot grown in the V-rich region by the CZ method. Using such an RTP apparatus, in the heat treatment sequence as shown in FIG. 5, the first atmospheric gas FA is 100% argon, the second atmospheric gas FB is 100% oxygen, and the temperature rising rate ΔTu: The RTP treatment was performed at 30 °C./second, maximum temperature T1: 1350 ° C., temperature drop rate ΔTd: 30 °C./second, and maximum time T1 holding time t: 5 seconds.”) Senda et al. disclose the temperature raising speed is preferably 10 °C/second or more and 150 °C/second or less, as shown in Fig. 4. However, Senda et al. lack anticipation of raising the temperature from 1300°C up to 1350 °C (T1) is performed at a slower rate than a rate at which the temperature is raised from a start of heating (T0) to 1300°C, as shown in Fig. 4. In the same field of endeavor, Park discloses a method of rapid thermal annealing a silicon wafer in which the wafer is heated to 1250 oC with a temperature raising speed of 50 oC/second, as shown in Fig. 5. In light of this disclosure of Park, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the rapid thermal process performed with the thermal budget of 53% or more and 65% or less, in the known method of Senda et al., the temperature raising speed after exceeding 1300°C up to 1350 °C could be slower, for example, 30 °C./second as in Example 1 of Senda et al., than that from a start of heating to 1300°C, for example, 50 oC/second as taught by Park. With respect to claim 7, Senda et al. disclose, in the rapid thermal process, raising the temperature from a start of heating to 1300°C at the rate of 130°C/s or more (“The temperature increase rate ΔTu is preferably 10 °C/second or more and 150 ° C/second or less.”).. Response to Arguments Applicant's arguments filed 23 June 2026 have been fully considered but they are not persuasive. Applicant has argued that there is nothing in Senda which supports the Examiner's interpretation of 5 seconds being a maximum holding time or representing 100% of the thermal budget in an RTP process as alleged. However, the Examiner’s interpretation of Senda is based on amended claim 1. In amended claim 1, Applicant requires that 100% of the thermal budget corresponds to applying the heating temperature of 1350 oC at a maximum holding time of 20s. Senda et al. disclose in Example 1 a holding time t of 5 seconds at 1350 oC, which is less than a predetermined longest holding time of 20s, see Fig. 5 and Example 1. Therefore, when the RTP is performed with a holding time less than the maximum holding time of 5 seconds, for example, a holding time of 3 seconds, the rapid thermal process is performed at 60% of the thermal budget. Similarly, with respect to Example 2, which has a holding time t of 15 seconds at 1350 oC, if the rapid thermal process is performed with a holding time of less than the maximum holding time of 15 seconds, for example, a holding time of 8.5 seconds, the rapid thermal process is performed at 57% of the thermal budget. Amended claim 1 requires that 100% of the thermal budget corresponds to applying the heating temperature of 1350 oC at a maximum holding time of 20s. In Examples 1 and 2, Senda et al. heat the silicon wafer to 1350 oC for 5 seconds and 15 seconds, respectively. Both holding times of Senda et al. are within a maximum holding time of 20s, as required in claim 1. Hence, Examples 1 and 2 of Senda correspond to 100% of the thermal budget. Hence, performing the RTP of Senda et al., for a holding time of 3 seconds in Example 1 and 8.5 seconds in Example 2, as outlined above (both holding times clearly within the range of holding times disclosed by Senda et al.) would obviously result in performing the rapid thermal process at 53% to 65% of the thermal budget. The Examiner’s interpretation of 5 seconds or 15 seconds being a maximum holding time is consistent with the limitation of claim 1 as to “a maximum holding time of 20s”. Moreover, Examples I and 2 of Senda et al. clearly are commensurate with what amended claim 1 requires 100% of the thermal budget to be, since both Examples 1 and 2 apply the heating temperature of 1350 oC at a holding temperature not greater than a maximum holding time of 20s. For these reasons, Applicant’s claimed method is not deemed patentably distinct from the known method of Senda et al. as applied in this Office action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARY A. WILCZEWSKI Primary Examiner Art Unit 2898 /MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Aug 02, 2023
Application Filed
Oct 24, 2025
Non-Final Rejection mailed — §103, §112
Feb 06, 2026
Response Filed
Apr 30, 2026
Final Rejection mailed — §103, §112
Jun 23, 2026
Request for Continued Examination
Jun 25, 2026
Response after Non-Final Action
Jul 08, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.1%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 835 resolved cases by this examiner. Grant probability derived from career allowance rate.

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