DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on January 20th, 2026, has been entered.
Upon entrance of the Amendment, claims 1 and 11 were amended, and claim 13 was added. Claims 1-13 are currently pending.
Response to Arguments
Applicant’s arguments with respect to the amended feature of claim 1 have been fully considered, the amended feature is obvious to one of ordinary skill in the art and a new ground of rejection is made.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashishita (U.S. Patent Application Publication No. 2019/0103298) in view of Caldwell (U.S. Patent No. 7,573,276).
Regarding to claim 1, Hayashishita teaches an electronic component manufacturing method comprising:
an arrangement step of arranging a plurality of electronic components in a state where electrodes are exposed (Fig. 10, elements 21; [0180], lines 6-9), on a support having a substrate (Fig. 10, element 90; [0181], line 6) and a holding layer (Fig. 10, element 12; [0181], line 5), with the holding layer interposed therebetween (Fig. 10); and
an evaluation step of evaluating electric characteristics of the electronic components among the electronic components arranged on the support by simultaneously connecting the exposed electrodes and probes and performing conduction evaluation (Fig. 10, [0180], last 4 lines).
Hayashishita is silent as to the number of electronic components.
Caldwell discloses an evaluation step of evaluating electric characteristics of a large number of the electronic components by simultaneously connecting the exposed electrodes and probes and performing conduction evaluation (Fig. 10, Fig. 5-7, valuation step of evaluating electric characteristics of more than 80 electronic components A by simultaneously connecting the exposed electrodes and probes). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hayashishita in view of Caldwell to simultaneously probe a large number of the electronic components in order to reduce test time, thus to increase productivity. Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to simultaneously probe 300 or more electronic components in order to further reduce test time, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 2, Hayashishita teaches the evaluation step is a step of performing the conduction evaluation in a state where the electronic components are heated ([0178], last line).
Regarding to claim 3, Hayashishita teaches a segmentation step of segmenting a precursor electronic component on another support different from the support before the arrangement step to obtain the electronic components (Figs. 8-9).
Regarding to claim 4, Hayashishita teaches the holding layer has a characteristic that a holding force is reduced by heat application or energy ray irradiation ([0127], lines 10-14, the adhesive layer is heated to above 75 degrees to reduce holding force, thus the die can be removed from the substrate).
Regarding to claim 6, Hayashishita teaches the substrate is made of a metal ([0257], line 1).
Regarding to claim 7, Hayashishita teaches the support includes a component manufacturing film adhered to one surface side of the substrate, and the component manufacturing film includes a resin base layer (Fig. 10, element 11, [0098], lines 1-3; [0123], lines 1-4), the holding layer provided on one surface side of the resin base layer (Fig. 10, the holding layer 12 provided on one surface side of the resin base layer 11), and a joint layer that is provided on an opposite side of the resin base layer and bonds the component manufacturing film to the substrate (Fig. 10).
Regarding to claim 8, Hayashishita teaches the resin base layer has a linear thermal expansion coefficient of 100 ppm/K or less ([0091], lines 1-3, thermal expansion coefficient of polyester, polyamide, polycarbonate, or acrylic resin, is known 100 ppm/K or less).
Regarding to claim 9, Hayashishita teaches the resin base layer has a melting point of 180°C or higher and a tensile elastic modulus of 50 MPa or more at a temperature of 160°C ([0091], lines 1-3, melting point of polyester, polyamide, polycarbonate, or acrylic resin, is known 180°C or higher, tensile elastic modulus of polyester, polyamide, polycarbonate, or acrylic resin, is known 50 MPa or more at a temperature of 160°C).
Regarding to claim 10, Caldwell discloses the number of the electronic components to be arranged is 100 or more (Fig. 6).
Regarding to claim 11, Hayashishita teaches a component manufacturing film used in the electronic component manufacturing method according to claim 1, component manufacturing film comprising: a resin base layer (Fig. 10, element 11); the holding layer provided on one surface side of the resin base layer (Fig. 10, element 12); and a joint layer that is provided on an opposite side of the resin base layer and bonds the component manufacturing film to the substrate (Fig. 10, joint layer between element 11 and element 90).
Regarding to claim 12, Hayashishita teaches a component manufacturing tool used in the electronic component manufacturing method according to claim 1, the component manufacturing tool comprising the substrate (Fig. 10, element 90); and the holding layer provided on one surface of the substrate (Fig. 10, element 12).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hayashishita (U.S. Patent Application Publication No. 2019/0103298) and Caldwell (U.S. Patent No. 7,573,276), as applied to claim 1 above, further in view of Miki et al. (U.S. Patent Application Publication No. 2013/0029147).
Regarding to claim 5, Hayashishita as modified does not explicitly disclose the holding layer includes thermally expandable particles and has a characteristic that a holding force is reduced by heating. Miki discloses a holding layer includes thermally expandable particles and has a characteristic that a holding force is reduced by heating ([0132], last 4 lines). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hayashishita in view of Miki to include thermally expandable particles having a characteristic that a holding force is reduced by heating in the holding layer, in order to reduce detachment time.
Claims 1-2, 4, 6, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson (U.S. Patent No. 8,889,526) in view of Henson et al. (U.S. Patent No. 7,649,366).
Regarding to claim 1, Johnson teaches an electronic component manufacturing method comprising:
an arrangement step of arranging a plurality of electronic components in a state where electrodes are exposed, on a support having a substrate and a holding layer, with the holding layer interposed therebetween (Fig. 13); and
an evaluation step of evaluating electric characteristics of the electronic components among the electronic components arranged on the support by simultaneously connecting the exposed electrodes and probes and performing conduction evaluation (Fig. 13, column 6, lines 26-28).
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Johnson is silent as to the number of electronic components.
Henson discloses an evaluation step of evaluating electric characteristics of a large number of the electronic components by simultaneously connecting the exposed electrodes and probes and performing conduction evaluation (Figs 7-8, column 8, lines 27-31 valuation step of evaluating electric characteristics of more than 80 electronic components by simultaneously connecting the exposed electrodes and probes. As shown in Fig. 7, about 120 dies 1 are simultaneously probed). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Johnson in view of Henson to simultaneously probe a large number of the electronic components in order to reduce test time, thus to increase productivity. Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to simultaneously probe 300 or more electronic components in order to further reduce test time, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
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Regarding to claim 2, Johnson teaches the evaluation step is a step of performing the conduction evaluation in a state where the electronic components are heated (column 4, lines 33-37).
Regarding to claim 4, Johnson teaches the holding layer has a characteristic that a holding force is reduced by heat application or energy ray irradiation (column 6, lines 65-67).
Regarding to claim 6, Johnson teaches the substrate is made of a metal (vacuum chuck 202 is metal).
Regarding to claim 10, Henson discloses the number of the electronic components to be arranged is 100 or more (Fig. 7).
Regarding to claim 12, Johnson teaches a component manufacturing tool used in the electronic component manufacturing method according to claim 1, the component manufacturing tool comprising the substrate (Fig. 13, element 202); and the holding layer provided on one surface of the substrate (Fig. 13).
Allowable Subject Matter
Claim 13 is allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 13, the prior art fails to anticipate or render obvious the combination of limitations including “an evaluation step of evaluating electric characteristics of 300 or more of the electronic components arranged on the support by simultaneously connecting the exposed electrodes and probes and performing conduction evaluation while the electronic components are heated to l 50°C or higher; wherein the substrate is formed using a heat-resistant resin, has a melt peak temperature of 200°C or higher as measured in accordance with JIS K7121, and has a tensile elastic modulus E' (160) of 100 MPa or more at a temperature of 160°C, and wherein the holding layer is formed of an adhesive, and the adhesive has a 180° peeling adhesive force of 0.3 N/25 mm or more and 8 N/25 mm or less, measured in accordance with JISZ0237 except that the adherend used in the measurement is a silicon wafer” in combination with the rest of limitations recited in claim 13.
For a purpose of clarification, the examiner suggests recitation the “in accordance with JIS K7121” to be amended to “in accordance with JIS K7121 Industrial Standard”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VU A VU/Primary Examiner, Art Unit 2897