DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continuity Information
The instant application is a national stage entry of PCT/JP2021/047358, filed 21 DEC 2021.
Priority
Acknowledgment is made of applicants’ claim for foreign priority based on applications filed in JAPAN on 10 FEB 2021. It is noted that applicants have filed a certified copy of said application as required by U.S.C 119, which papers have been placed of record in the file. See 24 NOV 2023 submission.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3 AUG 2023 was filed before the mailing of a first Office action on the merits. The submission follows provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows (Graham Factors):
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as obvious over DELACRUZ et al. (US 20180173600; below, “DELACRUZ” – 3 AUG 2023 IDS noted prior art reference) with evidence from or in view of Ueda (JP 54099581; below, “Ueda” – 3 AUG 2023 IDS noted prior art reference). At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 1 {2}, DELACRUZ, in Figures 1 to 2F and related text, e.g., Abstract, paragraphs [0002] to [0078], discloses (see below for: an artificial intelligence (AI) module) comprising:
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a first semiconductor chip (200 - Data Processing Unit, DPU), wherein
the first semiconductor chip (200) includes:
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a plurality of first processing units (computation blocks 220) each of which performs a predetermined operation; and
a plurality of second processing units (memory blocks 222) each including memory, and
the plurality of first processing units (compute blocks 220) and the plurality of second processing units (memory blocks 222) are arranged in a checkered pattern (Fig. 2C) or in a striped pattern in plan view; {first processing units each perform the predetermined operation based on a machine learning model}.
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DELACRUZ is silent regarding DPU 200 being an AI module {machine learning module}. However, DELACRUZ, in Abstract, [0002], and [0004], teaches that DPUs are used to constitute hardware for artificial intelligence applications. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify DELACRUZ to include an AI module; {the plurality of first processing units performing based on a machine learning model}. This is because the modification allows DPUs to offload networking tasks, allowing processors like graphics processing units (GPUs) and central processing units (CPUs) to operate more efficiently. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
Claims 3-9, 11, 12, and 15 are rejected under 35 U.S.C. 103 as obvious over DELACRUZ with evidence from or in view of Ueda with further evidence from or in further view of Kuroda (JP 2012-156186; below, “Kuroda” – 3 AUG 2023 IDS noted prior art reference). MPEP § 2143(A)-(G).
RE 3, modified DELACRUZ is silent regarding the AI module according to claim 1, further comprising:
(see Kuroda for: a second semiconductor chip stacked on the first semiconductor chip (200), wherein
the second semiconductor chip includes):
a plurality of third processing units each of which performs a predetermined operation (computation blocks 220 of DELACRUZ); and
a plurality of fourth processing units each including memory (memory blocks 222 of DELACRUZ), and
the plurality of third processing units (computation blocks 220 of DELACRUZ) and the plurality of fourth processing units are arranged in a checkered pattern or in a striped pattern in plan view (see Fig. 2C of DELACRUZ).
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Kuroda, in FIG. 1 and related text, e.g., Abstract, paragraphs [0027] to [0030], teaches a second semiconductor chip (12 or 13) stacked on a first semiconductor chip (11). Chips 11, 12, 13 include power-supplying through-hole electrodes (6, 7) passing through.
It would have been obvious … to modify DELACRUZ with evidence from or in view of Ueda to stack a second DPU on the first DPU. This is because the modification provides stacked DPUs in which power supply voltage drops within the chips is reduced (Kuroda [0028]. Furthermore, it would have been obvious because all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 4, modified DELACRUZ discloses the AI module according to claim 3, wherein
the plurality of third processing units (computation blocks 220 of DELACRUZ) each perform the predetermined operation based on a machine learning model.
RE 5, modified DELACRUZ discloses the AI module according to claim 3, wherein
the first semiconductor chip (200) further includes a first communication unit (e.g., coil 2/3), and
the second semiconductor chip (2nd DPU) further includes a second communication unit that communicates with the first communication unit.
RE 6, modified DELACRUZ discloses the AI module according to claim 5, wherein
the first communication unit (coil 2/3) and the second communication unit (coil 2/3) each include an antenna having a coil shape (Kuroda’s FIG. 1, [0030]).
RE 7, modified DELACRUZ discloses the AI module according to claim 6, wherein
the first communication unit (coil 2/3) and the second communication unit (coil 2/3) communicate with each other through the antenna of the first communication unit and the antenna of the second communication unit being inductively coupled (Kuroda’s FIG. 1, [0030]).
RE 8, modified DELACRUZ discloses the AI module according to claim 5, wherein
the plurality of first processing units (computation blocks 220) correspond one-to-one with the plurality of third processing units (computation blocks 220 of DELACRUZ) and overlap the corresponding third processing units (computation blocks 220 of DELACRUZ) in plan view, and
the plurality of second processing units (memory blocks 222) correspond one-to-one with the plurality of fourth processing units (memory blocks 222 of DELACRUZ) and overlap the corresponding fourth processing units (memory blocks 222 of DELACRUZ) in plan view.
RE 9, modified DELACRUZ discloses the AI module according to claim 8, wherein
the first communication unit overlaps one of the plurality of second processing units (memory blocks 222) in plan view, or
the second communication unit overlaps one of the plurality of fourth processing units (memory blocks 222 of DELACRUZ) in plan view.
RE 11, modified DELACRUZ discloses the AI module according to claim 5, wherein
the first semiconductor chip (200) further includes one or more fifth processing units (memory blocks 222 of DELACRUZ) each including memory,
the second semiconductor chip (2nd DPU) further includes one or more sixth processing units (memory blocks 222 of DELACRUZ) each including memory, and
the one or more fifth processing units (memory blocks 222 of DELACRUZ) correspond one-to-one with the one or more sixth processing units (memory blocks 222 of DELACRUZ) and overlap the corresponding sixth processing units (memory blocks 222 of DELACRUZ) in plan view.
RE 12, modified DELACRUZ discloses the AI module according to claim 11, wherein
the first communication unit overlaps one of the one or more fifth processing units (memory blocks 222 of DELACRUZ) in plan view, and
the second communication unit overlaps one of the one or more sixth processing units (memory blocks 222 of DELACRUZ) in plan view.
RE 15, modified DELACRUZ discloses the AI module according to claim 3, further comprising:
a through via for supplying power to the second semiconductor chip (2nd DPU), the through via passing (e.g., 6, 7 of Kuroda’s FIG. 1) through the first semiconductor chip (200).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as obvious over DELACRUZ with evidence from or in view of Ueda with further evidence from or in further view of Kuroda with still further evidence from or in still further view of Morimoto et al. (WO 2012157167; below, “Morimoto” – 3 AUG 2023 IDS noted prior art reference). MPEP § 2143(A)-(G).
RE 13, modified DELACRUZ is silent regarding the AI module according to claim 3, wherein
the first semiconductor chip (200) further includes a first semiconductor substrate including a first main surface and a second main surface that face opposite directions,
the plurality of first processing units (computation blocks 220) and the plurality of second processing units (memory blocks 222) are disposed at positions closer to the first main surface of the first semiconductor substrate than to the second main surface,
the second semiconductor chip (2nd DPU) further includes a second semiconductor substrate including a third main surface and a fourth main surface that face opposite directions,
the plurality of third processing units (computation blocks 220 of DELACRUZ) and the plurality of fourth processing units (memory blocks 222 of DELACRUZ) are disposed at positions closer to the third main surface of the second semiconductor substrate than to the fourth main surface, and
the first semiconductor chip (200) and the second semiconductor chip (2nd DPU) are (see Morimoto for: stacked such that the first main surface and the third main surface face each other).
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Morimoto, in FIGS. 1-4 and related text, e.g., paragraphs [0019] to [0044], teaches a three-dimensional integrated circuit formed by stacking semiconductor chips (10) in which one semiconductor chip (10) is inverted and stacked on the matching semiconductor chip (10).
It would have been obvious … to modify DELACRUZ with evidence from or in view of Ueda with further evidence from or in further view of Kuroda to invert one DPU and stack it on a matching, second DPU. This is because the modification provides stacked-DPU device in which an efficiency of a circuit is increased while reducing power consumption. Furthermore, it would have been obvious because all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
RE 14, modified DELACRUZ discloses the AI module according to claim 13, further comprising:
a third semiconductor chip (3rd DPU, Kuroda’s FIG. 1 (number of stacked chips not particularly limited)) stacked on the second semiconductor chip (2nd DPU); and
a fourth semiconductor chip (4th DPU, Kuroda’s FIG. 1) stacked on the third semiconductor chip, wherein
the third semiconductor chip (3rd DPU) includes:
a third semiconductor substrate including a fifth main surface and a sixth main surface that face opposite directions;
a plurality of seventh processing units (computation blocks 220 of DELACRUZ) each of which performs a predetermined operation; and
a plurality of eighth processing units (memory blocks 222 of DELACRUZ) each including memory,
the plurality of seventh processing units (computation blocks 220 of DELACRUZ) and the plurality of eighth processing units (memory blocks 222 of DELACRUZ) are disposed at positions closer to the fifth main surface of the third semiconductor substrate than to the sixth main surface, and are arranged in a checkered pattern or in a striped pattern in plan view,
the fourth semiconductor chip (4th DPU) includes:
a fourth semiconductor substrate including a seventh main surface and an eighth main surface that face opposite directions;
a plurality of ninth processing units (computation blocks 220 of DELACRUZ) each of which performs a predetermined operation; and
a plurality of tenth processing units (memory blocks 222 of DELACRUZ) each including memory,
the plurality of ninth processing units (computation blocks 220 of DELACRUZ) and the plurality of tenth processing units (memory blocks 222 of DELACRUZ) are disposed at positions closer to the seventh main surface of the fourth semiconductor substrate than to the eighth main surface, and are arranged in a checkered pattern or in a striped pattern in plan view,
(see Morimoto for: the third semiconductor chip and the fourth semiconductor chip are stacked such that the fifth main surface and the seventh main surface face each other, and the second semiconductor chip (2nd DPU) and the third semiconductor chip are stacked such that the fourth main surface and the sixth main surface face each other (Morimoto’s FIGS. 1-4)).
Claims 1-9 and 11-15 are rejected.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon rejected base claim 1 but would be allowable if rewritten in independent form including all of the limitations of the base claims and any intervening claims.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon, Bartley et al. (US 20100271071), is considered pertinent to applicants’ disclosure. Bartley et al. does not teach, inter alia, a plurality of first processing units (operation blocks 211) each of which performs a predetermined operation; and a plurality of second processing units (memory blocks 221) each including memory, and the plurality of first processing units (operation blocks 211) and the plurality of second processing units (memory blocks 221) are arranged in a checkered pattern (FIG. 3B) or in a striped pattern in plan view.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is (571) 270-3322. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez, can be reached on (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815