DETAILED ACTION
This office action is in response to the application filed on August 3, 2023. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/3/2023 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the K pads of the first functional chip being interconnected with a second functional chip" in the 8th line of claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the K pads of the second functional chip being interconnected with the first functional chip” in the 16th line of claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the K pads of the first functional chip are electrically connected with the K pads of the second functional chip in a one-to-one correspondence” in the 19th line of claim. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-3 depend from Claim 1, thus inherit the deficiencies identified supra. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (WO 2021/146860) in view of Khandros (US 8,324,725).
With respect to Claim 1, Lu discloses (Fig. 3) most aspects of the current invention including a three-dimensional integrated system with a compatible chip (10), comprising:
a first chip (101), provided with a first front surface and a first back surface arranged oppositely, the first front surface comprising a first area and a second area, the second area being arranged around the first area, a first functional chip (110) being arranged on the first area, the first functional chip being provided with pads, pads of the first functional chip being interconnected with a second functional chip (130) (par 91)
a second chip (103), provided with a second front surface and a second back surface arranged oppositely, the second front surface comprising a third area and a fourth area, the fourth area being arranged around the third area, the second functional chip being arranged on the third area, pads of the second functional chip being interconnected with the first functional chip
wherein the first chip is aligned and bonded with the second chip through the one-to-one correspondence bonding of the first pads and M second pads, and the pads of the first functional chip are electrically connected with the pads of the second functional chip in a one-to-one correspondence
However, Lu fails to disclose M, N, P and K are respectively integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, M=N+P-K.
On the other hand, and in the same field of endeavor, Khandros teaches (Fig. 9-11) a three-dimensional integrated system with a compatible chip comprising a first chip (1104), provided with a first front surface and a first back surface arranged oppositely, the first front surface comprising a first area and a second area, and a third area, the second area being arranged around the first area, the third area being arranged around the second area, a first functional chip (1018) being arranged on the first area, first pads (1038) being arranged on the second area, second pads (1040) being arranged on the third area, the first functional chip being provided with third pads, the third pads being electrically connected with the second pads in a one-to-one correspondence, the first pads being electrically connected with the second pads in a one-to-one correspondence, and the third pads of the first functional chip being interconnected with a second functional chip (1016), the second functional chip, provided with a second front surface and a second back surface arranged oppositely and pads of the second functional chip being interconnected with the first functional chip.
Additionally, Khandros teaches the pads are respectively integers greater than or equal to 2 and Khandros teaches such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the three-dimensional integrated system with a compatible chip as claimed by the applicant and including the pads are respectively integers greater than or equal to 2 in the device of Lu, as taught by Khandros because such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
With respect to Claim 2, Khandros teaches (Fig. 9-11) the three-dimensional integrated system with the compatible chip according to claim 1, wherein the M first pads are arranged around the first functional chip, the M second pads are arranged around the second functional chip, and the M first pads on the second area are aligned with the M second pads on the fourth area one by one.
With respect to Claim 3, Khandros teaches (Fig. 9-11) the three-dimensional integrated system with the compatible chip according to claim 1, wherein M through holes are arranged on the first back surface of the first chip, and the M through holes correspond to expose the M first pads one by one.
With respect to Claim 4, Lu discloses (Fig. 6) most aspects of the current invention including a three-dimensional integrated system with a compatible chip (20), comprising:
a first chip (210), provided with a first front surface and a first back surface arranged oppositely, the first front surface comprising a first area, a second area and a third area, the second area being arranged around the first area, the third area being arranged around the second area, a first functional chip (210/CPU chip) being arranged on the first area, first pads being arranged on the second area, second pads being arranged on the third area, the first functional chip being provided with pads, the pads of the first functional chip being electrically connected with the second pads in a one-to-one correspondence, the first pads being electrically connected with the second pads in a one-to-one correspondence, and pads of the first functional chip being interconnected with a second functional chip (220/GPU chip) (par 143,147)
the second functional chip, provided with a second front surface and a second back surface arranged oppositely, p pads being electrically drawn out from the second front surface, and pads of the second functional chip being interconnected with the first functional chip; (par 153-155)
wherein the pads of the second functional chip are connected with the first pads in a one-to-one correspondence, so that the second functional chip is arranged on the second area of the first chip, and the pads of the first functional chip are electrically connected with the pads of the second functional chip in a one-to-one correspondence
However, Lu fails to disclose m, n, p, k are respectively integers greater than or equal to 2, and n<m<n+p, p<m<n+p, k<n, k<p, m=n+p-k.
On the other hand, and in the same field of endeavor, Khandros teaches (Fig. 9-11) a three-dimensional integrated system with a compatible chip comprising a first chip (1104), provided with a first front surface and a first back surface arranged oppositely, the first front surface comprising a first area and a second area, and a third area, the second area being arranged around the first area, the third area being arranged around the second area, a first functional chip (1018) being arranged on the first area, first pads (1038) being arranged on the second area, second pads (1040) being arranged on the third area, the first functional chip being provided with third pads, the third pads being electrically connected with the second pads in a one-to-one correspondence, the first pads being electrically connected with the second pads in a one-to-one correspondence, and the third pads of the first functional chip being interconnected with a second functional chip (1016), the second functional chip, provided with a second front surface and a second back surface arranged oppositely and pads of the second functional chip being interconnected with the first functional chip.
Additionally, Khandros teaches the pads are respectively integers greater than or equal to 2 and Khandros teaches such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the three-dimensional integrated system with a compatible chip as claimed by the applicant and including the pads are respectively integers greater than or equal to 2 in the device of Lu, as taught by Khandros because such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
With respect to Claim 5, Khandros teaches (Fig. 9-11) the three-dimensional integrated system with the compatible chip according to claim 4, wherein the second pads are arranged around the first functional chip and the first pads, and the first pads in the second area are aligned with the second pads of the second functional chip one by one
With respect to Claim 6, Khandros teaches (Fig. 9-11) the three-dimensional integrated system with the compatible chip according to claim 4, wherein through holes are arranged on the first back surface of the first chip, and the through holes expose the m second pads one by one.
With respect to Claim 7, Lu discloses (Fig. 3) most aspects of the current invention including a manufacturing method of a three-dimensional integrated system with a compatible chip (10), comprising:
obtaining a layout design of a first functional chip (110) and a layout design of the second functional chip (130)
determining a number N of pads of the first functional chip, a number P of pads of the second functional chip, and a number K of pads that need to be electrically connected between the first functional chip and the second functional chip according to the layout design of the first functional chip and the layout design of the second functional chip (par 91)
expanding the layout design of the first functional chip, arranging M first pads around a periphery of the first functional chip, and electrically connecting N of the first pads with the N pads of the first functional chip in a one-to-one correspondence to obtain a layout design of a first chip (101) (par 91)
expanding the layout design of the second functional chip, arranging M second pads around a periphery of the second functional chip, and electrically connecting P of the second pads with the P pads of the second functional chip in a one-to-one correspondence to obtain a layout design of a second chip (103)
manufacturing the first chip with reference to the layout design of the first chip
manufacturing the second chip with reference to the layout design of the second chip
aligning and bonding the first chip and the second chip through a one-to-one corresponding bonding of the M first pads and the M second pads, and electrically connecting the K pads of the first functional chip with the K pads of the second functional chip in a one-to-one correspondence
However, Lu fails to disclose M, N, P and K are respectively integers greater than or equal to 2, and N<M<N+P, P<M<N+P, K<N, K<P, M=N+P-K.
On the other hand, and in the same field of endeavor, Khandros teaches (Fig. 9-11) a manufacturing method of a three-dimensional integrated system with a compatible chip comprising a first chip (1104), provided with a first front surface and a first back surface arranged oppositely, the first front surface comprising a first area and a second area, the second area being arranged around the first area, a first functional chip (1018) being arranged on the first area, first pads (1038) being arranged on the second area, the first functional chip being provided with third pads, the third pads being electrically connected with the second pads in a one-to-one correspondence, the first pads being electrically connected with the second pads in a one-to-one correspondence, and the third pads of the first functional chip being interconnected with a second functional chip (1016), the second functional chip, provided with a second front surface and a second back surface arranged oppositely and pads of the second functional chip being interconnected with the first functional chip.
Additionally, Khandros teaches the pads are respectively integers greater than or equal to 2 and Khandros teaches such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the three-dimensional integrated system with a compatible chip as claimed by the applicant and including the pads are respectively integers greater than or equal to 2 in the device of Lu, as taught by Khandros because such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
With respect to Claim 8, Khandros teaches (Fig. 9-11) the manufacturing method of the three-dimensional integrated system with the compatible chip according to claim 7, wherein the first chip is provided with a first front surface and a first back surface arranged oppositely, the first functional chip and the M first pads are formed on the first front surface of the first chip, and the manufacturing method further comprises: thinning the first back surface of the first chip; etching the first back surface of the first chip, forming M through holes on the first back surface of the first chip, and the M through holes exposing the M first pads in a one-to-one correspondence; and dicing, packaging and testing in sequence to obtain the three-dimensional integrated system.
With respect to Claim 9, Lu discloses (Fig. 6) most aspects of the current invention including a manufacturing method of a three-dimensional integrated system with a compatible chip (20), comprising:
obtaining a layout design of a first functional chip (210/CPU chip) and a layout design of the second functional chip (220/GPU chip)
determining a number n of pads of the first functional chip, a number p of pads of the second functional chip, and a number k of pads that need to be electrically connected between the first functional chip and the second functional chip according to the layout design of the first functional chip and the layout design of the second functional chip (par 143,147)
expanding the layout design of the first functional chip, designing a chip connection area outside the first functional chip, arranging p first pads on the chip connection area, arranging m second pads around the first functional chip and the p first pads, providing the first functional chip with n pads, electrically connecting the n pads of the first functional chip with n of the second pads in a one-to-one correspondence, and electrically connecting the p first pads with p of the second pads in a one-to-one correspondence to obtain a layout design of a first chip
manufacturing the first chip with reference to the layout design of the first chip (210)
manufacturing the second functional chip with reference to the layout design of the second functional chip, and electrically drawing out the p pads from a front surface of the second functional chip
arranging the second functional chip on the chip connection area of the first chip through a one-to-one correspondence connection between the p pads of the second functional chip and the p first pads, and electrically connecting the k pads of the first functional chip with the k pads of the second functional chip in a one-to-one correspondence
However, Lu fails to disclose m, n, p, k are respectively integers greater than or equal to 2, and n<m<n+p, p<m<n+p, k<n, k<p, m=n+p-k.
On the other hand, and in the same field of endeavor, Khandros teaches (Fig. 9-11) a manufacturing method of a three-dimensional integrated system with a compatible chip comprising a first chip (1104), provided with a first front surface and a first back surface arranged oppositely, the first front surface comprising a first area and a second area, and a third area, the second area being arranged around the first area, the third area being arranged around the second area, a first functional chip (1018) being arranged on the first area, first pads (1038) being arranged on the second area, second pads (1040) being arranged on the third area, the first functional chip being provided with third pads, the third pads being electrically connected with the second pads in a one-to-one correspondence, the first pads being electrically connected with the second pads in a one-to-one correspondence, and the third pads of the first functional chip being interconnected with a second functional chip (1016), the second functional chip, provided with a second front surface and a second back surface arranged oppositely and pads of the second functional chip being interconnected with the first functional chip.
Additionally, Khandros teaches the pads are respectively integers greater than or equal to 2 and Khandros teaches such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the three-dimensional integrated system with a compatible chip as claimed by the applicant and including the pads are respectively integers greater than or equal to 2 in the device of Lu, as taught by Khandros because such arrangement reduces the complexity of interconnecting the dies with each other and with the wiring substrate, and further also reduce cross-talk problems.
With respect to Claim 10, Khandros teaches (Fig. 9-11) the manufacturing method of the three-dimensional integrated system with the compatible chip according to claim 9, wherein the first chip is provided with a first front surface and a first back surface arranged oppositely, the first functional chip, the p first pads and the m second pads are formed on the first front surface of the first chip, and the manufacturing method further comprises: thinning the first back surface of the first chip; etching the first back surface of the first chip, forming m through holes on the first back surface of the first chip, and the m through holes exposing the m second pads in a one-to-one correspondence; and dicing, packaging and testing in sequence to obtain the three-dimensional integrated system.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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