DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 11, 17, 19, 22 and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito JP 2018-164066 A (see attached English Translation).
Regarding claims 1, 6, 11 and 17, Ito discloses:
A semiconductor package (Fig. 3; 200), comprising:
a first interposer (120) that includes a first face (top) and a second face (bottom) situated on an opposite side from the first face;
a second interposer (130) that includes a third face (top) and a fourth face (bottom) situated on an opposite side from the third face, and that is arrayed with the first interposer in a first direction;
a third interposer (140) that includes a fifth face (top) and a sixth face (bottom) situated on an opposite side from the fifth face, and that is situated between the first interposer and the second interposer in the first direction;
a first semiconductor element (150) that overlaps the first face and the fifth face in plan view; and
a second semiconductor element (160) that overlaps the third face and the fifth face in plan view, wherein
the third interposer includes wiring (140 interconnect bridge) that electrically connects the first semiconductor element and the second semiconductor element.
(claim 6) a third semiconductor element (110).
(claim 11) a first through via (120 shown with through vias).
(claim 17) interposers 120 and 130 without an inorganic insulating material on the faces.
Regarding claims 19 and 22, Ito discloses:
A manufacturing method of a semiconductor package (Figs. 1-3), the manufacturing method comprising:
a disposing step of disposing a first interposer (120) that includes a first face (top) and a second face (bottom) situated on an opposite side from the first face, a second interposer (130) that includes a third face (top) and a fourth face (bottom) situated on an opposite side from the third face, and a third interposer (140) that includes a fifth face (top) and a sixth face (bottom) situated on an opposite side from the fifth face;
a first mounting step of mounting a first semiconductor element (150) so as to overlap the first face and the fifth face in plan view; and
a second mounting step of mounting a second semiconductor element (160) so as to overlap the third face and the fifth face in plan view, wherein
the second interposer is arrayed with the first interposer in a first direction,
the third interposer is situated between the first interposer and the second interposer in the first direction, and
the third interposer includes wiring (140 interconnect bridge) that electrically connects the first semiconductor element and the second semiconductor element.
(claim 22) a third semiconductor element (110).
Regarding claim 26, Ito discloses:
An interposer group (Fig. 3) onto which a first semiconductor element (150) and a second semiconductor element (160) are mounted, the interposer group comprising:
a first interposer (120) that includes a first face (top) and a second face (bottom) situated on an opposite side from the first face;
a second interposer (130) that includes a third face (top) and a fourth face (bottom) situated on an opposite side from the third face, and that is arrayed with the first interposer in a first direction; and
a third interposer (140) that includes a fifth face (top) and a sixth face (bottom) situated on an opposite side from the fifth face, and that is situated between the first interposer and the second interposer in the first direction, wherein
the first semiconductor element is mounted so as to overlap the first face and the fifth face in plan view,
the second semiconductor element is mounted so as to overlap the third face and the fifth face in plan view, and
the third interposer includes wiring (140 interconnect bridge) that electrically connects the first semiconductor element and the second semiconductor element.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, as applied to claims 1 and 19 above, in view of Komiyama JP 11-177020 A (see attached English Translation).
Regarding claims 2, 3, and 20, Yeh does not disclose:
(claim 2) wherein the first interposer includes a first cavity, and the semiconductor package further comprises a first internal semiconductor element that is situated in the first cavity. (claim 3) wherein the first cavity is formed in the first face, and the first internal semiconductor element is electrically connected to the first semiconductor element; and (claim 20) wherein the first interposer includes a first cavity, and the first mounting step includes a step of disposing, in the first cavity, a first internal semiconductor element that is connected to the first semiconductor element.
Komiyama discloses a publication from a similar field of endeavor in which:
(claim 2) wherein an interposer (10) includes a first cavity (17), and the semiconductor package further comprises a first internal semiconductor element (18) that is situated in the first cavity. (claim 3) wherein the first cavity is formed in a first face (top of 12), and the first internal semiconductor element is electrically connected to a first semiconductor element (16); and (claim 20) wherein a interposer (10) includes a first cavity (17), and the first mounting step includes a step of disposing, in the first cavity, a first internal semiconductor element (18) that is connected to a first semiconductor element (16) (refer to Fig. 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a similar cavity with an internal semiconductor element of Komiyama within the first face of the interposer of Yeh such that it is electrically connected to the first semiconductor to further add functionality/performance to the overall semiconductor package.
Claims 7, 8 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, as applied to claims 6 and 22 above, in view of Hwang et al. US 2010/0327439 A1.
Regarding claims 7, 8 and 23, Yeh does not disclose:
(claim 7) further comprising a wiring substrate that includes a substrate and a pad that is electrically connected to the third semiconductor element; (claim 8) wherein the substrate contains an organic material; and (claim 23) further comprising a step of disposing a wiring substrate including a substrate and a pad, such that the pad of the wiring substrate is electrically connected to the third semiconductor element.
Hwang discloses a publication from a similar field of endeavor in which:
(claim 7) further comprising a wiring substrate (10) that includes a substrate (10) and a pad (12) that is electrically connected to a third semiconductor element (20’); (claim 8) wherein the substrate contains an organic material (10 PCB); and (claim 23) further comprising a step of disposing a wiring substrate (10) including a substrate (10) and a pad (12), such that the pad of the wiring substrate is electrically connected to the third semiconductor element.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to connect the wiring substrate of Hwang to the third semiconductor element of Yeh to allow the semiconductor package to be connected external to other electrical modules for applications such as computers, mobile devices, etc.
Claims 13-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh, as applied to claim 1 above, in view of Wu et al. WO 2013/119309 A1.
Regarding claims 13-16 and 18, Yeh does not disclose:
(claim 13) wherein the third interposer includes a third through via; (claim 14) wherein the third interposer includes a redistribution layer that is situated on the fifth face, and that includes an insulating layer and wiring, and the insulating layer contains an organic insulating material; (claim 15) wherein the organic insulating material contains polyimide, epoxy-based resin, or acrylic-based resin; (claim 16) wherein the insulating layer contains a filler made of an inorganic material; and (claim 18) wherein the first interposer includes a first substrate made of an inorganic material, and a redistribution layer that is situated on one of the faces of the first substrate and that includes an insulating layer and wiring, and the second interposer includes a second substrate made of an inorganic material, and a redistribution layer that is situated on one of the faces of the second substrate and that includes an insulating layer and wiring.
Wu discloses a publication from a similar field of endeavor in which:
(claim 13) wherein a interposer (1220 or 1225) includes a through via (1335); (claim 14) wherein a third interposer (1220 or 1225) includes a redistribution layer (1310 or 1320) that is situated on the face, and that includes an insulating layer (unnumbered layer of 1310 or 1320) and wiring (1315 or 1325), and the insulating layer contains an organic insulating material (unnumbered layer of 1310 or 1320); (claim 15) wherein the organic insulating material contains polyimide, epoxy-based resin, or acrylic-based resin (unnumbered layer of 1310 or 1320); (claim 16) wherein the insulating layer contains a filler made of an inorganic material (unnumbered layer of 1310 or 1320); and (claim 18) wherein the interposer (1220 or 1225) includes a substrate made of an inorganic material, and a redistribution layer (1310 or 1320) that is situated on one of the faces of the substrate and that includes an insulating layer (unnumbered layer of 1310 or 1320) and wiring (1315 or 1325), and the another interposer (1220 or 1225) includes a another substrate made of an inorganic material, and a redistribution layer (1310 or 1320) that is situated on one of the face of the another substrate and that includes an insulating layer (unnumbered layer of 1310 or 1320) and wiring (1315 or 1325).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the both the through-vias and redistribution layers of Wu on the various interposer components of Yeh to allow further interconnection configurations within the semiconductor package.
Allowable Subject Matter
Claims 9 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claim 9 stating “wherein the first interposer includes a cavity formed in the second face, and the semiconductor package further comprises a first internal element that is situated in the cavity formed in the second face and that is electrically connected to the third semiconductor element”; and of claim 24 stating “further comprising: a preparation step of preparing a third semiconductor element, wherein, in the disposing step, the first interposer, the second interposer, and the third interposer are disposed such that the second face, the fourth face, and the sixth face overlap the third semiconductor element in plan view”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893