DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Figures 1, 4k, 4l, and 4m: 109a, 109b, 109c.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore,
the language of claim 3:
a side of at least a part of the source electrode near the active layer contacts the first conductor sub-portion, and a side of at least a part of the drain electrode near the active layer contacts the second conductor sub-portion;
and
(2) the language of claim 7, whose parent claims are directed to Figure 2:
wherein in a plane parallel to the substrate, along a direction from the channel portion to the first conductor sub-portion, an edge of a side of the source electrode away from the gate electrode extends beyond an edge of a side of the first conductor sub-portion away from the channel portion; and in the plane parallel to the substrate, along a direction from the channel portion to the second conductor sub-portion, an edge of a side of the drain electrode away from the gate electrode extends beyond an edge of a side of the second conductor sub-portion away from the channel portion
(emphasis added)
must be shown or the feature(s) canceled from the claim(s). These features are not in Figure 2. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because:
The description on page 14, paragraph 102, lines 5-10 of the paragraph is not shown in the drawings.
The steps (S410-S460) listed in page 22, paragraphs 139, 131, 143; page 23, paragraph 145, 148, 149, are not shown in the drawings. Compare with Figure 3.
A description of Figure 4a is missing.
The steps (S500, S600, S700, S800) listed in page 23, paragraphs 152, 154, 156, 157, are not shown in the drawings. Compare with Figure 3.
The steps (S710-S713; S713a-S713g) listed on pages 24-25, are not shown in the drawings. Compare with Figure 3.
The steps (S720-S723; S723a-S723f) listed on pages 25-26, are not shown in the drawings. Compare with Figure 3.
The steps (S810-S815; S820-S822) listed on pages 26-27, are not shown in the drawings. Compare with Figure 3.
The steps (S740-S742; S742a-742e) listed on page 28, are not shown in the drawings. Compare with Figure 3.
The steps (S750-S752; S752a-S752d) listed on pages 28-29, are not shown in the drawings. Compare with Figure 3.
The steps (S760, S770, S771, S772; S772a-772e) listed on pages 30-31, are not shown in the drawings. Compare with Figure 3.
The steps (S830-S834; S834a-S834c) listed on page 31, are not shown in the drawings. Compare with Figure 3.
The steps (S510, S520; S520a-S520e) listed on page 32, are not shown in the drawings. Compare with Figure 3.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Page 8, paragraph 70, line 3 of the page: Change “portion103” to “portion 103”.
Page 14, paragraph 101, lines 4, 5 of the paragraph: In each line, change “etc..” to “etc.”.
Page 15, paragraph 105, lines 6, 8 of the page: In each line, change “etc..” to “etc.”.
Page 15, paragraph 109, lines 10, 12, of the paragraph: In each line, change “etc..” to “etc.”.
Page 16, paragraph 112, lines 8, 16 of the paragraph: Should the reference to “first insulation layer” instead be to “passivation layer 112”?
Page 17, paragraph 113, line 4 of the paragraph: Change “saide” to “side”.
Page 19, paragraph 121, line 7 of the paragraph: Change “etc..” to “etc.”.
Page 20, paragraph 123, line 5 of the paragraph: Change “etc..” to “etc.”.
Page 25, paragraph 178, line 4 of the paragraph: Change “damages” to “damage”.
Appropriate correction is required.
Claim Objections
Claims 10, 14, 15, 19, and 20 are objected to because of the following informalities:
Claim 10, lines 1-2: Please provide antecedent basis for “the gate electrode insulation layer”. This element was defined in claim 4, but claim 10 does not depend from claim 4 directly or indirectly.
Claim 14, lines 5-6: Please provide antecedent basis for “the second metal layer”
Claim 15 is objected to for depending from objected-to base claim 14.
Claim 15, line 7: Please provide antecedent basis for “the second metal layer wiring”.
Claim 19, line 7: Change “anodes expose” to “anodes and expose”.
Claim 20 is objected to for depending from objected-to base claim 19.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 10, 14, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, which depends from claim 8, which depends from claim 3, which depends from claim 2, which depends from claim 1: Claim 9, lines 1-2, require that “the first insulation layer comprises a passivation layer located near the substrate….” (emphasis added). The term “near” is vague because the term does not identify the location of the passivation layer with respect to the substrate. Because the term is vague, claim 9 is rejected as indefinite.
Claim 10 is rejected for depending from rejected base claim 9.
Regarding claim 10, which depends from claim 9, which depends from claim 8, which depends from claim 3, which depends from claim 2, which depends from claim 1: Claim 10, lines 1-2, refer to “the gate electrode insulation layer”. However, this term has not been defined in claim 10, or its parent claims. Because antecedent basis is missing for “the gate electrode insulation layer”, claim 10 is rejected as indefinite.
Regarding claim 14, which depends from claim 2, which depends from claim 1: Claim 14, lines 5-6, refer to “the second metal layer”, but the second metal layer has not been defined in claims 1, 2, or 14. (The second metal layer is defined in claim 3.) Because the second metal layer has not been defined, claim 14 is rejected as indefinite.
Claim 15 is rejected for depending from rejected base claim 14.
Regarding claim 15, which depends from claim 14, which depends from claim 2, which depends from claim 1: Claim 15, line 7, refers to “the second metal layer wiring”. However, this term has not been defined in claim 15, or its parent claims. Because antecedent basis is missing for “the second metal layer wiring”, claim 15 is rejected as indefinite.
Remarks
The Office makes the following observations about this application.
First, WIPO conducted a search and issued a Written Opinion in this application’s international application. One reference, Deng, CN114361226A, was cited as an “X” reference (equivalent to a Section 102 reference), including citations to paragraph 59-73 and 83-99, as well as Figures 1, 2, and 7-12. However, the Deng reference ends at paragraph 58, and has only Figures 1-4, which do not anticipate the claims. For these reasons, the Office did not use the Deng reference in a rejection. Another reference cited in the Written Opinion, is more pertinent, but the arrangement of the pixel definition layer—one layer with openings—is different from the claimed invention, which is a plurality of pixel definition portions (one pixel definition portion per anode), each pixel definition portion having an opening at its respective subpixel anode. The plurality of pixel definition portions, in conjunction with the requirement that an outer angle that the pixel definition portion side makes with the substrate, is key to the invention because the limits on the outer angle prevent damage to the display. Angles for openings in pixel definition layers and for inner angles—that is, the angle of an inside portion of side of the pixel definition portion and the substrate—are known to fall within the claimed range. However, the prior art ranges as to suitable outer angles are not as narrow.
Building on the interpretation of the claims, second, the claims encompass an arrangement in which the display area, or a portion thereof, includes pixel definition portions that meet the included angle requirements of 35°-45°.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hu, U.S. Pat. Pub. No. 2025/0089542 (PCT filing date: Jan. 18, 2023).
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Regarding claim 1: Hu Figures 8 and 9 disclose a display panel, comprising: a substrate; a plurality of anodes (AD) disposed on the substrate (PLN2); and a plurality of pixel definition portions (PDR) covering edges of the anodes (AD) and exposing the anodes (AD) partially; wherein each of the pixel definition portions (PDR) surrounds one of the anodes (AD), and adjacent ones of the pixel definition portions (PDR) are disposed at intervals; wherein along a direction parallel to the substrate (PLN2), the pixel definition portion (PDR) comprises a first side surface away from the anodes (AD), a first included angle (α2) is defined between a side of the first side surface near the substrate (PLN2) and the substrate (PLN2), the first included angle α2 ranges from 15 degrees to 45 degrees, which encompasses the claimed range of 35 degrees to 45 degrees. Hu specification ¶¶ 57-64, 52 (anode AD).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park, U.S. Pat. Pub. No. 2017/0053973, Figures 1, 2, 4A-4H, and further in view of Kwon, U.S. Pat. Pub. No. 2017/0005148, Figure 1B.
Park, Figures 1, 2:
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Park, Figures 4A-4F:
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Park, Figures 4G, 4H
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Kwon Figures 1B:
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Regarding claim 1: Park Figures 1, 2, and 4A-4H disclose a display panel (100), comprising: a substrate (110); a plurality of pixel electrodes (131) disposed on the substrate (110) (Park discloses a plurality of pixels, Park specification ¶ 68, thus a plurality of pixel electrodes are provided, see Park Abstract); and a plurality of pixel definition portions (140) covering edges of the pixel electrodes (131) and exposing the pixel electrodes (131) partially (pixel definition portions are described as having a donut shape, an annular shape, or a rectangular frame shape, Park specification ¶ 84); wherein each of the pixel definition portions (140) surrounds one of the pixel electrodes (131), and adjacent ones of the pixel definition portions (140) are disposed at intervals; wherein along a direction parallel to the substrate (110), the pixel definition portion (140) comprises a first side surface (140b) away from the pixel electrode (131), a first included angle (θ2) is defined between a side of the first side surface (140b) near the substrate (110) and the substrate (110), the first included angle (θ2) is smaller than about 40 degrees, which overlaps the claimed range of 35 degrees to 45 degrees. Park specification ¶¶ 64-105, 109-127. Park does not disclose that the pixel electrode is an anode.
Kwon Figure 1B, directed to an OLED subpixel, discloses the electrode (121) in the position of a pixel electrode is an anode. Kwon specification ¶ 11. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Park to use an anode for the pixel electrode because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 2, which depends from claim 1: The combination discloses a first metal layer (123, 124) located between the anodes (131) and the substrate (110); and a first insulation layer (119) located between the first metal layer (123, 124) and the anodes (131) and comprising a first via hole (VIA), wherein the anode (131) comprises a first connection portion located in the first via hole (VIA) and connected to the first metal layer (123, 124), and the pixel definition portion (140) covers the first connection portion. See Park Figures 2, 4F-4H.
Regarding claim 19: Park Figures 2 and 4A-4H disclose a display panel manufacturing method, comprising: providing a substrate (110); forming a pixel electrode material layer (131’) on the substrate (110); forming a pixel definition material layer (140’’’) on the pixel electrode material layer (131’); and first-patterning the pixel electrode material layer (131’) and the pixel definition material layer (140’’’) to form a plurality of pixel electrode (131) and a plurality of pixel definition portions (140), respectively; wherein the pixel definition portions (140) cover edges of the pixel electrodes (131) [and] expose the pixel electrodes (131) partially, each of the pixel definition portions (140) surrounds one of the pixel electrodes (131), and adjacent ones of the pixel definition portions (140) are disposed at intervals; wherein along a direction parallel to the substrate (110), the pixel definition portion (140) comprises a first side surface away from the pixel electrodes (131), a first included angle (θ2) is defined between a side of the first side surface (140b) near the substrate (110) and the substrate (110), the first included angle is smaller than about 40 degrees, which overlaps the claimed range of 35 degrees to 45 degrees. Park specification ¶¶ 64-105, 109-127. Park does not disclose that the pixel electrode is an anode.
Kwon Figure 1B, directed to an OLED subpixel, discloses the electrode (121) in the position of a pixel electrode is an anode. Kwon specification ¶ 11. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Park to use an anode for the pixel electrode because the modification would have involved the substitution of an equivalent known for the same purpose.
Claims 3-5, 8-11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Yang, U.S. Pat. Pub. No. 2022/0406861, Figures 2, 5A-5E, and 10A-10D.
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Regarding claim 3, which depends from claim 2: The combination discloses an active layer (121) located between the first metal layer (123, 124) and the substrate (110) and comprising a channel portion, a first conductor sub-portion (source portion) and a second conductor sub-portion (drain portion) that are located on two opposite sides of the channel portion respectively; wherein the first metal layer (123, 124) comprises a source electrode (123) and a drain electrode (124), the source electrode (123) is located on the first conductor sub-portion, the drain electrode (124) is located on the second conductor sub-portion. See Park Figure 2; Park specification ¶¶ 71-74, 113.
The combination does not disclose that a side of at least a part of the source electrode (123) near the active layer (121) contacts the first conductor sub-portion, and a side of at least a part of the drain electrode (124) near the active layer (121) contacts the second conductor sub-portion. (For purposes of examination, this language is interpreted as contact between the metal layer in a manner other than through a filled via.)
Yang Figures 2, 5A-5E, and 10A-10D, directed to a OLED display device, disclose an active layer (111) located between the first metal layer (112, 114) and the substrate (101) and comprising a channel portion, a first conductor sub-portion and a second conductor sub-portion that are located on two opposite sides of the channel portion respectively; wherein the first metal layer (112, 114) comprises a source electrode (114) and a drain electrode (112), the source electrode (114) is located on the first conductor sub-portion, the drain electrode (112) is located on the second conductor sub-portion; and a side of at least a part of the source electrode (114) near the active layer (111) contacts the first conductor sub-portion, and a side of at least a part of the drain electrode (112) near the active layer contacts the second conductor sub-portion. Yang specification ¶¶ 63, 66-117, 131-181. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Park to use the Yang transistor design because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 4, which depends from claim 3: Yang discloses a gate electrode (113) located between the source electrode (114) and the drain electrode (112), wherein an orthographic projection of the gate electrode (113) on the active layer (111) covers the channel portion; and a gate electrode insulation layer (103) at least located between the gate electrode (113) and the channel portion. See Yang Figures 2, 5E.
Regarding claim 5, which depends from claim 4: Yang discloses the gate (113) electrode is located on the first metal layer (112, 113, 114), the gate electrode insulation layer (103) comprises a first insulation portion, a second insulation portion, and a third insulation portion disposed separately from one another, the first insulation portion is disposed between the channel portion and the gate electrode (113); the second insulation portion is disposed between a part of the source electrode (114) and the first conductor sub-portion, the third insulation portion is disposed between a part of the drain electrode (112) and the second conductor sub-portion; and an end of the source electrode (114) near the gate electrode (113) contacts the first conductor sub-portion, an end of the drain electrode (112) near the gate electrode (113) contacts the second conductor sub-portion. See id.
Regarding claim 8, which depends from claim 3: Yang discloses a second metal layer (116) located between the active layer (111) and the substrate (101) and comprising a first light shielding portion (116), wherein an orthographic projection of the active layer (111) on the substrate (101) is located within an orthographic projection of the first light shielding portion (116) on the substrate; and a buffer layer (102) located on a side of the active layer (111) near the substrate (101) and covering the second metal layer (116). Yang Figures 2, 5E; Yang specification ¶¶ 70-76.
Regarding claim 9, which depends from claim 8: Yang discloses the first insulation layer comprises a passivation layer (unshown, see Yang specification ¶ 84), and between planarization layer (105) and the first metal layer (112, 113, 114) located near the substrate (101), the buffer layer (102) is located between the second metal layer (116) and the active layer (111), a side of the buffer layer (102) away from the substrate (101) directly contacts the active layer (111) and the passivation layer (unshown, but because first planarization layer (105a) directly contacts buffer layer (102) in Yang Figures 2, 5E, a passivation layer would be between the first planarization layer (105a) and the buffer layer (102) and thus directly contact the buffer layer (102)); and a side of the buffer layer (102) near the substrate (101) directly contacts the second metal layer (116) and the substrate (110). Id. ¶¶ 70-84.
Regarding claim 10, which depends from claim 9: Yang discloses when the gate electrode insulation layer (103) comprises a first insulation portion, a second insulation portion, and a third insulation portion that are disposed separately from one another, an end of the second insulation portion away from the first insulation portion contacts the buffer layer (102), and an end of the third insulation portion away from the first insulation portion contacts the buffer layer (102). See Yang Figures 2, 5E.
Regarding claim 11, which depends from claim 8: Yang discloses the first insulation layer (Yang: 105) further comprises a second via hole located on a side of the active layer; the buffer layer (102) comprises a third via hole communicating with the second via hole, the anode (151) is connected to the first light shielding portion (116) through the second via hole and the third via hole; and the anode (151) comprises a second connection portion, and an orthographic projection of the pixel definition portions (Yang: 106; Park: 140) on the substrate (101) covers an orthographic projection of the second connection portion on the substrate (101). See Yang Figure 2. To the extent that the orthographic projection of the pixel definition portion on the substrate partially exposes an edge of an orthographic projection of the second connection portion on the substrate, the difference relates to the shapes of the respective pixel definition portion and the second connection portion. The application does not indicate that this requirement is patentably significant, thus, the difference is a patentably insignificant shape variation.
Regarding claim 13, which depends from claim 8: Yang discloses a gate electrode insulation layer (103) comprises a sixth via hole located on a side of a third insulation portion away from the active layer (111), the buffer layer (102) comprises a seventh via hole, the sixth via hole communicates with the seventh via hole, and the drain electrode (112) is connected to the first light shielding portion (116) through the sixth via hole and the seventh via hole. See id.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, further in view of Kim, U.S. Pat. Pub. No. 2015/0200234, Figures 1-3.
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Regarding claim 16, which depends from claim 1: The combination discloses that the pixel definition portions (140) and the anodes (131) include an overlapping portion, but is silent as to the width of an orthographic projection of the overlapping portion on the substrate.
Kim, directed to an organic light emitting display device, discloses a pixel definition layer (432) and the pixel electrodes (131) include an overlapping portion, and a width of an orthographic projection of the overlapping portion on the substrate is greater than 2 microns. Kim specification ¶ 66 (greater than 3 microns); see generally id. ¶¶ 42-71. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Kim design because the design permits propagated light to be emitted to the outside efficiently. Id. ¶ 66.
Regarding claim 17, which depends from claim 16: The combination discloses wherein the display panel further comprises an organic layer (132) located on a side of the anodes (131) away from the substrate (110) and comprising a light emitting layer; and along the direction parallel to the substrate (110), the pixel definition portion (140) comprises a second side surface (140a) near the anode (131), an orthographic projection of the anode (131) on the substrate (110) and an orthographic projection of the second side surface (140a) on the substrate (110) commonly cover an orthographic projection of the light emitting layer (132) on the substrate (110). See Park Figure 2; Park specification ¶ 65.
Regarding claim 18, which depends from claim 17: Park discloses that a side of the second side surface (140a) near the anode (131) and the anode (131) comprises a second included angle (θ1), and the second included angle (θ1) smaller than 55 degrees, Park specification ¶ 88, which falls within the claimed range of from 35 degrees to 45 degrees.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Park, Kwon, and Yang, and further in view of Zheng, Chinese Pat. Pub. No. CN114122144A (published March 1, 2022), Figure 1.
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Regarding claim 6, which depends from claim 4: The combination does not disclose that the gate electrode is located on a side of the first metal layer away from the substrate, no insulation layer is disposed between the source electrode and the first conductor sub-portion, and no insulation layer is disposed between the drain electrode and the second conductor sub-portion.
Zheng, directed to similar subject matter, discloses that the gate electrode (50) is located on a side of the first metal layer (31) away from the substrate (10), no insulation layer is disposed between the source electrode (311) and the first conductor sub-portion (202), and no insulation layer is disposed between the drain electrode (312) and the second conductor sub-portion (202). Zheng specification ¶¶ 44-82. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Zheng transistor design because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 7, which depends from claim 6: Zheng discloses wherein in a plane parallel to the substrate (10), along a direction from the channel portion (201) to the first conductor sub-portion (202), an edge of a side of the source electrode (311) away from the gate electrode (50) extends to an edge of a side of the first conductor sub-portion (202) away from the channel portion (201); and in the plane parallel to the substrate (10), along a direction from the channel portion (201) to the second conductor sub-portion (202), an edge of a side of the drain electrode (312) away from the gate electrode (50) extends to an edge of a side of the second conductor sub-portion (202) away from the channel portion (201). Id. Zheng does not disclose that source electrode (311) or the drain electrode (312) extend beyond the edge of a side of their respective first and second conductor sub-portions (202). However, applicants have not disclosed the patentable significance of the source and drain electrodes extending beyond the edges of a side of their respective first and second conductive sub-portions. Because this feature is a patentably insignificant shape variation, claim 7 is rejected as obvious.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Park, U.S. Pat. Pub. No. 2022/0037456 [hereinafter Park ’456], Figure 10.
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Regarding claim 12, which depends from claim 8: Park Figure 2 discloses a gate insulating layer (113) which is deposited conformally on the substrate (110), while Yang Figures 2 and 10A-10D discloses a gate insulating layer (103’) which is deposited on the active layer (111) and the buffer layer (102), and removed in places where the source (114), gate (113), and drain (112) do not mask the gate insulating layer (103). Furthermore, Yang discloses an opening in the gate insulating layer (103) at the location where the drain electrode contacts the light shielding portion (116) and an opening adjacent the source electrode where the buffer layer (102) is exposed. However, the combination does not disclose a gate electrode insulation layer comprises a fourth via hole located in a side of a second insulation portion away from active layer, the buffer layer comprises a fifth via hole communicating with the fourth via hole, and the source electrode is connected to the first light shielding portion through the fourth via hole and the fifth via hole.
Park ’456 Figure 10, directed to similar subject matter, discloses the buffer layer (110) comprises a fifth via hole, and the source electrode (SE2’) is connected to the first light shielding portion (BML2) through the fifth via hole. Park ’456 specification ¶¶ 153-156. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Park ’456 design because the design would prevent potential damage to the transistor due to an electrostatic discharge. Id. ¶ 154. Once combined, the combination discloses a gate electrode insulation layer (Yang, 103) comprises a fourth via hole located in a side of a second insulation portion away from active layer (Yang, 111), the buffer layer (Yang, 102; Park ’456 110) comprises a fifth via hole communicating with the fourth via hole (like that shown in Park Figure 2 for the connection made between the drain (112) and the light shielding layer (116)), and the source electrode (Yang 114; Park ’456 SE2’) is connected to the first light shielding portion (Yang, 116; Park ’456 BML2’) through the fourth via hole and the fifth via hole. This renders obvious claim 12.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Ma, U.S. Pat. Pub. No. 2021/0089186, Figures 1, 2, and 5.
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Regarding claim 14, which depends from claim 2: Park discloses the display panel (100) comprises a display region (DA) and a non-display region (PA) located on at least one side of the display region (DA), the display panel further comprises a terminal (pad portion, not shown) located in the non-display region (PA). Park specification ¶ 155. The combination is silent as to the details relating to the terminal.
Ma Figures 2 and 5, directed to similar subject matter, disclose a display panel (600) comprises a display region (504) and a non-display region (516) located on at least one side of the display region (504), the display panel (600) further comprises a terminal located in the non-display region (516), and the terminal (210) is located on the first metal layer (source/drain layer (148)), and the terminal comprises a first terminal (210), and the first terminal (210) is connected to the second metal layer (344) (by way of first wiring (216)). Ma specification ¶¶ 33, 34, 39, 58. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Ma terminal because the modification would provide a location for the terminal.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park, Kwon, and Ma, and further in view of Yang.
Regarding claim 15, which depends from claim 14: The combination does not disclose that when a gate electrode insulation layer comprises a first insulation portion, a second insulation portion, and a third insulation portion that are disposed separately from one another, the gate electrode insulation layer further comprises a fourth insulation portion located between the terminal and a buffer layer, the gate electrode insulation layer comprises an eighth via hole defined through the fourth insulation portion, the buffer layer comprises a ninth via hole defined through the buffer layer between the second metal layer wiring and the fourth insulation portion, an orthographic projection of the eighth via hole on the substrate covers an orthographic projection of the ninth via hole on the substrate; and the first terminal comprises a first terminal connection portion located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the second metal layer wiring, and the first terminal connection portion contacts the second metal layer wiring.
Yang Figures 2, 5A-5D, and 10A-10D, directed to similar subject matter, disclose an alternate transistor design in which a gate electrode insulation layer (103) comprises a first insulation portion, a second insulation portion, and a third insulation portion that are disposed separately from one another, as a result of etching a preliminary gate electrode insulation layer (103’) that the drain electrode (112), the gate electrode (113), and the source electrode (114) mask. Yang specification ¶¶ 222-242. When the Ma terminal is on the same metallization layer as the source and drain electrode, the gate electrode insulation layer (103) further comprises a fourth insulation portion located between the terminal and a buffer layer (102), the gate electrode insulation layer (103) comprises an eighth via hole defined through the fourth insulation portion (similar to the design of the drain electrode (112) contacting the light shielding layer (116) through its respective insulation portion and the buffer layer), the buffer layer (102) comprises a ninth via hole defined through the buffer layer (102) between the second metal layer wiring (116) and the fourth insulation portion (id.), an orthographic projection of the eighth via hole on the substrate (101) covers an orthographic projection of the ninth via hole on the substrate (101) (id.); and the first terminal comprises a first terminal connection portion located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the second metal layer wiring (id.), and the first terminal connection portion contacts the second metal layer wiring (116). For these reasons, claim 15 is obvious.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Park ’456, Figures 11A-21.
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Regarding claim 20, which depends from claim 19: The combination discloses wherein before the step of forming the pixel electrode/anode material layer (131’) on the substrate (110), the method further comprises: forming a semiconductor material layer on the substrate (110), which forms a semiconductor layer (121); forming a first metal material layer on the semiconductor layer (121), wherein the first metal material layer directly contacts the semiconductor layer (121); and second-processing the first metal material layer to form a first metal layer (123, 124) respectively; wherein the first metal layer (123, 124) comprises a source electrode (123) and a drain electrode (124), wherein the source electrode (123) and the drain electrode (124) are located on two opposite sides of the semiconductor layer (121). Park specification ¶¶ 111-115. Park does not disclose forming a first metal material layer on the semiconductor material layer, wherein the first metal material layer directly contacts the semiconductor material layer; and second-processing the semiconductor material layer and the first metal material layer to form a semiconductor layer and a first metal layer respectively.
Park ’456 Figures 11A-21, directed to similar subject matter, discloses before the step of forming the anode material layer on the substrate, the method further comprises: forming a semiconductor material layer (AML) on the substrate (100); forming a first metal material layer (CML) on the semiconductor material layer (AML), wherein the first metal material layer (CML) directly contacts the semiconductor material layer (AML); and second-processing the semiconductor material layer (AML) and the first metal material layer (CML) to form a semiconductor layer (A2) and a first metal layer (LL/SE2, CP) respectively; wherein the first metal layer (LL/SE2, CP) comprises a source electrode (SE2) and a drain electrode (CP), wherein the source electrode (SE2) and the drain electrode (CP) are located on two opposite sides of the semiconductor layer (A2). Park ’456 specification ¶¶ 157-178. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Park ’456 design because the modification would have involved the substitution of an equivalent set of steps known for the same purpose.
Information Disclosure Statement
The information disclosure statement filed October 27, 2025 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. All references which were provided were considered, and the remaining reference that was not provided was stricken through to indicate that it was not considered.
Conclusion
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/Victoria K. Hall/Primary Examiner, Art Unit 2897