DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim 1 stands rejected under Section 102(a)(2) in view of Hu. Claims 1, 2, and 19 stand rejected under Section 103 in view of Park and Kwon. Claims 3-5, 8-11, and 13 stand rejected under Section 103 in view of Park, Kwon, and Yang. Claims 16-18 stand rejected under Section 103 in view of Park, Kwon, and Kim. Claims 6 and 7 stand rejected under Section 103 in view of Park, Kwon, Yang, and Zheng. Claim 12 stands rejected under Section 103 in view of Park, Kwon, and Park ’456. Claim 14 stands rejected under Section 103 in view of Park, Kwon, and Ma. Claim 15 stands rejected under Section 103 in view of Park, Kwon, Ma, and Yang. Claim 20 stands rejected under Section 103 in view of Park, Kwon, and Park ’456. Claims 9, 10, 14, and 15 stand rejected under Section 112(b). Claims 10, 14, 15, 19, and 20 stand objected to. The specification and drawings stand objected to.
Applicants amended claims 1, 9, 10, 14, 15, and 19, and canceled claim 7. Applicants provided replacement drawings and provided amendments to the specification. Applicants argue that the application is in condition for allowance.
Turning first to the drawings: Applicants’ amendments to the drawings and specification address a number of the drawing objections. The drawing objections that were addressed are accepted and entered. Applicants’ arguments with respect to the drawing objection relating to claim 3 are persuasive. This drawing objection is withdrawn. Informalities were introduced in the amendments, which are noted below. Furthermore, an objection that was not addressed relating to paragraph 102, lines 5-10, not being shown is re-stated.
Next, specification: Applicants’ amendments address the previously noted specification objections and are accepted and entered. No new matter has been added. The previously noted specification objections are withdrawn. Informalities were introduced in the amendments, which are noted below.
Claim objections: Applicants’ amendments address the previously noted claim objections and are accepted and entered. No new matter has been added. The previously noted claim objections are withdrawn. The Office notes that applicants amended an older version of the claims—compare the original claim 16 to the amended claim 16.
Section 112(b) rejections: Applicants’ amendments address the previously noted Section 112(b) rejections and are accepted and entered. No new matter has been added. The previously noted Section 112(b) rejections are withdrawn.
Section 102 rejection: Applicants’ argue that the amendment to claim 1 overcomes the Section 102 rejection based on Hu. First, Hu discloses that the pixel definition portions (PDR) are discrete and separated from one another. Applicants argue that PLN2 is a part of the pixel definition layer, Amendment and Response to Office Action [hereinafter Applicants’ Response], at 13-14, but PLN2 is a second planarization layer. Hu specification ¶ 52. As for applicants’ arguments regarding the first included angle, that is, that Hu’s disclosed range of 15-45 degrees does not anticipate applicants’ claimed range of 35-45 degrees, Applicants’ Response at 14, Hu’s disclosed range anticipates applicants’ claimed range if there is no allegation of criticality of the 35-45 degree range over the 15-45 degree range. MPEP § 2131.03(II); ClearValue Inc. v. Pearl River Polymers Inc., 668 F.3d 1340, 1345 (Fed. Cir. 2012). Applicants’ disclose that an included angle of greater than 45 degrees causes problems, and discloses benefits of an included angle within 35-45 degrees. However, applicants do not disclose any benefits of an included angle of 35-45 degrees over an included angle of 15 degree to less than 35 degrees. Instead, applicants’ disclosure states:
The first included angle α ranges from 35 degrees to 45 degrees, for example, the first included angle α can be 36 degrees, 37 degrees, 38 degrees, 39 degrees, 40 degrees, 41 degrees, 42 degrees, 43 degrees, 44 degrees, etc. An angle value of the first included angle a is within the above range such that a slope the first side surface 103a is gentler. Also, under a circumstance of a constant height, a total surface area of the pixel definition portions 103 increases, which facilitates increasing a contact area between the pixel definition portions 103 and an adjacent film layer, enhances firmness of the bonding between the pixel definition portions 103 and an adjacent film layer such that the display panel 100 applied to a bending scenario would not easily have separated film layers, and improves product quality of the display panel 100.
Applicants’ specification ¶ 121. Based on applicants’ disclosure, the additional range of 15-34 degrees would have the same benefit as the 35-45 degree range. Therefore, there are no unexpected benefits of 35-45 degrees over 15-45 degrees. For these reasons, applicants’ arguments are not persuasive. The rejection is maintained.
Section 103 rejection: Regarding the rejections of independent claims 1 and 19, and dependent claim 2: Applicants argue that Park’s pixel defining layer (140) is a continuous layer instead of a discrete separated pixel definition portion. Applicants’ Response at 16. However, Park shows that its pixel defining layer (140) ends at the planarization layer (11). Furthermore, Park states: “When viewed in a viewing direction from above in a plan view, the pixel defining layer 140 may have a donut shape, an annular shape or a rectangular frame shape.” Park specification ¶ 84. This demonstrates that the Park pixel defining layer (140) is a discrete pixel definition portion that is separate from other pixel definition portions. Applicants refer to a statement by the undersigned in the Remarks section of the March 24, 2026 Non-Final Rejection in which the Office reviewed an office action by WIPO and determined that the art cited was unusable by this Office. Specifically, the Office was referring to Qian, CN112599698, cited in WIPO’s Written Opinion of the International Searching Authority, mailed January 24, 2024, both of which were provided by applicants in their April 22, 2024 IDS, not the Park reference cited in the Section 103 rejections. As for applicants’ second argument regarding the claimed specific 35°-45° range as compared with Park’s requirement “smaller than about 40 degrees”, the Office’s discussion from the previous paragraph is incorporated by reference. The rejections are maintained.
Regarding the rejection of claim 3, applicants argue that “Yang’s transistor architecture is a specifically designed bottom-gate, self-aligned coplanar structure achieved through a multi-step etching process.” Applicants’ Response at 17. Applicants then contend that “[t]he mere assertion that combined Park’s panel structure with Yang’s transistor design would be an ‘equivalent substitution’ is insufficient to establish obviousness.” Id. Applicants continue: “The combination would require modifying both the pixel definition layer architecture of Park and adopting Yang’s transistor fabrication process, two separate, non-trivial modification without a clear motivation or reasonable expectation of success.” Id. Turning to the Yang reference, Yang discloses a top gate transistor (110), with a gate electrode (113) located on top of the active layer (111). Yang Figures 2, 5A; Yang specification ¶ 78. A light-shielding layer (116) is located underneath the transistor (110). Id. ¶¶ 74-78. Replacing the Park transistor with the Yang transistor would have no effect on the Park’s pixel definition layer architecture because both Yang and Park have planarization layers (Park (119); Yang (105)) separating the pixel definition layers from the transistors. See Yang Figure 2; Park Figure 2. The transistors, both top gate transistors, function in same way by providing signals to their respective pixel electrodes of their respective organic light-emitting elements. Applicants’ arguments are unpersuasive. The rejection is maintained.
Regarding the rejection of claim 7: Applicants’ arguments are moot because applicants cancelled claim 7.
Regarding the rejection of claim 6: Applicants argue that
Claim 6 requires a specific bottom-gate configuration in which (1) the gate electrode is located on a side of the first metal layer away from the substrate, and (2) no insulation layer is disposed between the source electrode and the first conductor sub-portion, and no insulation layer is disposed between the drain electrode and the second conductor sub-portion.
Applicants’ Response, at 18.
Starting with applicants’ first contention, that is, that claim 6 requires a bottom-gate configuration—this is incorrect. If the gate electrode is located on a side of the first metal layer away from the substrate, then the first metal layer is between the gate electrode and the substrate. Per claim 3, which claim 6 depends from by way of claim 4, the first metal layer comprises a source electrode and a drain electrode, with the source electrode located on the first conductor sub-portion of the active layer and the drain electrode located on the second conductor sub-portion of the active layer. For claim 6, this places the order of the transistor from the substrate as: active layer, first metal layer (source and drain electrodes), and gate electrode, which is a classic top-gate transistor design, not a bottom-gate transistor design. Claim 4 requires the gate electrode and a gate electrode insulation layer at least located between the gate electrode and the channel portion of the active layer. Thus, if the source and drain electrodes directly contact their respective conductor sub-portions of the active layer, and the gate electrode is separated from the channel portion of the active layer by the gate electrode insulation layer, then the gate electrode is located on a side of the first metal layer (source and drain electrodes) away from the substrate. Zheng shows exactly this arrangement. For these reasons, applicants’ arguments are unpersuasive. As for applicants’ arguments for motivation for making the substitution, again, the Zheng transistor functions like the Yang and Park transistors by providing signals to their respective pixel electrodes used with an organic light emitting device. Again, applicants’ arguments are unpersuasive. The rejection is maintained.
Regarding the rejection of claim 12: Applicants argue that the prior art combination does not show the claimed arrangement in which a gate electrode insulation layer comprises a fourth via hole located in a side of a second insulation portion away from the active layer, the buffer layer comprises a fifth via hole communicating with the fourth via hole, and the source electrode is connected to the first light shielding portion through the fourth via hole and the fifth via hole. However, before Park ’456 is cited, the prior art combination shows this arrangement except that the drain electrode is connected to the first light shielding portion through the fourth via hole and the fifth via hole. Park ’456 Figure 10 shows an alternate arrangement in which the source electrode is connected to the light shielding portion, and this arrangement which can be used instead for the reasons stated in the rejection. Once combined, the combination meets the claim requirements. The rejection is maintained.
Regarding the rejections of claims 14 and 15: The rejections have been updated to reflect the amended claim structure.
Regarding the rejections of claims 16-18: Applicants’ arguments are directed to their arguments with respect to claim 1. The rejections of claims 16-18 are maintained for the same reasons as stated above with respect to claim 1.
Regarding the rejection of claim 20: Applicants’ arguments are directed to their arguments with respect to claim 19. The rejections of claims 16-18 are maintained for the same reasons as stated above with respect to claim 19.
Drawings
The drawings were received on June 18, 2026. These drawings are accepted and entered.
The drawings are objected to because:
The description on page 14, paragraph 102, lines 5-10 of the paragraph is not shown in the drawings.
In Figure 3i, delete 114 from S740.
In Figure 3l, delete 109 from S750. Adjust the box around S750 to encompass S751 and S752.
In Figure 3p, delete 112 from S834.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Using the amendments in the June 18, 2026 Amendment and Response to Office Action, the disclosure is objected to because of the following informalities:
Paragraph 217, line 1: Delete “With reference to FIG. 3j,” and make the “a” uppercase.
Paragraph 218, line 1: Add “With reference to FIG. 3j, and make the “T” in “The” lowercase.
Appropriate correction is required.
Claim Objections
Claims 16-18 are objected to because of the following informalities:
Claim 16, line 1: Change “any one of claims 1 to 15” to “claim 1”.
Claims 17 and 18 are objected to for depending from objected-to base claim 16.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 9, which depends from claim 8, which depends from claim 3, which depends from claim 2, which depends from claim 1: Claim 9 has been amended to require the passivation layer to be located between the second metal layer and the active layer. This corresponds to passivation layer (112) being located between second metal layer (110) and active layer (105). However, the passivation layer (112), according to applicants’ disclosure, is located between the first metal layer (104) and the planarization layer (113). Because the amendment is not supported by the originally filed disclosure, claim 9 is rejected for failing to meet the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, which depends from claim 8, which depends from claim 3, which depends from claim 2, which depends from claim 1: Claim 2, line 3, defines a first insulation layer and its location, located between the first metal layer and the anodes. Claim 3, lines 1-2 define an active layer located between the first metal layer and the substrate. Claim 8, lines 1-2, define a second metal layer located between the active layer and the substrate. Thus, this language defines the order of the substrate, the second metal layer, the active layer, the first active layer, the first insulation layer, and the anodes, in that order. Claim 9, lines 1-2, require that “the first insulation layer comprises a passivation layer located between the second metal layer and the active layer….” (emphasis added). This places the first insulation layer in a new location other than that which it has been defined. Because the requirements of claim 9 conflict with claim 2, 3, and 8, claim 9 is rejected as indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hu, U.S. Pat. Pub. No. 2025/0089542 (PCT filing date: Jan. 18, 2023).
PNG
media_image1.png
566
434
media_image1.png
Greyscale
Regarding claim 1: Hu Figures 8 and 9 disclose a display panel, comprising: a substrate; a plurality of anodes (AD) disposed on the substrate (PLN2); and a plurality of pixel definition portions (PDR) covering edges of the anodes (AD) and exposing the anodes (AD) partially; wherein each of the pixel definition portions (PDR) surrounds one of the anodes (AD), the pixel definition portions (PDR) are discrete and separated from one another, and adjacent ones of the pixel definition portions (PDR) are disposed at intervals; wherein along a direction parallel to the substrate (PLN2), the pixel definition portion (PDR) comprises a first side surface away from the anodes (AD), a first included angle (α2) is defined between a side of the first side surface near the substrate (PLN2) and the substrate (PLN2), the first included angle α2 ranges from 15 degrees to 45 degrees, which encompasses the claimed range of 35 degrees to 45 degrees. Hu specification ¶¶ 57-64, 52 (anode AD).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park, U.S. Pat. Pub. No. 2017/0053973, Figures 1, 2, 4A-4H, and further in view of Kwon, U.S. Pat. Pub. No. 2017/0005148, Figure 1B.
Park, Figures 1, 2, 4A-4F:
PNG
media_image2.png
457
749
media_image2.png
Greyscale
PNG
media_image3.png
790
698
media_image3.png
Greyscale
Park, Figures 4G, 4H
PNG
media_image4.png
606
362
media_image4.png
Greyscale
Kwon Figures 1B:
PNG
media_image5.png
268
357
media_image5.png
Greyscale
Regarding claim 1: Park Figures 1, 2, and 4A-4H disclose a display panel (100), comprising: a substrate (110); a plurality of pixel electrodes (131) disposed on the substrate (110) (Park discloses a plurality of pixels, Park specification ¶ 68, thus a plurality of pixel electrodes are provided, see Park Abstract); and a plurality of pixel definition portions (140) covering edges of the pixel electrodes (131) and exposing the pixel electrodes (131) partially (pixel definition portions are described as having a donut shape, an annular shape, or a rectangular frame shape, Park specification ¶ 84); wherein each of the pixel definition portions (140) surrounds one of the pixel electrodes (131), the pixel definition portions (140) are discrete and separated from one another, and adjacent ones of the pixel definition portions (140) are disposed at intervals; wherein along a direction parallel to the substrate (110), the pixel definition portion (140) comprises a first side surface (140b) away from the pixel electrode (131), a first included angle (θ2) is defined between a side of the first side surface (140b) near the substrate (110) and the substrate (110), the first included angle (θ2) is smaller than about 40 degrees, which overlaps the claimed range of 35 degrees to 45 degrees. Park specification ¶¶ 64-105, 109-127. Park does not disclose that the pixel electrode is an anode.
Kwon Figure 1B, directed to an OLED subpixel, discloses the electrode (121) in the position of a pixel electrode is an anode. Kwon specification ¶ 11. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Park to use an anode for the pixel electrode because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 2, which depends from claim 1: The combination discloses a first metal layer (123, 124) located between the anodes (131) and the substrate (110); and a first insulation layer (119) located between the first metal layer (123, 124) and the anodes (131) and comprising a first via hole (VIA), wherein the anode (131) comprises a first connection portion located in the first via hole (VIA) and connected to the first metal layer (123, 124), and the pixel definition portion (140) covers the first connection portion. See Park Figures 2, 4F-4H.
Regarding claim 19: Park Figures 2 and 4A-4H disclose a display panel manufacturing method, comprising: providing a substrate (110); forming a pixel electrode material layer (131’) on the substrate (110); forming a pixel definition material layer (140’’’) on the pixel electrode material layer (131’); and first-patterning the pixel electrode material layer (131’) and the pixel definition material layer (140’’’) to form a plurality of pixel electrode (131) and a plurality of pixel definition portions (140), respectively; wherein the pixel definition portions (140) cover edges of the pixel electrodes (131) and expose the pixel electrodes (131) partially, each of the pixel definition portions (140) surrounds one of the pixel electrodes (131), the pixel definition portions (140) are discrete and separated from one another, and adjacent ones of the pixel definition portions (140) are disposed at intervals; wherein along a direction parallel to the substrate (110), the pixel definition portion (140) comprises a first side surface away from the pixel electrodes (131), a first included angle (θ2) is defined between a side of the first side surface (140b) near the substrate (110) and the substrate (110), the first included angle is smaller than about 40 degrees, which overlaps the claimed range of 35 degrees to 45 degrees. Park specification ¶¶ 64-105, 109-127. Park does not disclose that the pixel electrode is an anode.
Kwon Figure 1B, directed to an OLED subpixel, discloses the electrode (121) in the position of a pixel electrode is an anode. Kwon specification ¶ 11. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Park to use an anode for the pixel electrode because the modification would have involved the substitution of an equivalent known for the same purpose.
Claims 3-5, 8, 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Yang, U.S. Pat. Pub. No. 2022/0406861, Figures 2, 5A-5E, and 10A-10D.
PNG
media_image6.png
571
908
media_image6.png
Greyscale
PNG
media_image7.png
861
513
media_image7.png
Greyscale
PNG
media_image8.png
1208
504
media_image8.png
Greyscale
Regarding claim 3, which depends from claim 2: The combination discloses an active layer (121) located between the first metal layer (123, 124) and the substrate (110) and comprising a channel portion, a first conductor sub-portion (source portion) and a second conductor sub-portion (drain portion) that are located on two opposite sides of the channel portion respectively; wherein the first metal layer (123, 124) comprises a source electrode (123) and a drain electrode (124), the source electrode (123) is located on the first conductor sub-portion, the drain electrode (124) is located on the second conductor sub-portion. See Park Figure 2; Park specification ¶¶ 71-74, 113.
The combination does not disclose that a side of at least a part of the source electrode (123) near the active layer (121) contacts the first conductor sub-portion, and a side of at least a part of the drain electrode (124) near the active layer (121) contacts the second conductor sub-portion. (For purposes of examination, this language is interpreted as contact between the metal layer in a manner other than through a filled via.)
Yang Figures 2, 5A-5E, and 10A-10D, directed to a OLED display device, disclose an active layer (111) located between the first metal layer (112, 114) and the substrate (101) and comprising a channel portion, a first conductor sub-portion and a second conductor sub-portion that are located on two opposite sides of the channel portion respectively; wherein the first metal layer (112, 114) comprises a source electrode (114) and a drain electrode (112), the source electrode (114) is located on the first conductor sub-portion, the drain electrode (112) is located on the second conductor sub-portion; and a side of at least a part of the source electrode (114) near the active layer (111) contacts the first conductor sub-portion, and a side of at least a part of the drain electrode (112) near the active layer contacts the second conductor sub-portion. Yang specification ¶¶ 63, 66-117, 131-181. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Park to use the Yang transistor design because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 4, which depends from claim 3: Yang discloses a gate electrode (113) located between the source electrode (114) and the drain electrode (112), wherein an orthographic projection of the gate electrode (113) on the active layer (111) covers the channel portion; and a gate electrode insulation layer (103) at least located between the gate electrode (113) and the channel portion. See Yang Figures 2, 5E.
Regarding claim 5, which depends from claim 4: Yang discloses the gate (113) electrode is located on the first metal layer (112, 113, 114), the gate electrode insulation layer (103) comprises a first insulation portion, a second insulation portion, and a third insulation portion disposed separately from one another, the first insulation portion is disposed between the channel portion and the gate electrode (113); the second insulation portion is disposed between a part of the source electrode (114) and the first conductor sub-portion, the third insulation portion is disposed between a part of the drain electrode (112) and the second conductor sub-portion; and an end of the source electrode (114) near the gate electrode (113) contacts the first conductor sub-portion, an end of the drain electrode (112) near the gate electrode (113) contacts the second conductor sub-portion. See id.
Regarding claim 8, which depends from claim 3: Yang discloses a second metal layer (116) located between the active layer (111) and the substrate (101) and comprising a first light shielding portion (116), wherein an orthographic projection of the active layer (111) on the substrate (101) is located within an orthographic projection of the first light shielding portion (116) on the substrate; and a buffer layer (102) located on a side of the active layer (111) near the substrate (101) and covering the second metal layer (116). Yang Figures 2, 5E; Yang specification ¶¶ 70-76.
Regarding claim 10, which depends from claim 5: Yang discloses when the gate electrode insulation layer (103) comprises a first insulation portion, a second insulation portion, and a third insulation portion that are disposed separately from one another, an end of the second insulation portion away from the first insulation portion contacts the buffer layer (102), and an end of the third insulation portion away from the first insulation portion contacts the buffer layer (102). See Yang Figures 2, 5E.
Regarding claim 11, which depends from claim 8: Yang discloses the first insulation layer (Yang: 105) further comprises a second via hole located on a side of the active layer; the buffer layer (102) comprises a third via hole communicating with the second via hole, the anode (151) is connected to the first light shielding portion (116) through the second via hole and the third via hole; and the anode (151) comprises a second connection portion, and an orthographic projection of the pixel definition portions (Yang: 106; Park: 140) on the substrate (101) covers an orthographic projection of the second connection portion on the substrate (101). See Yang Figure 2. To the extent that the orthographic projection of the pixel definition portion on the substrate partially exposes an edge of an orthographic projection of the second connection portion on the substrate, the difference relates to the shapes of the respective pixel definition portion and the second connection portion. The application does not indicate that this requirement is patentably significant, thus, the difference is a patentably insignificant shape variation.
Regarding claim 13, which depends from claim 8: Yang discloses a gate electrode insulation layer (103) comprises a sixth via hole located on a side of a third insulation portion away from the active layer (111), the buffer layer (102) comprises a seventh via hole, the sixth via hole communicates with the seventh via hole, and the drain electrode (112) is connected to the first light shielding portion (116) through the sixth via hole and the seventh via hole. See id.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, further in view of Kim, U.S. Pat. Pub. No. 2015/0200234, Figures 1-3.
PNG
media_image9.png
656
804
media_image9.png
Greyscale
Regarding claim 16, which depends from claim 11: The combination discloses that the pixel definition portions (140) and the anodes (131) include an overlapping portion, but is silent as to the width of an orthographic projection of the overlapping portion on the substrate.
Kim, directed to an organic light emitting display device, discloses a pixel definition layer (432) and the pixel electrodes (131) include an overlapping portion, and a width of an orthographic projection of the overlapping portion on the substrate is greater than 2 microns. Kim specification ¶ 66 (greater than 3 microns); see generally id. ¶¶ 42-71. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Kim design because the design permits propagated light to be emitted to the outside efficiently. Id. ¶ 66.
Regarding claim 17, which depends from claim 16: The combination discloses wherein the display panel further comprises an organic layer (132) located on a side of the anodes (131) away from the substrate (110) and comprising a light emitting layer; and along the direction parallel to the substrate (110), the pixel definition portion (140) comprises a second side surface (140a) near the anode (131), an orthographic projection of the anode (131) on the substrate (110) and an orthographic projection of the second side surface (140a) on the substrate (110) commonly cover an orthographic projection of the light emitting layer (132) on the substrate (110). See Park Figure 2; Park specification ¶ 65.
Regarding claim 18, which depends from claim 17: Park discloses that a side of the second side surface (140a) near the anode (131) and the anode (131) comprises a second included angle (θ1), and the second included angle (θ1) smaller than 55 degrees, Park specification ¶ 88, which falls within the claimed range of from 35 degrees to 45 degrees.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park, Kwon, and Yang, and further in view of Zheng, Chinese Pat. Pub. No. CN114122144A (published March 1, 2022), Figure 1.
PNG
media_image10.png
314
338
media_image10.png
Greyscale
Regarding claim 6, which depends from claim 4: The combination does not disclose that the gate electrode is located on a side of the first metal layer away from the substrate, no insulation layer is disposed between the source electrode and the first conductor sub-portion, and no insulation layer is disposed between the drain electrode and the second conductor sub-portion.
Zheng, directed to similar subject matter, discloses that the gate electrode (50) is located on a side of the first metal layer (31) away from the substrate (10), no insulation layer is disposed between the source electrode (311) and the first conductor sub-portion (202), and no insulation layer is disposed between the drain electrode (312) and the second conductor sub-portion (202). Zheng specification ¶¶ 44-82. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Zheng transistor design because the modification would have involved the substitution of an equivalent known for the same purpose.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Park, U.S. Pat. Pub. No. 2022/0037456 [hereinafter Park ’456], Figure 10.
PNG
media_image11.png
419
377
media_image11.png
Greyscale
Regarding claim 12, which depends from claim 8: Park Figure 2 discloses a gate insulating layer (113) which is deposited conformally on the substrate (110), while Yang Figures 2 and 10A-10D discloses a gate insulating layer (103’) which is deposited on the active layer (111) and the buffer layer (102), and removed in places where the source (114), gate (113), and drain (112) do not mask the gate insulating layer (103). Furthermore, Yang discloses an opening in the gate insulating layer (103) at the location where the drain electrode contacts the light shielding portion (116) and an opening adjacent the source electrode where the buffer layer (102) is exposed. However, the combination does not disclose a gate electrode insulation layer comprises a fourth via hole located in a side of a second insulation portion away from active layer, the buffer layer comprises a fifth via hole communicating with the fourth via hole, and the source electrode is connected to the first light shielding portion through the fourth via hole and the fifth via hole.
Park ’456 Figure 10, directed to similar subject matter, discloses the buffer layer (110) comprises a fifth via hole, and the source electrode (SE2’) is connected to the first light shielding portion (BML2) through the fifth via hole. Park ’456 specification ¶¶ 153-156. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Park ’456 design because the design would prevent potential damage to the transistor due to an electrostatic discharge. Id. ¶ 154. Once combined, the combination discloses a gate electrode insulation layer (Yang, 103) comprises a fourth via hole located in a side of a second insulation portion away from active layer (Yang, 111), the buffer layer (Yang, 102; Park ’456 110) comprises a fifth via hole communicating with the fourth via hole (like that shown in Park Figure 2 for the connection made between the drain (112) and the light shielding layer (116)), and the source electrode (Yang 114; Park ’456 SE2’) is connected to the first light shielding portion (Yang, 116; Park ’456 BML2’) through the fourth via hole and the fifth via hole. This renders obvious claim 12.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Ma, U.S. Pat. Pub. No. 2021/0089186, Figures 1, 2, and 5.
PNG
media_image12.png
1058
893
media_image12.png
Greyscale
Regarding claim 14, which depends from claim 8: Park discloses the display panel (100) comprises a display region (DA) and a non-display region (PA) located on at least one side of the display region (DA), the display panel further comprises a terminal (pad portion, not shown) located in the non-display region (PA). Park specification ¶ 155. The combination is silent as to the details relating to the terminal.
Ma Figures 2 and 5, directed to similar subject matter, disclose a display panel (600) comprises a display region (504) and a non-display region (516) located on at least one side of the display region (504), the display panel (600) further comprises a terminal located in the non-display region (516), and the terminal (210) is located on the first metal layer (source/drain layer (148)), and the terminal comprises a first terminal (210), and the first terminal (210) is connected to the second metal layer (344) (by way of first wiring (216)). Ma specification ¶¶ 33, 34, 39, 58. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Ma terminal because the modification would provide a location for the terminal.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park, Kwon, and Ma, and further in view of Yang.
Regarding claim 15, which depends from claim 14: The combination does not disclose that when a gate electrode insulation layer comprises a first insulation portion, a second insulation portion, and a third insulation portion that are disposed separately from one another, the gate electrode insulation layer further comprises a fourth insulation portion located between the terminal and a buffer layer, the gate electrode insulation layer comprises an eighth via hole defined through the fourth insulation portion, the buffer layer comprises a ninth via hole defined through the buffer layer between the second metal layer wiring and the fourth insulation portion, an orthographic projection of the eighth via hole on the substrate covers an orthographic projection of the ninth via hole on the substrate; and the first terminal comprises a first terminal connection portion located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the second metal layer wiring, and the first terminal connection portion contacts the second metal layer wiring.
Yang Figures 2, 5A-5D, and 10A-10D, directed to similar subject matter, disclose an alternate transistor design in which a gate electrode insulation layer (103) comprises a first insulation portion, a second insulation portion, and a third insulation portion that are disposed separately from one another, as a result of etching a preliminary gate electrode insulation layer (103’) that the drain electrode (112), the gate electrode (113), and the source electrode (114) mask. Yang specification ¶¶ 222-242. When the Ma terminal is on the same metallization layer as the source and drain electrode, the gate electrode insulation layer (103) further comprises a fourth insulation portion located between the terminal and a buffer layer (102), the gate electrode insulation layer (103) comprises an eighth via hole defined through the fourth insulation portion (similar to the design of the drain electrode (112) contacting the light shielding layer (116) (a wiring on the second metal layer) through its respective insulation portion and the buffer layer), the buffer layer (102) comprises a ninth via hole defined through the buffer layer (102) between a wiring on the second metal layer (116) and the fourth insulation portion (id.), an orthographic projection of the eighth via hole on the substrate (101) covers an orthographic projection of the ninth via hole on the substrate (101) (id.); and the first terminal comprises a first terminal connection portion located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the wiring on the second metal layer (id.), and the first terminal connection portion contacts the wiring on the second metal layer (116). For these reasons, claim 15 is obvious.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Kwon, and further in view of Park ’456, Figures 11A-21.
PNG
media_image13.png
1038
946
media_image13.png
Greyscale
PNG
media_image14.png
1229
946
media_image14.png
Greyscale
Regarding claim 20, which depends from claim 19: The combination discloses wherein before the step of forming the pixel electrode/anode material layer (131’) on the substrate (110), the method further comprises: forming a semiconductor material layer on the substrate (110), which forms a semiconductor layer (121); forming a first metal material layer on the semiconductor layer (121), wherein the first metal material layer directly contacts the semiconductor layer (121); and second-processing the first metal material layer to form a first metal layer (123, 124) respectively; wherein the first metal layer (123, 124) comprises a source electrode (123) and a drain electrode (124), wherein the source electrode (123) and the drain electrode (124) are located on two opposite sides of the semiconductor layer (121). Park specification ¶¶ 111-115. Park does not disclose forming a first metal material layer on the semiconductor material layer, wherein the first metal material layer directly contacts the semiconductor material layer; and second-processing the semiconductor material layer and the first metal material layer to form a semiconductor layer and a first metal layer respectively.
Park ’456 Figures 11A-21, directed to similar subject matter, discloses before the step of forming the anode material layer on the substrate, the method further comprises: forming a semiconductor material layer (AML) on the substrate (100); forming a first metal material layer (CML) on the semiconductor material layer (AML), wherein the first metal material layer (CML) directly contacts the semiconductor material layer (AML); and second-processing the semiconductor material layer (AML) and the first metal material layer (CML) to form a semiconductor layer (A2) and a first metal layer (LL/SE2, CP) respectively; wherein the first metal layer (LL/SE2, CP) comprises a source electrode (SE2) and a drain electrode (CP), wherein the source electrode (SE2) and the drain electrode (CP) are located on two opposite sides of the semiconductor layer (A2). Park ’456 specification ¶¶ 157-178. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to include the Park ’456 design because the modification would have involved the substitution of an equivalent set of steps known for the same purpose.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Victoria K. Hall/Primary Examiner, Art Unit 2897
1 This claim is interpreted to depend from claim 1, as in the previous set of claims.
Prosecution Insights