DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11, 14, 15 and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 11, 14, 15 and 18:
These claims have been amended to recite “directly” with respect to side(s) of regions; however, the specification as originally filed does not disclose any structures/elements being “directly” on any sides of other structures/elements. Furthermore, the term “directly” would require a clear disclosure where exactly one structure/element ends such that it is clear what structure/element is “directly” on said one structure/element. The specification does not disclose any endpoints, starting points, or directions of any structure/elements in a manner that would indicate the inventors had possession of the claimed invention at the time the application was filed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-19 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsueda et al. (US 2018/0040683 A1; hereinafter, “Matsueda”, of record).
Regarding claims 1-3 and 5-12:
re claim 1, Matsueda discloses a display panel having a display area 11 (Fig. 1 and [0034]) and a peripheral area, wherein the peripheral area (region outside of area “11” in Fig. 1, e.g., 12/3/10 in Fig. 1) comprises a first region (see “first region” in Exhibit A), a second region (see “second region” in Exhibit A), a third region (see “third region” in Exhibit A), and a fourth region (see “fourth region” in Exhibit A);
the second region comprises a scan circuit (see “scan circuit” in Exhibit A, and “Si” in Fig. 7 and [0053]) configured to generate control signals for subpixels in the display area;
the third region comprises a voltage supply pad (see “voltage supply pad” and VDD in Fig. 7 and [0042]) configured to provide a voltage supply signal to the subpixels in the display area (i.e., voltage from VDD is supplied to the display area);
the first region comprises fanout lines (see “fanout lines…” in Exhibit A) connecting the scan circuit to the subpixels (e.g., “Cell” in Fig. 7 and [0058]) in the display area; and
the fourth region comprises one or more sub-regions (see “one or more sub-regions” in Exhibit A);
wherein the second region comprises a plurality of scan unit areas B21 (Fig. 6B and [0051], i.e., Fig. 6B correlates to the “scan circuit” in Exhibits A and B) and one or more connecting line areas B12/B22 (Fig. 6B and [0051]);
the scan circuit comprises a plurality of scan units in cascading stages (i.e., the driver block shown in Fig. 6B comprises a shift register, which will include cascaded latches/flip-flops);
a respective scan unit of the plurality of scan units comprises transistors (the shift register will include transistors);
the transistors of the scan circuit is absent in the one or more connecting line areas;
the one or more connecting line areas B12/B22 comprises only signal lines (Fig. 6B);
a respective connecting line area of the one or more connecting line areas comprises signal lines connecting scan units of adjacent stages and respectively in two adjacent scan unit areas of the plurality of scan unit areas (i.e., in Fig. 2, scan unit areas, Sn, are positioned around the display, and each scan unit is connected to a scan line, e.g., SL1 [0037]; accordingly, signal lines connect scan units of adjacent stages and in two adjacent scan unit areas);
re claim 2, the display panel of claim 1, wherein the fanout lines connect to the scan circuit at a first connecting interface (see “first connecting interface” in Exhibit A) and connect to the display area at a second connecting interface (see “second connecting interface” in Exhibit A); and
a first width of the first connecting interface is less than a second width of the second connecting interface (see difference in widths of the “first connecting interface” and the “second connecting interface” in Exhibit A);
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re claim 3, the display panel of claim 1, wherein the scan circuit (see “scan circuit” in Exhibit B) has a non-uniform inter-unit distance;
in a first portion (see “first portion” in Exhibit B) of the scan circuit adjacent to at least one sub-region of the one or more sub-regions, the scan circuit has a first average inter-unit distance between adjacent scan units in the first portion (see “first average inter-unit distance (A)” in Exhibit B, wherein a “scan unit” is considered to be a small square encircled by a larger square, as shown in Exhibit B, Figs. 6B and 7);
in a second portion (see “second portion” in Exhibit B) of the scan circuit that is not directly adjacent to the one or more sub-regions, the scan circuit has a second average inter-unit distance between adjacent scan units in the first portion (see “second average inter-unit distance (B+C)/2” in Exhibit B, wherein a “scan unit” is considered to be a small square encircled by a larger square, as shown in Exhibit B, Figs. 6B and 7); and
the second average inter-unit distance is greater than the first average inter-unit distance (see difference in distances in Exhibit B);
re claim 5, the display panel of claim 1, wherein the fanout lines (e.g., “OUT” in Fig. 6B is one fanout line) connect to the scan circuit (e.g., shift register in B21 of Fig. 6B) through the plurality of scan units in the plurality of scan unit areas (in B21 of Fig. 6B, wherein a plurality of scan units are around the display), and do not directly connect to the one or more connecting line areas B12/B22 (Fig. 6B);
a first connecting interface (see “first connecting interface” in Exhibit A) is between the first region and the plurality of scan unit areas; and
the first connecting interface is absent in regions corresponding to the one or more connecting line areas (i.e., in Exhibits A and B, the connecting line areas are located between the third and fourth regions);
re claim 6, the display panel of claim 1, wherein at least one sub- region of the one or more sub-regions (see “(one or more sub-regions)” in Exhibit A) of the fourth region is surrounded by a combination of the first region (see “first region” in Exhibit A) and the second region (see “second region” in Exhibit A);
re claim 7, the display panel of claim 1, wherein two scan unit areas of the plurality of scan unit areas are respectively on a first side and on a second side of a respective sub-region of the one or more sub-regions (i.e., Exhibits A and B show only a portion of the display panel, however, in Fig. 2, it is clear scan unit areas, Sn, and sub-regions, Dm or data unit areas, are arranged alternately around the display panel; accordingly, two scan unit areas, Sn, are respectively on a first side and a second side of a respective sub-region, Dm), the first side and the second side being opposite to each other; and
a portion of the first region (see “first region” in Exhibits A and B) is on a third side of the respective sub-region (see “(one or more sub-regions” in Exhibits A and B), a respective connecting line area of the one or more connecting line areas is on a fourth side of the respective sub-region (i.e., the connecting line area is located between the “(one or more sub-regions)” and the “third region” in Exhibits A and B), the third side and the fourth side being opposite to each other;
re claim 8, the display panel of claim 1, wherein a first sub-region of the one or more sub-regions is on one side of at least one scan unit area of the plurality of scan unit areas; and
a second sub-region of the one or more sub-regions is on an opposite side of the at least one scan unit area (in Exhibits A and B, the “scan circuit” is located between the “(one or more sub-regions)”);
re claim 9, the display panel of claim 1, wherein the plurality of scan unit areas (“scan circuit” in Exhibits A and B) and at least one of the one or more sub-regions (“(one of more sub-regions)”) are arranged in a same column (i.e., in Fig. 2, the display is circular; accordingly, the at some regions of the circular display, a plurality of scan unit areas and at least one sub-region are in a same column);
re claim 10, the display panel of claim 1, wherein signal lines in the respective connecting line area of the one or more connecting line areas curve around at least one sub-region of the one or more sub-regions (i.e., the connecting line area is located between the “(one or more sub-regions)” and the “third region” in Exhibits A and B; accordingly, signal lines in the connecting line area curve around at least one sub-region, especially because the display panel has a circular shape);
re claim 11, the display panel of claim 1, wherein the one or more sub-regions (see Exhibit C) comprise a first respective sub-region (see “1st sub-region” in Exhibit C) and a second respective sub-region (see “2nd sub-region” in Exhibit C);
the first respective sub-region is surrounded by a combination of the first region (see “first region” in Exhibit C) and the second region (see “second region” in Exhibit C);
two scan unit areas (there will be scan unit areas “B21” directly on the side of “1” and directly on the side of “6” in Exhibit C) of the plurality of scan unit areas B21 are respectively directly on a first side (see “1” in Exhibit C) and on a second side (see “2” in Exhibit C) of the first respective sub-region (see “1st sub-region” in Exhibit C, i.e., scan units and sub-region “data units” are alternately arranged around the display, see Fig. 2 and see “scan circuit” with dotted arrow in Exhibit C), the first side and the second side being opposite to each other;
a portion of the first region is directly on a third side (see “3” in Exhibit C) of the first respective sub-region;
a respective connecting line area (e.g., B12) of the one or more connecting line areas B12/B22 is directly on a fourth side (see “4” in Exhibit C) of the first respective sub-region, the third side and the fourth side being opposite to each other;
the third region (see “third region” in Exhibit C, which comprises a combination of four parts) is directly on a first side (see “5” in Exhibit C), a second side (see “6” in Exhibit C), and a fourth side (see “7” in Exhibit C) of the second respective sub-region; and
a respective scan unit area B21 (Exhibit C) of the plurality of scan unit areas is directly on a third side (see “8” in Exhibit C) of the second respective sub-region; and
re claim 12, the display panel of claim 1, wherein the third region (see “third region” in Exhibit C) comprises a main area (see “main area” in Exhibit C) and a surrounding area (an area of the “third region” excluding the “main area” in Exhibit C);
the main area is on a side of the second region (see “second region” in Exhibit C) away from the display area;
the one or more sub-regions comprises a first respective sub-region (see “X” in Exhibit C);
the surrounding area completely surrounds the first respective sub-region (i.e., in Exhibit C, “X” in completely within the “third region”); and
the voltage supply pad (see “voltage supply pad” in Exhibit A) is at least partially present in the surrounding area.
Therefore, claims 1-12 are anticipated by Matsueda.
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Regarding claims 13-19 and 21:
re claim 13, Matsueda discloses a display panel having a display area 11 (Fig. 1 and [0034]) and a peripheral area, wherein the peripheral area (region outside of area “11” in Fig. 1, e.g., 12/3/10 in Fig. 1) comprises a first region (see “first region” in Exhibit A), a second region (see “second region” in Exhibit A), a third region (see “third region” in Exhibit A), and a fourth region (see “fourth region” in Exhibit A);
the second region comprises a scan circuit (see “scan circuit” in Exhibit A, and “Si” in Fig. 7 and [0053]) configured to generate control signals for subpixels in the display area;
the third region comprises a voltage supply pad (see “voltage supply pad” and VDD in Fig. 7 and [0042]) configured to provide a voltage supply signal to the subpixels in the display area (i.e., voltage from VDD is supplied to the display area);
the first region comprises fanout lines (see “fanout lines…” in Exhibit A) connecting the scan circuit to the subpixels (e.g., “Cell” in Fig. 7 and [0058]) in the display area; and
the fourth region comprises one or more sub-regions (see “one or more sub-regions” in Exhibit A);
wherein the third region (“see third region” in Exhibit C) comprises a plurality of straight line areas (e.g., straight wiring lines from “scan circuit” in Exhibit C) and one or more curved line areas (e.g., area containing T1, T2, T3, T4, T5, T6, VDD, VSS, Yn, CLK2, CLK1 and the four lines beyond CLK1 shown in Exhibit C and Fig. 7);
signal lines in the plurality of straight line areas extend substantially along a same extension direction (i.e., the straight lines from “scan circuit” are parallel);
signal lines in the one or more curved line areas are curved signal lines (the curved signal lines extend along the curvature of the display panel, Fig. 2); and
signal lines in a respective curved line area of the one or more curved line areas connect signal lines in two adjacent straight line areas of the plurality of straight line areas (i.e., the straight lines from “scan circuit” connect to curved lines in the “third region” in Exhibit C);
re claim 14, the display panel of claim 13, wherein two straight line areas of the plurality of straight line areas are respectively directly on a first side (see “1” in Exhibit C) and directly on a second side (see “2” in Exhibit C) of a respective sub-region of the one or more sub-regions (see “1st sub-region” in Exhibit C, wherein “scan circuit” alternates with “sub-regions” around the circular display panel, i.e., there is a “scan circuit” directly on the first side 1 and directly on the second side 2), the first side and the second side being opposite to each other; and
a respective curved line area of the one or more curved line areas is directly on a third side (see part of “third region” near “5” in Exhibit C) of the respective sub-region;
re claim 15, the display panel of claim 13, wherein a first sub-region (see “1st sub-region” in Exhibit C) of the one or more sub-regions is directly on one side (see “2” in Exhibit C) of at least one straight line area of the plurality of straight line areas; and
a second sub-region (see “2nd sub-region” in Exhibit C) of the one or more sub-regions is directly on an opposite side (see “8” in Exhibit C) of the at least one straight line area;
re claim 16, the display panel of claim 13, wherein the plurality of straight line areas and at least one of the one or more sub-regions are arranged in a same column (i.e., in Fig. 2, the display is circular; accordingly, the at some regions of the circular display, a plurality of straight line areas and at least one sub-region are in a same column);
re claim 17, the display panel of claim 13, wherein signal lines in the respective curved line area of the one or more curved line areas curve around a side of at least one sub-region of the one or more sub-regions (i.e., the display panel has a circular shape, accordingly, signal lines in the curved line area curve around the sub-regions); and
signal lines in a respective connecting line area of the one or more connecting line areas curve around the signal lines in the respective curved line area of the one or more curved line areas (i.e., the display panel has a circular shape, and there are a plurality of signal lines in the curved area of the “third region” in Exhibit C; accordingly, signal lines in a connecting line area curve around the other signal lines in the curved line area);
re claim 18, the display panel of claim 13, wherein the one or more sub-regions comprise a first respective sub-region (see “1st sub-region” in Exhibit C) and a second respective sub-region (see “2nd sub-region” in Exhibit C);
two straight line areas of the plurality of straight line areas are respectively on a first side (see “1” in Exhibit C) and directly on a second side (see “2” in Exhibit C) of the first respective sub-region, the first side (1) and the second side (2) being opposite to each other;
a respective curved line area of the one or more curved line areas is directly on a third side (see “9” in Exhibit C) of the first respective sub-region;
the fourth region (see “fourth region…” in Exhibit C) further comprises a margin area (see “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8” and “9” in Exhibit C) directly on a side (see “4”/“9”, and “5” in Exhibit C) of the first respective sub-region and the second respective sub-region away from the display area;
the margin area 1/2/3/4/5/6/7/8/9 (Exhibit C) is directly on a fourth side (see “3” in Exhibit C) of the first respective sub-region;
the margin area 1/2/3/4/5/6/7/8/9 (Exhibit C) is directly on a first side (see “5” in Exhibit C), a second side (see “6” in Exhibit C), and a fourth side (see “7” in Exhibit C) of the second respective sub-region (see “2nd sub-region” in Exhibit C); and
a respective straight line area of the plurality of straight line areas (i.e., in the “scan circuit”, see Exhibit C) is on a third side (see “8” in Exhibit C) of the second respective sub-region;
re claim 19, the display panel of claim 1, further comprising an encapsulating layer 34 (Fig. 9 and [0069]) extending from the display area into the peripheral area;
wherein the encapsulating layer 34 encapsulates light emitting elements LT (Fig. 9 and [0067]) and circuits T/C (Fig. 9 and [0067]) in the display panel;
the encapsulating layer 34 extends throughout the display area [0075];
the encapsulating layer is at least partially present in the first region, the second region, and the third region; and
the encapsulating layer is at least partially absent in the fourth region (i.e., an airgap 41 is interposed between sealing glass 42 and encapsulating layer 35, see Fig. 9 and [0070]; accordingly, the encapsulating layer is at least partially absent in a vertical direction of the fourth region); and
re claim 21, A display apparatus (Fig. 2), comprising the display panel of claim l, and one or more integrated circuits (Fig. 4) connected to the display panel.
Therefore, claims 13-19 and 21 are anticipated by Matsueda.
Remarks
The objections to the title and to claim 12 are withdrawn in view of the amendments.
Applicant’s remark have been carefully reviewed and considered, however, they are not persuasive primarily for reasons explained in detail above. Specifically regarding claim 1, applicant submits in Figs. 6B and 7 of Matsueda, B22 is a “DEMUX wiring region” that is not connected to the B21; accordingly, Matsueda fails to teach or suggest that “a respective connecting line area of the one or more connecting line areas comprises signal lines connecting scan units of adjacent stages and respectively in two adjacent scan unit areas of the plurality of scan unit areas”. The examiner respectfully disagrees because B21 and B22 are regions/areas and in Fig. 6B, areas B21 and B22 are clearly connected. Furthermore, claim 1 requires a respective connecting line area to comprise signal lines, however, the current claim language does not require the signal lines to connect scan units within the respective connecting line area. In other words, as long as the signal lines are in the respective connecting line area, those signal lines could be connected to scan units in different areas/regions of the display panel.
With regard to amended claim 3, Matsueda has been reinterpreted and discloses all limitations in this claim as explained in detail above; accordingly, applicant’s remarks are moot in view of the new interpretation of Matsueda.
With regard to claim 11, 14, 15 and 18, the amendment requiring “directly on” in considered to be new matter. However, the current claims are essentially directed to regions/areas that could be chosen to be continuous or segmented; accordingly, Matsueda has been reinterpreted to clearly show that regions being “directly on” other regions, as currently claimed, are disclosed/anticipated depending on what one considers to be a region/area.
Similar to claims 11, 14, 15 and 18, claim 12 is disclosed by Matsueda when suitable regions/areas are chosen to represent “a main area”, “a surrounding area” and “a first respective sub-region”. As explained and shown in detail hereinbefore (in Exhibit C), “a main area” is shown, “a surrounding area” is chosen to be the remaining parts of the “third region” that are not the “main area”, and “a first respective subregion is shown as “X” in Exhibit C. Therefore, current claim 12 is broad enough to be anticipated by Matsueda.
With regard to claim 13, applicant submits that the “area containing T1, T2, T3, etc.” is in the second region annotated in Exhibit C”. The examiner respectfully disagrees because there are a plurality of other curved signal lines, most of which are located in the third region annotated in Exhibit C, and each of the curved lines has been explicitly referenced in this Office action (instead of “etc.”). In Fig. 7 and Exhibit C, the straight signal lines are clearly connected to curved signal lines (e.g., CLK1, CLK2) in the third region; furthermore, the current claim language would only require signal lines in a respective curved line area to be connected (somewhere in the display) to signal lines in two adjacent straight line areas. Accordingly, the examiner respectfully disagrees with what appears to be applicant’s required interpretation of the current claim language.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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