DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al (US Patent 10440813).
Regarding claim 1, Li teaches a semiconductor device comprising:
a semiconductor chip (Fig. 9, 93); and
a wiring board portion having the semiconductor chip mounted thereon and having an external connection terminal for establishing electrical connection to an outside (Fig. 9, chip 93 mounted on wiring board portion 96 with external connection 100), the external connection terminal being formed on a back surface which is a surface opposite to a front surface which is a surface on which the semiconductor chip is mounted (Fig. 9, external connections 104/110 on opposite side of 96 from chip 93),
wherein the semiconductor chip is connected to a terminal formed on the front surface of the wiring board portion through a bonding wire to be wire-bonded to the wiring board portion (Fig. 9, chip 93 connected to wiring board 96 via wire bonds 95), and
a heat dissipation member is disposed between the bonding wire and the wiring board portion (Fig. 9, heat dissipation member 98 disposed between the bonding wire 95 and wiring board 96, meaning that a line can be drawn starting from bonding wire 95 then hit heat dissipation member 98 and then end at wiring board 96).
Regarding claim 2, Li teaches the limitations of claim 1 upon which claim 2 depends.
Li teaches wherein the heat dissipation member is at least partially in contact with a side surface of the semiconductor chip (Fig. 9, heat dissipation member 98 in contact with side surface of chip 93).
Regarding claim 3, Li teaches the limitations of claim 1 upon which claim 3 depends.
Li teaches wherein the heat dissipation member includes a heat pipe (col 6, lines 40-55).
Regarding claim 4, Li teaches the limitations of claim 1 upon which claim 4 depends.
Li teaches further comprising a frame portion which protrudes from the wiring board portion in the same side as a side in which the semiconductor chip is mounted and which surrounds a side portion of the semiconductor chip,
wherein the frame portion covers the bonding wire (Fig. 9, 97, col 16, lines 11-15).
Regarding claim 5, Li teaches the limitations of claim 1 upon which claim 5 depends.
Li teaches further comprising a frame portion which protrudes from the wiring board portion in the same side as a side in which the semiconductor chip is mounted and which is provided outside the semiconductor chip to surround a side portion of the semiconductor chip (Fig. 9, 97, col 16, lines 11-15),
wherein in the frame portion, there is disposed an in-frame heat dissipation member which is a heat dissipation member different from the heat dissipation member (Fig. 9, portion of 98 under 96 on either side of and away from 93).
Regarding claim 6, Li teaches the limitations of claim 1 upon which claim 6 depends.
Li teaches wherein the heat dissipation member is at least partially embedded in a groove formed in the front surface of the wiring board portion (Fig. 9, heat dissipation member 98 embedded in grove of wiring board 96).
Regarding claim 8, Li teaches the limitations of claim 1 upon which claim 8 depends.
Li teaches wherein the semiconductor chip is formed to have a substantially rectangular plate shape, and the heat dissipation member is in contact with all of four side surfaces of the semiconductor chip (Fig. 1, rectangular chips 34 in thermal contact with heat spreader 40, Fig. 9, chip 93 in thermal contact with heat dissipate member 98 on all four sides of chip 93).
Regarding claim 9, Li teaches the limitations of claim 1 upon which claim 9 depends.
Li teaches wherein a communication path from the heat dissipation member to a heat release portion is formed on the front surface of the wiring board portion (Fig. 9, 98 to heat release in 97 when 97 is air, col 16, lines 11-15).
Regarding claim 10, Li teaches the limitations of claim 1 upon which claim 10 depends.
Li teaches wherein a communication path from the heat dissipation member to a heat release portion is formed on the back surface of the wiring board portion (Fig. 9, heat dissipation member to heat spreader extension 106).
Regarding claim 11, Li teaches the limitations of claim 1 upon which claim 11 depends.
Li teaches a frame portion which protrudes from the wiring board portion in the same side as a side in which the semiconductor chip is mounted and which surrounds a side portion of the semiconductor chip; and
a transparent resin with which a space surrounded by the frame portion is filled (Fig. 9, 97, col 16, lines 11-15).
Regarding claim 12, Li teaches the limitations of claim 1 upon which claim 12 depends.
Li teaches a semiconductor device as a solid-state image pickup element (col 2, lines 58-65).
Regarding claim 13, Li teaches a method for manufacturing a semiconductor device, the semiconductor device including:
a semiconductor chip (Fig. 9, 93); and
a wiring board portion having the semiconductor chip mounted thereon and having an external connection terminal for establishing electrical connection to an outside (Fig. 9, chip 93 mounted on wiring board portion 96 with external connection 104/110), the external connection terminal being formed on a back surface which is a surface opposite to a front surface which is a surface on which the semiconductor chip is mounted (Fig. 9, external connections 100 on opposite side of 96 from chip 93), and
the semiconductor chip being connected to a terminal formed on the front surface of the wiring board portion through a bonding wire to be wire-bonded to the wiring board portion (Fig. 9, chip 93 connected to wiring board 96 via wire bonds 95),
wherein the method comprises at least a process for disposing a heat dissipation member between the bonding wire and the wiring board portion (Fig. 9, heat dissipation member 98 disposed between the bonding wire 95 and wiring board 96).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Patent 10440813) in view of Kariyazaki (US Publication 20100109152).
Regarding claim 7, Li teaches the limitations of claim 1 upon which claim 7 depends.
Li does not specifically teach wherein the heat dissipation member is bonded to a side surface of the semiconductor chip through a thermally conductive resin.
Kariyazaki teaches wherein the heat dissipation member is bonded to a side surface of the semiconductor chip through a thermally conductive resin (Fig. 2A, heat dissipation member 102, chip 260, thermally conductive resin 210, para 41 and 44).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li to include the thermally conductive resin attaching the heat dissipation member to the semiconductor chip to include the sides as taught by Kariyazaki in order to further improve the heat dissipation properties of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim (US Publication 20180211944) – Fan-out semiconductor package module.
Ifis (US Publication 20220272828) – Heat Removal Architecture for Stack-Type Component Carrier With Embedded Component.
Lee et al (US Publication 20210193555) – Semiconductor device and semiconductor package having the same.
Chiriac et al (US Publication 20220412664) – Micro-channel pulsating heat pipe.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818