Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/09/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-5, 7-12, and 14-20 without traverse in the reply filed on 12/19/2025 is acknowledged.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites, “wherein an aspect ratio defined by a depth and a width of a via is substantially same in the plurality of vias”. The Examiner believes the Applicant intended to recite “wherein an aspect ratio defined by a depth and a width of a via is substantially the same in the plurality of vias” in order for the claim to be grammatically correct.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 9, 11, 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2,
Claim 2 recites “wherein the via is connected to wiring in a wiring layer constituting a chip”. It is not to the Examiner how a chip is defined. In the Applicant’s figures, a chip comprises a wiring layer and semiconductor substrate. Claim 2 states that a wiring layer constitutes a chip. It is unclear if a chip is only a wiring layer or is semiconductor substrate and a wiring layer. The Examiner interprets a chip to be both a semiconductor substrate and wiring layer as this interpretation is consistent with other claims and Applicant’s drawings.
Regarding Claim 3,
Claim 3 recites, “wherein the plurality of vias includes a first via penetrating a chip stacked in a wiring layer”. The recitation could mean that a first via is stacked on a wiring layer or that a chip is stacked on a wiring layer. Applicant’s figures show that a chip comprises a wiring layer and not that a chip is stacked on a wiring layer. For this reason, the Examiner interprets the recitation to mean, “wherein the plurality of vias includes a first via penetrating a chip comprising a wiring layer”.
Claim 4 is further rejected as it depends upon claim 3.
Regarding Claim 9,
Claim 9 recites, “wherein the third chip is constituted by a same material as the second chip”. The recitation is grammatically incorrect and Applicant’s intent is not clear to the Examiner. The recitation could mean, “wherein the third chip constitutes a same material as the second chip” to make the recitation grammatically correct. However the recitation could also mean, “wherein the third chip consists of a same material as the second chip”. The Examiner interprets the recitation to mean the first listed meaning as this meaning is most similar to the Applicants original recitation.
Regarding Claim 11,
Claim 11 recites, “wherein an insulating film of a same material ”. The Examiner considers three meanings to this recitation. The first is that an insulating film consists of a single material. The second is that the insulating film is the same material as another element. However this element is not listed. The third is that the Applicant did not intend to include the words “of a same material”. The Examiner interprets the recitation according to the third interpretation because the Applicant did not list what material the insulating film is the same as.
Regarding Claim 14,
Claim 14 recites, “wherein a first chip, and a second chip and a third chip smaller than the first chip are stacked on the first chip”. The Examiner does not understand this recitation as a first chip cannot be stacked upon itself. The Examiner believes the Applicant intended to recite, “wherein a chip stack comprises:
a first chip;
a second chip stacked on the first chip, wherein the second chip is smaller than the first chip;
a third chip stacked on the second chip, wherein the third chip is smaller than the first chip” and will therefore interpret the recitation according to this newly written recitation.
Claims 15 and 16 are further rejected as they depend upon claim 14.
Regarding Claim 15,
Claim 15 recites, “wherein a width of a portion of the via located above the second chip is larger than a width of an interval between the second chip and the third chip ”. It is not clear what the interval is an interval of. The Examiner interprets the interval to be an interval of the via as this matches Applicant’s figures.
Claim 15 further recites, “than a width of an interval between the second chip and the third chip”. It is not clear what the interval is an interval of. The Examiner interprets the interval to be a second interval of the via as this matches Applicant’s figures.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 11, 14-15, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al US 20150318246 A1. Yu et al will be referenced to as Yu henceforth.
Regarding Claim 1,
Yu teaches:
“A semiconductor device comprising a plurality of vias (conductive vias 4306, [0080], FIG. 46), wherein an aspect ratio defined by a depth and a width of a via is substantially same in the plurality of vias ([0015], [0038] FIG. 46: The conductive vias have a height to width aspect ratio between about 3 and about 10.). ”
Regarding Claim 2,
Yu teaches:
“The semiconductor device according to claim 1,
wherein the via is connected to wiring in a wiring layer (conductive features 4308, first wiring layer, [0080], FIG. 43, annotated FIG. 46 #1) constituting a chip (die 4302A, [0079], FIG. 44, FIG. 46).”
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Regarding Claim 3,
Yu teaches:
“The semiconductor device according to claim 1, wherein the plurality of vias includes a first via (annotated FIG. 46 #2) penetrating a chip stacked in a wiring layer (annotated FIG. 46 #1, annotated FIG. 46 #2) and a second via not penetrating the chip (annotated FIG. 46 #1, annotated FIG. 46 #2). ”
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Regarding Claim 4,
Yu teaches:
“The semiconductor device according to claim 3, wherein in a case where the first via and the second via are connected to wiring having a same depth (annotated FIG. 46 #3), an aspect ratio of the first via and an aspect ratio of the second via are different from each other (annotated FIG. 46 #2: The middle portion of the first via has a different aspect ratio from the bottom portion of the second via.).”
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Regarding Claim 5,
Yu teaches:
“The semiconductor device according to claim 1, wherein a second chip is stacked on a first chip (die 4302B, [0079], FIG. 44, FIG. 46), and the plurality of vias includes a first via (annotated FIG. 46 #4) connected to first wiring in a first wiring layer (annotated FIG. 46 #1, annotated FIG. 46 #4) included in the first chip (annotated FIG. 46 #4) and a second via connected to second wiring in a second wiring layer (annotated FIG. 46 #4: the second wiring layer contains the second wiring #2) included in the second chip (4302B, FIG. 43, FIG. 46).”
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Regarding Claim 7,
Yu teaches:
“The semiconductor device according to claim 5, wherein wiring formed on a surface of the first wiring layer and wiring formed on a surface of the second wiring layer are bonded ([0079], FIG. 44, FIG. 46: 4302 A and 4302 B are bonded. Because the chips are bonded, so are the wiring layers on the surfaces of those chips.).”
Regarding Claim 11,
Yu teaches:
“The semiconductor device according to claim 5, wherein an insulating film of a same material is formed on a side surface and an upper surface of the second chip (isolation material 4304, [0080], FIG. 44), a side surface of the first via, and a side surface of the second via (FIG. 44).”
Regarding Claim 14,
Yu teaches:
“The semiconductor device according to claim 1, wherein a first chip (Yu: die 4302A, [0079], FIG. 44, FIG. 46), and a second chip (die 4302C, [0079], FIG.44, FIG. 46) and a third chip (die 4302D, [0079], FIG. 44, FIG. 46) smaller than the first chip are stacked on the first chip (FIG. 44: The second chip and the third chip are less wide than the first chip.), and the plurality of vias includes vias formed between the second chip and the third chip (FIG. 44).”
Regarding Claim 15,
Yu teaches:
“The semiconductor device according to claim 14 wherein a width of a portion of the via located above the second chip is larger than a width of an interval between the second chip and the third chip (annotated FIG. 46 #6), and a width of a portion of the via located below the second chip is smaller than a width of an interval between the second chip and the third chip (annotated FIG. 46 #6).”
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Regarding Claim 18,
Yu teaches:
“The semiconductor device according to claim 1, wherein the aspect ratio is in a range of 1 to 20 ([0015], [0038] FIG. 46: The conductive vias have a height to width aspect ratio between about 3 and about 10.).”
Regarding Claim 20,
Yu teaches:
“A manufacturing method for manufacturing a semiconductor device including a plurality of vias (conductive vias 4306, [0080], FIG. 46), the manufacturing method comprising forming a hole in which a width of a via is set such that an aspect ratio defined by a depth and a width of the via is substantially same in the plurality of vias ([0015], [0038] FIG. 46: The conductive vias have a height to width aspect ratio between about 3 and about 10. The height to aspect ratio is set in a via opening.).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claims 1-5, 7, 14-15, 18 and 20 above, and further in view of Baba et al WO 2020129712 A1. Baba et al will be referenced to as Baba henceforth.
Regarding Claim 12,
Yu teaches:
“The semiconductor device according to claim 5, wherein the second chip has a configuration in which a semiconductor substrate having an area smaller than an area of the second wiring layer (annotated FIG. 46 #5) is stacked on the second wiring layer (annotated FIG. 46 #4), ”
Yu doesn’t substantially teach:
“and the second via is formed in a region of the second wiring layer where the semiconductor substrate is not stacked.”
However, Baba teaches:
“and the second via is formed in a region of the second wiring layer where the semiconductor substrate is not stacked (Baba: [0080], FIG. 17: insulating layer 53, which is a portion of 51 is not stacked on semiconductor substrate 21.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yu is modifiable in view of Baba.
This is because Baba teaches that by including an insulating layer around the via, crosstalk between adjacent circuits may be reduced. One of ordinary skill in the art would recognize this as advantageous because cross-talk between semiconductor devices causes a misreading of signals leading to poorer device performance.
Claim 16 rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claims 1-5, 7, 14-15, 18 and 20 above, and further in view of another embodiment of Yu.
Regarding Claim 16,
Yu teaches:
“The semiconductor device according to claim 14, wherein the via is connected to first wiring formed in a wiring layer of the first chip (annotated FIG. 46 #2), second wiring formed in a wiring layer of the second chip (annotated FIG. 46 #2)”
Yu doesn’t substantially teach alone:
“third wiring formed in a wiring layer of the third chip. ”
However, another embodiment of Yu teaches:
“third wiring formed in a wiring layer of the third chip (via connected to wiring in each chip, [0073], [0079], annotated FIG. 38 #1: The via connected to wiring in each chip is connected to wiring in wafer RDL 3014, die RDL 3008, and second die 3802.) ”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yu is modifiable in view of Kao.
This is because Yu teaches that additional dies and packages may be bonded to a package to provide additional functions (Yu: [0073]). Yu further teaches that package 4400 may be formed in accordance to various chip-on-wafer bonding techniques described in previous embodiments (Yu: [0079]). Therefore, because FIG. 38 demonstrates a previous embodiment in which a chip-on wafer bonding technique is described wherein a via is connected to wiring in 3 chips, one of ordinary skill in the art would conclude the embodiment described by FIG. 44 and FIG. 46 of Yu would be modifiable by FIG. 38 of Yu for the purpose of adding additional functions to a device package which one of ordinary skill in the art would find advantageous as additional functions make for a more computationally powerful device.
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claims 1-5, 7, 14-15, 18 and 20 above, and further in view of Kao et al US 20170200756 A1. Kao et al will be referenced to as Kao henceforth.
Regarding Claim 17,
Yu teaches:
“The semiconductor device according to claim 5,”
Yu doesn’t substantially teach:
“wherein the first chip is a solid-state imaging element.”
However, Kao teaches:
“wherein the first chip is a solid-state imaging element (Kao: [0027]: the semiconductor substrate 100 may include image sensor devices.).
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Yu is modifiable in view of Kao.
This is because Yu teaches a first chip with one or more active devices which may be logic or memory devices (Yu: [0003], [0017]). Yu doesn’t substantively teach a first chip with an active device which may be an image sensor. Kao teaches a first chip which may include active devices such as a logic devices or memory devices. Kao further teaches a first chip which may include an image sensor. Because both Yu and Kao have active devices which may be logic or memory circuits, one of ordinary skill in the art would have deemed it obvious to substitute the logic or memory devices of Yu for the image sensor of Kao for the predictable result of forming an image sensing device.
Regarding Claim 19,
Yu/Kao teaches:
“An imaging device comprising:
a first chip (Yu: die 4302A, [0079], FIG. 44, FIG. 46) on which a solid-state imaging element is formed (Kao: [0027]: the semiconductor substrate 100 may include image sensor devices.);
a second chip (Yu: die 4302B, [0079], FIG. 44, FIG. 46) that processes a signal from the first chip (Yu: [0003], [0079], FIG. 44, FIG. 46: 4302B may have an active device which is a processor. One of ordinary skill in the art would find it clear that because 4302A and 4302B are directly connected, then it may be 4302B may have a processor which processes a signal from 4302A.); and
a plurality of vias formed in the first chip and the second chip (Yu: conductive vias 4306, [0080], FIG. 46),
wherein an aspect ratio defined by a depth and a width of a via is substantially same in the plurality of vias (Yu: [0015], [0038] FIG. 46: The conductive vias have a height to width aspect ratio between about 3 and about 10.).”
Allowable Subject Matter
Claims 8, 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 8,
Yu/Baba/Kao fails to explicitly teach :
“the third chip is a dummy chip” In view of the rest of the limitations of claim 8.
Yu/Baba/Kao fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because Yu only teaches semiconductor dies with one or more active devices (Yu: [0003], [0017], [0045], [0052], [0062], [0079]) in each of its embodiments. Semiconductor dies with active devices are not dummy chips. Baba and Kao fail to remedy this deficiency. Kao teaches dummy pads; however dummy pads are not dummy chips as they do not contain a semiconductor substrate.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Yu/Baba/Kao to reach all of the limitations of the claim.
Regarding Claims 9 and 10, these claims depend on claim 8 and are objected to for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights