Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 have been presented for examination based on the amendment filed on
08/09/2023.
Claims 1-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Claim(s) 1-6, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB No.2009/0024969 by Rajit Chandra in view of JP PGPUB No. JP2008304302A by Genzo Matsui et al.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB No.2009/0024969 by Rajit Chandra in view of JP PGPUB No. JP2008304302A by Genzo Matsui et al. in further view of NPL: “Lifetime Estimation of Enameled Wires Under Accelerated Thermal Aging Using Curve Fitting Methods” by KHOWJA et al.
This action is made Non-Final.
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Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (abstract idea) without significantly more.
Regarding Step 2A, Prong One, the claims recite the abstract idea of heat dissipation modeling and design optimization. Specifically, the steps of 'calculating' performance and 'generating' a model based on 'equivalence' fall within the mathematical concepts and mental processes groupings (MPEP § 2106.04(a)(2)). The use of a log-linear formula in Claim 7 further confirms the mathematical nature of the exception.
Regarding Step 2A, Prong Two, the claims do not integrate the abstract idea into a practical application. The recitation of a 'processor,' 'memory,' and 'medium' to execute these steps represents a generic computer implementation that does not improve computer functionality (MPEP § 2106.05(a), (f)). The limitation to semiconductor design is a mere field-of-use, and the 'outputting' step is insignificant extra-solution activity (MPEP § 2106.05(g), (h)).
Regarding Step 2B, the additional elements do not result in the claim as a whole amounting to significantly more than the exception. The use of a computer to perform iterative regression or bisection to find an optimal design parameter is well-understood, routine, and conventional in the Electronic Design Automation (EDA) art (MPEP § 2106.05(d)). The claims merely automate a mental or mathematical process using a computer as a tool, which does not constitute an inventive concept."
Claims [ 1 ]:
Step 1: The claims fall within the four statutory categories:
Claim 1 is a "non-transitory computer-readable recording medium" (Manufacture). (See In re Nuijten, 500 F.3d 1346, 84 USPQ2d 1495 (Fed. Cir. 2007))( See, e.g., Mentor Graphics v. EVE-USA, Inc., 851 F.3d at 1294-95, 112 USPQ2d at 1134)
Claim 9 is a "proposal device" comprising a processor and memory (Machine).
Claim 10 is a "computer-implemented proposal method" (Process). (See 35 U.S.C. 100(b))( See MPEP § 2106.03)
Step 2A, Prong 1: This part of the eligibility analysis evaluates whether the claim recites a judicial exception. As explained in MPEP 2106.04, subsection II, a claim “recites” a judicial exception when the judicial exception is “set forth” or “described” in the claim. The limitations are bolded for abstract idea/judicial exception identification.
Claim 1
Mapping Under Step 2A Prong 1
A non-transitory computer-readable recording medium having stored therein a program configured to cause a computer to execute procedures comprising:
calculating heat dissipation performance based on a reference model that represents a configuration of a semiconductor device in which a multi-layered thermally conductive member includes a heating element;
calculating heat dissipation performance based on a comparative model in which a configuration related to the thermally conductive member of the reference model has been changed;
generating a proposed model in which a configuration related to the heating element of the comparative model is changed such that the heat dissipation performance based on the comparative model is equivalent to the heat dissipation performance based on the reference model;
and outputting information based on the proposed model.
See Step 1.Mathematical Concepts: The step of "calculating heat dissipation performance1" to meet an "equivalent2" performance standard rely on mathematical correlations and algorithms. Specifically, Claim 7 explicitly recites a mathematical formula (log(Rth)=a+b⋅log(S)) 3to model the relationship between heating area and thermal resistance. (2106.04(a)(2) Abstract Idea Groupings)
Mathematical Concepts: The step of "calculating heat dissipation performance" to meet an "equivalent" performance standard rely on mathematical correlations and algorithms. Specifically, Claim 7 explicitly recites a mathematical formula (log(Rth)=a+b⋅log(S)) to model the relationship between heating area and thermal resistance. (2106.04(a)(2) Abstract Idea Groupings)Mental Processes: The logic of "changing" a configuration parameter accordingly describes an evaluation or judgment that could be performed in the human mind. (see MPEP § 2106.04(a)(2), subsection III) (See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 71, 101 USPQ2d 1961, 1965 (2012))
Mathematical Concepts: The step of "generating a proposed model4" to meet an "equivalent" performance standard rely on mathematical correlations and algorithms. Specifically, Claim 7 explicitly recites a mathematical formula (log(Rth)=a+b⋅log(S)) to model the relationship between heating area and thermal resistance. (2106.04(a)(2) Abstract Idea Groupings)
Mental Processes: The logic of comparing two performance values to reach a state of "equivalence" and then "changing" a configuration parameter accordingly describes an evaluation or judgment that could be performed in the human mind. (see MPEP § 2106.04(a)(2), subsection III) (See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 71, 101 USPQ2d 1961, 1965 (2012)) The high-level recitation of "generating a proposed model" without specific non-generic structural steps describes the idea of a solution rather than a physical invention. (See MPEP § 2106.07(a))( See Electric Power Group, LLC v. Alstom, S.A., 830 F.3d 1350, 1356, 119 USPQ2d 1739, 1743-44 (Fed. Cir. 2016); Intellectual Ventures I v. Symantec, 838 F.3d 1307, 1327, 120 USPQ2d 1353, 1366 (Fed. Cir. 2016); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1417 (Fed. Cir. 2015))
See Step 2A, Prong 2
Step 2A, Prong 2: This part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by (1) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (2) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d). As per (1) the additional elements are identified as bolded parts of the limitations in column 1 of the table below, and as per (2) the evaluation is shown in the mapping section of the table.
In accordance with this step, the judicial exception is not integrated into a practical application.
Claim 1
Mapping Under Step 2A Prong 2
A non-transitory computer-readable recording medium having stored therein a program configured to cause a computer to execute procedures comprising:
calculating heat dissipation performance based on a reference model that represents a configuration of a semiconductor device in which a multi-layered thermally conductive member includes a heating element;
calculating heat dissipation performance based on a comparative model in which a configuration related to the thermally conductive member of the reference model has been changed;
generating a proposed model in which a configuration related to the heating element of the comparative model is changed such that the heat dissipation performance based on the comparative model is equivalent to the heat dissipation performance based on the reference model;
and outputting information based on the proposed model
Generic Computer Implementation: The additional elements (processor, memory, computer-readable medium) are recited at a high level of generality and merely serve as a tool to execute the calculations more efficiently. (discussed in MPEP § 2106.05(f))( discussed in MPEP § 2106.05(g))( See Affinity Labs v. DirecTV, 838 F.3d 1253, 1262, 120 USPQ2d 1201, 1207 (Fed. Cir. 2016) (cellular telephone); TLI Communications LLC v. AV Auto, LLC, 823 F.3d 607, 613, 118 USPQ2d 1744, 1748 (Fed. Cir. 2016))
See Step 2A, Prong 1
See Step 2A, Prong 1
Mere Instructions To Apply An Exception: The use of a computer as a tool to automate manual modeling tasks (like identifying equivalence) is considered a generic computer function. The claim essentially recites the abstract idea while adding instructions to "apply it" on a computer. (See 2106.05(f)(1))
Insignificant Extra-Solution Activity: The "outputting information" step is a routine post-solution activity that does not alter the underlying abstract nature of the modeling process. (2106.05(g) Insignificant Extra-Solution Activity)( See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 79, 101 USPQ2d 1961, 1968 (2012))( See Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015))
Step 2B: This part of the eligibility analysis evaluates whether the claim as a whole amounts to significantly more than the recited exception i.e., whether any additional element, or combination of additional elements, adds an inventive concept to the claim. See MPEP 2106.05. This step determines whether the additional elements amount to "significantly more" than the exception by providing an unconventional technological solution. (see MPEP § 2106.05(g) and see MPEP § 2106.05(h))
Well-Understood, Routine, Conventional Activity: Using a computer to simulate physical performance (CAD/EDA) is a routine activity in the engineering arts. (2106.05(d))( See MPEP § 2106.05(d)) Reaching "equivalence" via an automated iterative loop (as establish in Claim 6) is a conventional application of optimization software. (see MPEP § 2106.05(a) (see MPEP § 2106.05(f)(see MPEP § 2106.05(g)))( See, e.g., Intellectual Ventures v. Symantec, 838 F.3d 1307, 1317; 120 USPQ2d 1353, 1359 (Fed. Cir. 2016))( See Genetic Techs. Ltd. v. Merial LLC, 818 F.3d 1369, 1377, 118 USPQ2d 1541, 1546 ( Fed. Cir. 2016))
Generic Components: The hardware components (processor/memory) are used in their ordinary capacity to perform basic functions (calculating, storing, receiving, and outputting data). (MPEP § 2106.05(d))
Conclusion: The additional elements do not amount to significantly more.
Regarding Claim 2
Claim 2 recites, “The non-transitory computer-readable recording medium according to claim 1, (See claim 1) wherein the configuration of the semiconductor device includes dimensions, a material, and a position of the heating element and dimensions, a material, and a position of each layer of the thermally conductive member.
Field of Use: Limitations that restrict the optimization logic to the field of "semiconductor device" design merely link the exception to a particular technological environment, which does not provide a meaningful limit on the exception. (2106.05(h))( see MPEP § 2106.07(a))
Regarding Claim 3
Claim 3 recites, “The non-transitory computer-readable recording medium according to claim 2 (See claim 2), wherein in the generating, the dimensions of the heating element of the comparative model are changed to generate the proposed model.”
Mathematical Concepts (2106.04(a)(2) Abstract Idea Groupings): The step of "generating a proposed model" to meet an "equivalent" performance standard rely on mathematical correlations and algorithms.
Mental Processes:(See MPEP § 2106.07(a))( See Electric Power Group, LLC v. Alstom, S.A., 830 F.3d 1350, 1356, 119 USPQ2d 1739, 1743-44 (Fed. Cir. 2016); Intellectual Ventures I v. Symantec, 838 F.3d 1307, 1327, 120 USPQ2d 1353, 1366 (Fed. Cir. 2016); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1417 (Fed. Cir. 2015)) The logic of "changing" a configuration parameter accordingly describes an evaluation or judgment that could be performed in the human mind. The high-level recitation of "generating a proposed model" without specific non-generic structural steps describes the idea of a solution rather than a physical invention.
Regarding Claim 4
Claim 4 recites, “The non-transitory computer-readable recording medium according to claim 3 (See claim 3), wherein in the outputting, the dimensions of the heating element of the proposed model are output.
Insignificant Extra-Solution Activity (2106.05(g) Insignificant Extra-Solution Activity)( See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 79, 101 USPQ2d 1961, 1968 (2012))( See Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015)) The "outputting information" step is a routine post-solution activity that does not alter the underlying abstract nature of the modeling process.
Regarding Claim 5
Claim 5 recites, “The non-transitory computer-readable recording medium according to claim 3 (See claim 3), wherein in the outputting, a cost of the semiconductor device calculated based on the proposed model is output.
Insignificant Extra-Solution Activity (2106.05(g) Insignificant Extra-Solution Activity)( See also Mayo Collaborative Servs. v. Prometheus Labs. Inc., 566 U.S. 66, 79, 101 USPQ2d 1961, 1968 (2012))( See Mayo, 566 U.S. at 79, 101 USPQ2d at 1968; OIP Techs., Inc. v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1092-93 (Fed. Cir. 2015)) The "outputting information" step is a routine post-solution activity that does not alter the underlying abstract nature of the modeling process.
Field of Use: Limitations that restrict the optimization logic to the field of "semiconductor device" design merely link the exception to a particular technological environment, which does not provide a meaningful limit on the exception. (2106.05(h))( see MPEP § 2106.07(a))
Regarding Claim 6
Claim 6 recites, “The non-transitory computer-readable recording medium according to claim 3 (See Claim 3), wherein the heat dissipation performance includes a thermal resistance, wherein in the generating, the proposed model is generated by repeatedly fitting an equation between a heating area and the thermal resistance, the fitting being performed using a thermal resistance before the dimensions of the heating element are changed in the comparative model and a thermal resistance after the dimensions of the heating element are changed in the comparative model, using the fitted equation to calculate a heating area corresponding to the thermal resistance based on the reference model, and changing, based on the heating area calculated using the equation, the dimensions of the heating element of the comparative model.”
Mathematical Concepts (2106.04(a)(2) Abstract Idea Groupings) The steps of "calculating heat dissipation performance" and "generating a proposed model" to meet an "equivalent" performance standard rely on mathematical correlations and algorithms.
Mental Processes:(See MPEP § 2106.07(a))( See Electric Power Group, LLC v. Alstom, S.A., 830 F.3d 1350, 1356, 119 USPQ2d 1739, 1743-44 (Fed. Cir. 2016); Intellectual Ventures I v. Symantec, 838 F.3d 1307, 1327, 120 USPQ2d 1353, 1366 (Fed. Cir. 2016); Internet Patents Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1417 (Fed. Cir. 2015)) The logic of "changing" a configuration parameter accordingly describes an evaluation or judgment that could be performed in the human mind. The high-level recitation of "generating a proposed model" without specific non-generic structural steps describes the idea of a solution rather than a physical invention.
Regarding Claim 7
Claim 7 recites, “The non-transitory computer-readable recording medium according to claim 6 (See claim 6), wherein the equation is expressed by log(Rth)=a+b*log(S) where Rth is the thermal resistance, S is the heating area, and a and b are fitting parameters.
Mathematical Concepts (2106.04(a)(2) Abstract Idea Groupings) Explicitly recites a mathematical formula log(Rth)=a+b*log(S) to model the relationship between heating area and thermal resistance.
Regarding Claim 8
Claim 8 recites, “The non-transitory computer-readable recording medium according to claim 7 (See claim 7), wherein in the outputting, the thermal resistance based on the reference model, the thermal resistance in the comparative model, and the thermal resistance based on the proposed model are output together with the fitted equation.”
Mathematical Concepts (2106.04(a)(2) Abstract Idea Groupings) Explicitly recites a mathematical formula log(Rth)=a+b*log(S) to model the relationship between heating area and thermal resistance.
Regarding Claim 9
Step 1: Machine
Step 2A Prong 1: similar to claim 1
Step 2A Prong 2: similar to claim 1
Step 2B: similar to claim 1
Regarding Claim 10
Step 1: Process
Step 2A Prong 1: similar to claim 1
Step 2A Prong 2: similar to claim 1
Step 2B: similar to claim 1
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB No.2009/0024969 by Rajit Chandra in view of JP PGPUB No. JP2008304302A by Genzo Matsui et al.
Regarding Claim 1
Chandra teaches A non-transitory computer-readable recording medium having stored therein a program configured to cause a computer to execute procedures comprising: ([0063]: “FIG. 4B illustrates the system environment associated with the thermally aware design automation suite of FIG. 4A. Computer System 300 is a general purpose computing system such as a Personal Computer (PC), Workstation, or Server, and includes a Processor 302, a Memory 304, a Thermal Computation Module 305 and various Input/Output (I/O) and Storage Devices 306.”
[FIG. 4A]:
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[FIG. 4B]:
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)
calculating heat dissipation performance based on a reference model that represents a configuration of a semiconductor device in which a multi-layered thermally conductive member includes a heating element; ([Claim 39]: “…a thermal analysis subsystem adapted to simulate the operational temperature distribution of at least part of the chip using thermal modeling of all thermally significant features of the physical structure, the thermally significant features comprising active devices of a die and embedded multi-layer interconnect of the die and being described by the design database” The examiner interprets where Calculating reference performance is shown in simulating temperature distribution using thermal modeling of all "thermally significant features," specifically comprising "active devices of a die [heating elements] and embedded multi-layer interconnect [thermally conductive member].") calculating heat dissipation performance based on a comparative model5 in which a configuration related to the thermally conductive member of the reference model has been changed; ([Claim 1]: “…based on the acts of simulating, selectively modifying aspects of the design database in accordance with at least one predetermined criteria.” [0056]: “Altering the thermal characteristics of the package design can be accomplished by one or more of the following exemplary but not limiting approaches: changing the package interconnect, metallization, and vias. Altering the thermal characteristics of the heat dissipater design can be accomplished by one or more of the following exemplary but not limiting approaches: changing the number, placement, orientation, geometry, height, density, and elemental composition of one or more heat sink fins in at least one region.” The examiner interprets where Comparative Model Dissipation is shown in "selectively modifying aspects of the design database" in response to thermal analysis, including changes to "package interconnect, metallization, and vias". This modified design constitutes a "comparative model" with a changed thermally conductive member.) generating a proposed mode6l in which a configuration related to the heating element ([0071]: “Assertions can be global to the whole chip (e.g., temperature within a certain range anywhere on the chip), or they can be attached to some physical or logical structure in the chip (e.g., the clock net is within a certain temperature range, a set of transistors are at the same temperature, etc.). In notable embodiments, assertions directly or indirectly (by a tool enforcing the assertion) cause circuit elements to be moved, transistor types to be changed, heating or cooling elements to be inserted, etc. In notable embodiments, assertions operate in conjunction with package-level thermal analysis, whereby modifications of the package, as well as the die, are used to help solve on-chip thermal problems.” The examiner interprets where generating a proposed model in which a configuration related to the heating element of the comparative model is changed such that the heat dissipation performance based on the comparative model is shown in modifying "circuit elements" (heating elements) to be moved or "transistor types to be changed" to help solve on-chip thermal problems identified during simulation.) of the comparative model is changed such that the heat dissipation performance based on the comparative model ([0071]: “Assertions can be global to the whole chip (e.g., temperature within a certain range anywhere on the chip), or they can be attached to some physical or logical structure in the chip (e.g., the clock net is within a certain temperature range, a set of transistors are at the same temperature, etc.). In notable embodiments, assertions directly or indirectly (by a tool enforcing the assertion) cause circuit elements to be moved, transistor types to be changed, heating or cooling elements to be inserted, etc. In notable embodiments, assertions operate in conjunction with package-level thermal analysis, whereby modifications of the package, as well as the die, are used to help solve on-chip thermal problems.” The examiner interprets where Proposed Model (Equivalence) is shown as modifying "circuit elements" (heating elements) to be moved or "transistor types to be changed" to help solve on-chip thermal problems identified during simulation.) outputting information based on the proposed model. ([0097]: “The thermally aware analysis flow begins by analyzing or simulating the thermal behavior of the electronic component design (“Thermal Analysis” 111), based in part on portions of “Design Description” 150. Output results include expected operating temperatures for various elements of the die, including various devices and interconnect. The results may also include a thermal diagram or temperature gradient map, indicating equi-thermal lines of identical temperature superimposed on a representation of the physical or mechanical layout of portions of the electronic component. Alternatively, a listing of elements and respective temperatures may be provided in a tabular format. Any combination of the results may be provided in human-readable and computer-readable representations” The examiner interprets where Outputting information is shown in outputting results including expected operating temperatures, thermal diagrams, or temperature gradient maps.)
Chandra does not explicitly use the phrase “equivalent to the heat dissipation performance based on the reference model." However; Matsui teaches ([0076]: (2) a step of storing, in a database, a relationship between a phase delay, which is a change in thermal reflection intensity of reflected light by the temperature measuring laser beam with respect to a change in heating laser beam intensity, and a thermal conductivity as a calibration model of a region in which the thermal conductivity with respect to the phase delay is set from measurement data acquired by measuring a reference sample for calibration having a known physical property value and a comparative sample including a known reference sample having a thermal conductivity higher than that of the reference sample for calibration under a measurement condition depending on a heating modulation frequency or / and a thermal diffusivity and the thermal conductivity with respect to the phase delay is uniquely determined, and measuring a phase delay by measuring a thermal reflection intensity of an unknown sample under the same condition as the measurement condition by a phase delay measuring means; A step of specifying, by the calculation unit, a thermal conductivity with respect to the phase delay measured by the phase delay measurement unit using the calibration model under the same condition.” The examiner interprets where equivalent to the heat dissipation performance based on the reference model is shown procedure of using a "calibration model" to match properties of an unknown sample to a known reference state under the "same condition.”)
It would have been obvious to a POSITA before the effective filing date of the invention to utilize the performance-matching procedures of Matsui within the automated repair framework of Chandra. The motivation to do so would be to improve design efficiency and ensure that modifications to the package or substrate do not inadvertently deviate from the established thermal requirements of the original design. The combination yields the predictable result of an automated thermal optimization tool that adjusts heating elements to preserve a baseline thermal signature.
Regarding Claim 2
Chandra in combination with Matsui teaches The non-transitory computer-readable recording medium according to claim 1. (See claim 1) Chandra teaches wherein the configuration of the semiconductor device includes dimensions, ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.”) a material, ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.”) and a position ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.”) of the heating element (See [FIG. 4A&4B], [Claim 17]: “The method of claim 1, wherein the selective modification comprises one or more of: a change in a heat generating element; a change in a heat conducting element; and a change in a heat dissipating element.” [0066]: “FIG. 4C shows a simplified view of a thermal model used by the thermally aware design automation suite of FIGS. 4A and 4B, in conjunction with the modeling of the semiconductor devices of FIGS. 3A through 3C, and in particular in the system contexts of FIGS. 2A through 2C. The full chip thermal model must account for boundary conditions, including, but not limited to, the packaging, board, and heat sink configuration and design, as well as material anisotropy and conductance (K) variations. The thermal conductance of the substrate layer is modeled according to the density and/or presence of active devices and implanted interconnect…”
[FIG. 4C]:
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[FIG. 2A]:
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[FIG. 2C]:
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[FIG. 3A]:
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[FIG. 3C]:
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The examiner interprets where Heating element: dimensions, material, and position is shown as modeling "heat generating elements" (active devices) and modifying them via "change in size" (dimensions), "elemental composition" (material), and "placement" (position).) and dimensions, ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.”) a material, ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.”) and a position ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.”) ([Claim 17]: “The method of claim 1, wherein the selective modification comprises one or more of: a change in a heat generating element; a change in a heat conducting element; and a change in a heat dissipating element.” [Claim 1]: “…simulating the operational temperature distribution of at least part of the chip using thermal modeling of all thermally significant features of the physical structure, the thermally significant features comprising active devices of a die and embedded multi-layer interconnect of the die and being described by the design database...” The examiner interprets where Thermally conductive member layers: dimensions, material, and position is shown in modeling "heat conducting elements" (multi-layer interconnect) and modifying them via "change in size" (dimensions), "material property" (material), and "arrangement" (position).)
Chandra fails explicitly to state that the "position" is defined for "each layer" of the conductive member. However, Matsui teaches a position of each layer of the thermally conductive member. ([0037]: “In FIG. 2, a thin-film / substrate two layer model is considered. Here, the thin film corresponds to a metal thin film, and the substrate corresponds to a target sample. Heating light subjected to sinusoidal intensity modulation at an angular frequency ω is applied to a metal thin film having a thickness d, a thermal diffusivity k, and a thermal effusivity b provided on a sample surface, and the metal thin film is heated. At this time, the temperature response of the surface becomes a periodic response of an angular frequency ω with a certain phase delay δ with respect to the heating light. As the thermal effusivity of the sample increases or the angular frequency ω decreases, the phase difference”) The examiner interprets where the detailed layer characterization is shown in characterizing layered semiconductor structures in a "two layer model" specifically by layer "thickness" and material properties for each layer.)
It would have been obvious to a POSITA before the effective filing date of the invention that the 'configuration' of the models being calculated in the procedures of Claim 1 must necessarily be defined by these same parameters. It would have been a routine and predictable application of Chandra’s 'thermally aware' suite to utilize these specific variables when generating a 'proposed model' that is thermally equivalent to a 'reference model,' as this merely involves adjusting known physical inputs to reach a known performance target."
It would have been obvious to a POSITA before the effective filing date of the invention to incorporate the layer-specific characterization parameters of Matsui into the thermal models of Chandra. The motivation to do so would be to improve the precision and reliability of the fine-grain thermal simulations taught by Chandra by accounting for the specific geometric and material properties of each constituent layer. The resulting combination yields the predictable result of a design program that can more accurately calculate heat dissipation performance across a layered semiconductor structure.
Regarding Claim 3
Chandra in combination with Matsui teaches The non-transitory computer-readable recording medium according to claim 2 (See Claim 2). Chandra teaches wherein in the generating, the dimensions of the heating element ([Claim 17]: “The method of claim 1, wherein the selective modification comprises one or more of: a change in a heat generating element; a change in a heat conducting element; and a change in a heat dissipating element.” [Claim 22]: “The method of claim 21, wherein the change of component sizing comprises resizing one or more transistors.”) of the comparative model are changed ([Claim 37]: “The method of claim 36, wherein the modification of configuration comprises one or more of: a change in size; a change in number; a change in placement; an exchange of placement; a change in topology; a change in orientation; a change in pattern; a change in geometry; a change in arrangement; a change in distribution; a change in at least one group property; a change in at least one material property; and a change in elemental composition.” [Claim 22]: “The method of claim 21, wherein the change of component sizing comprises resizing one or more transistors.”) to generate the proposed model. [Abstract]: “The thermally aware design automation suite uses the simulations of the thermal analysis engine to repair or otherwise modify the thermally significant structures to equalize temperature variations across the chip, impose specified design assertions on selected portions of the chip, and verify overall chip performance and reliability over designated operating ranges and manufacturing variations. The thermally significant structures are introduced or modified via one or more of: change in number, change in location, and change in material properties.”
[FIG. 5]:
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The examiner interprets where Change heater dimensions is shown in "resizing" (changing dimensions) "one or more transistors" (heating elements) and a "change in geometry" to optimize design to reach "thermal closure" or "equalize temperature variations")
It would have been obvious to a POSITA before the effective filing date of the invention to incorporate Matsui’s high-accuracy thermal property database and calculation techniques into Chandra’s design suite to improve the precision of the heat dissipation performance calculations. The modification of heating element dimensions in the proposed model to maintain equivalent performance is explicitly taught by Chandra's transistor resizing and geometry modification steps. The combination of these known design and measurement methodologies yields the predictable result of an accurately optimized semiconductor thermal model.
Regarding Claim 4
Chandra in combination with Matsui teaches The non-transitory computer-readable recording medium according to claim 3 (See claim 3). Chandra teaches wherein in the outputting, the dimensions of the heating element of the proposed model are output. (See [0097] & [0091]: “After the final routing and temperature aware timing analysis is completed, if there are any more temperature hot spots the thermal analysis tool applies further repair actions using thermal structures to further minimize temperature gradients, and the flow is then completed with the optimal temperature distribution for the given design and package parameters.” The examiner interprets where Output element dimensions is shown in using "Repair" actions to find optimal distributions and "output results" including "a thermal diagram or temperature gradient map... superimposed on a representation of the physical or mechanical layout" or, alternatively, "a listing of elements... provided in a tabular format".)
It would have been obvious to a POSITA before the time of the invention to modify the output of Chandra to include the specific dimensions calculated by the repair program. The motivation for this modification would be to provide the circuit designer with the necessary physical parameters required to manufacture the improved chip. This modification represents the mere output of the results of a known calculation method, which is a routine expedient in the field of EDA tools yielding a predictable result.
Regarding Claim 5
Chandra in combination with Matsui teaches The non-transitory computer-readable recording medium according to claim 3 (See claim 3). Chandra teaches wherein in the outputting, a cost of the semiconductor device calculated based on the proposed model is output. ([0086]: “…This approach is most beneficial for cost-sensitive applications where overly-conservative margin left in the design corresponds to increased silicon area.” [0120]: “Functionally equivalent techniques known to those of ordinary skill in the art may be employed instead of those illustrated to implement various components, sub-systems, functions, operations, routines, and sub-routines. It is also understood that many design functional aspects may be carried out in either hardware (i.e., generally dedicated circuitry) or software (i.e., via some manner of programmed controller or processor), as a function of implementation dependent design constraints and the technology trends of faster processing (which facilitates migration of functions previously in hardware into software) and higher integration density (which facilitates migration of functions previously in software into hardware). Specific variations may include, but are not limited to: differences in partitioning; different form factors and configurations; use of different operating systems and other system software; use of different interface standards, network protocols, or communication links; and other variations to be expected when implementing the concepts taught herein in accordance with the unique engineering and business constraints of a particular application.” The examiner interprets where Outputting calculated cost based on the proposed model is shown as the design automation flow. Calculation is routine arithmetic.)
A PHOSITA would have found it obvious before the effective filing date of the invention to perform a routine arithmetic calculation summing the costs of the materials and area defined in the proposed model; and outputting that result. Such an addition is the mere automation of a manual business calculation yielding a predictable result, which does not distinguish the invention over the prior art (MPEP § 2144.04).
Regarding Claim 6
Chandra in combination with Matsui teaches The non-transitory computer-readable recording medium according to claim 3 (See claim 3). Chandra teaches wherein the heat dissipation performance includes a thermal resistance, (See FIG 2-4 A-B] & [0066]: The examiner interprets where Performance includes thermal resistance is shown in thermal modeling using "material anisotropy and conductance (K) variations". As thermal resistance is the mathematical reciprocal of conductance, this is an inherent parameter of the modeling.) (See [FIG. 5], [Claim 22], [0073]: “FIG. 6A illustrates the inputs, outputs, and internal actions of the thermal analysis engine of FIG. 5. An initial power estimate is derived and a three dimensional thermal model of the chip is constructed from the design layout, layer thermal coefficients, and a thermal model of the package. The thermal model is then used to solve for the temperature of the cells and wires of the chip in three dimensions. The calculated chip temperatures are then used to refine the power estimate. As suggested by the inner loop, this process repeats until the calculated chip temperature settles to a final value. The final power calculation is subsequently passed to electromigration analysis, timing analysis, and IR drop analysis tools to check for problems warranting improvement or repair.” [0074]: “FIG. 6B provides greater detail of the inner loop of the thermal analysis engine. The thermal model is used to compute the cell and wire temperatures from the current power value. As suggested by the decision block at the bottom center, as long as changes in the computed cell and wire temperatures have not settled out, the leakage and switching power are iteratively recalculated as a function of the updated temperature. The loop is exited and the iteration stops once the computed cell and wire temperatures settle out.”
[FIG. 6A]:
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[FIG. 6B]:
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The examiner interprets where Fitting using resistance before and after dimension changes is shown in an iterative loop where calculated temperatures are used to refine power estimates and repair/optimize designs (e.g., resizing transistors).) (See [Claim 22], [Claim 56]: “The article of manufacture of claim 53, wherein the modification of configuration of the chip metallization comprises one or more of: a change in location; a change in patterning in at least one region; a change in cross section in at least one region; a change in thickness in at least one region; a change in elemental composition in at least one region; a change in at least one material property in at least one region; a change in tile arrangement in at least one region; and a change in tile density in at least one region.” [0099]: “If additional iterations are not required (“No” 113N), then the thermally aware analysis flow is complete, and flow continues, using the results of the analysis to improve the design (“Optimize/Repair” 121)”
[FIG. 12]:
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The examiner interprets where Changing dimensions based on calculated heating area is shown in repairing designs by changing component sizing (e.g., resizing transistors) or metallization thickness to achieve thermal goals.)
Chandra does not explicitly recite "repeatedly fitting an equation" between area and resistance to calculate the new dimensions. However, Matsui teaches wherein in the generating, the proposed model is generated by repeatedly fitting an equation between a heating area and the thermal resistance (See [0076], [0042]: “A heat reflection signal of the reference sample for calibration is measured by a thermophysical property microscope, and a phase delay is obtained. In a range where the thermal effusivity can be measured, a calibration curve for thermal effusivity calibration is created using Ai. In a region where the thermal effusivity is high and calibration thereof is impossible, a calibration curve for thermal conductivity calibration is created” The examiner interprets where Generated by repeatedly fitting an equation (Area vs. Resistance) is shown in storing relationships between physical properties as a "calibration model" or curve generated from measurement data.)
Matsui teaches using the fitted equation to calculate a heating area corresponding to the thermal resistance based on the reference model ([0024]: “According to an aspect of the present invention, there is provided a thermophysical property measurement method using a thermophysical property
measurement device including a heating laser that emits a heating laser beam for heating a surface of a sample through a metal thin film formed on the surface of the sample, a temperature measuring laser that emits a temperature measuring laser beam with which the surface of the sample is irradiated, a microscope optical system that focuses both the laser beams on a measurement position on the surface of the sample, a unit that detects reflected light of the temperature measuring laser beam, and a
calculation unit that calculates a thermophysical property value of the sample on the basis of the detected reflected light. A boundary line indicating a boundary of the region is displayed on the calibration model displayed on the screen, and when the phase delay of the unknown sample measured by the measurement unit is in the region, the thermal conductivity with respect to the phase delay is specified by the calculation unit using the calibration model under the same condition, and when the phase delay is not in the region A thermal effusivity with respect to a phase delay is specified using the specific model under the same condition.” The examiner interprets where Using fitted equation to calculate area for target resistance is shown in using a calibration model/curve to "specify" an unknown property value based on a measured value.)
It would have been obvious to a POSITA before the effective filing date of the invention to incorporate the curve-fitting and property-specification techniques of Matsui into the iterative design loop of Chandra. The motivation would be to replace simple incremental dimension changes with a regression-based calculation (fitting an equation to "before" and "after" data) to more efficiently reach the target thermal resistance. This is a predictable application of known statistical modeling to a known optimization problem. The resulting efficiency improvement is a difference in degree, not in kind, and does not impart patentability.
Regarding Claim 9
Machine version of Claim 1. Similar rejection to Claim 1. See Claim 1.
Regarding Claim 10
Process/Method version of Claim 1. Similar rejection to Claim 1. See Claim 1.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US PGPUB No.2009/0024969 by Rajit Chandra in view of JP PGPUB No.2008-304302 by Matsui et al. in further view of NPL: “Lifetime Estimation of Enameled Wires Under Accelerated Thermal Aging Using Curve Fitting Methods” by KHOWJA et al.
Regarding Claim 7
Chandra in combination with Matsui teaches The non-transitory computer-readable recording medium according to claim 6 (See claim 6). Chandra teaches th is the thermal resistance, ([See FIG 2-4 A-B] & [0066], [Claim 30]: “The method of claim 26, wherein one of the metallization types is preferentially used to improve the heat transfer characteristics of one or more wires.” The examiner interprets where Rth is the thermal resistance is shown as 3D thermal modeling and computing "thermal conductance (K) variations". Resistance is the standard inverse of conductance, used to check problems in "heat transfer characteristics") S is the heating area, ([See [Claim 17& 22]: The examiner interprets where S heating area is shown in “resizing one or more transistors" and changing the "size" of the "heat generating element", which is functionally equivalent to changing its area (S).)
Chandra in view of Matsui does not explicitly state the log-log equation expressed by log(Rth)=a+b*log(S) and a and b are fitting parameters. However; Khowja teaches wherein the equation is expressed by log(Rth)=a+b*log(S) ([P.18995 §2B3 ¶1]: “The Power series function fits a curve through a given dataset in the form of (8). In this case, if the coefficient d is negative, the function represents a decrease through a power law whereas, if d is positive, the function increases through a positive power law [14].
y(t) = Ptd” The examiner interprets equation is expressed by log(Rth)=a+b*log(S) is shown as Power series CF" in the form of y(t) = Ptd. A POSITA would recognize that taking the logarithm of both sides (log(y) = log(P) + d×log(t)) yields the exact mathematical form of Claim 7.) ([P.18995 §2B ¶1]: “Let y(t) be the output of the curve fitting model, t be the input data given to the model, and A, B, m, c, P and d, are curve fitting constants which are to be determined using the given dataset.”)
A person of ordinary skill in the art (POSITA) before the effective filing date of the invention would have found it obvious to improve the iterative resizing loop of Chandra by applying the power series model of Khowja to the variables of heating area (S) and thermal resistance (Rth).
Because a power-law relationship (Rth = P×Sd) is linearized using the formula log(Rth}) = a + b×log(S) (where a=log(P) and b = d), the use of the claimed equation to calculate required heating areas is a predictable application of the curve fitting and 'least mean square' methods taught by Khowja. This combination yields the expected benefit of reaching thermal closure with fewer iterations, thereby reducing computational cost and time-to-market.
Regarding Claim 8
Chandra in combination with Matsui, and Khowja, teaches The non-transitory computer-readable recording medium according to claim 7 (See claim 7). Chandra teaches wherein in the outputting, (See [0097]: The examiner interprets where Outputting thermal resistance is shown in teaches outputting "expected operating temperatures" and "listings of elements" in "tabular format". Because High-Density Plasma is calculated for each design stage (design, repair, final), outputting these intermediate and final values is inherent.)
Chandra in view of Matsui fails to explicitly teach the thermal resistance based on the reference model, the thermal resistance in the comparative model, and the thermal resistance based on the proposed model are output together with the fitted equation. However; Khowja teaches the thermal resistance based on the reference model, the thermal resistance in the comparative model, and the thermal resistance based on the proposed model
([FIG. 9]:
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The examiner interprets where Outputting thermal resistance (Reference, Comparative, Proposed) is shown in plotting the results of multiple thermal models (CM, NN, LCF) together on a single comparative plot.) are output together with the fitted equation.
([FIG. 5b]:
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The examiner interprets where Outputting Equation is shown in displaying the fitted mathematical equations (e.g., (y = -0.384ln(t) + 2.2145)) and (R2) values directly on the output plots.)
It would have been obvious to a POSITA before the effective filing date of the invention to utilize Khowja's multi-model reporting format within Chandra’s CAD framework. The motivation would be to provide the designer with a unified view of the optimization cycle; showing the original reference state, the modified comparative state, and the final proposed state, along with the mathematical proof (the equation) of the optimization, thereby improving the speed and predictability of the thermal design verification process. The combination yields a consolidated thermal optimization report as a predictable result of applying standard comparative plotting techniques to a known simulation workflow.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARIC RAYJEE MARKS whose telephone number is (571)467-6372. The examiner can normally be reached Monday-Friday 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached at (571) 272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AARIC R MARKS/Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188
1 Spec [0017]: “ [6] The program as described in [3], wherein the heat dissipation performance includes a thermal resistance, wherein in the proposed configuration generation procedure, the proposed model is generated by repeatedly fitting an equation relating a heating area to the thermal resistance, the fitting being performed using a thermal resistance before the dimensions of the heating element are changed in the comparative model and a thermal resistance after the dimensions of the heating element are changed in the comparative model,
using the fitted equation to calculate a heating area corresponding to the thermal resistance based on the reference model, and changing, based on the heating area calculated using the equation, the dimensions of the heating element of the comparative model.”
2 Spec [0177]: “FIG. 19(B) is a table illustrating the result of obtaining the element size of the heating element based on the processing procedure of the proposed configuration generation unit according to the embodiment. FIG. 19(B) indicates the results obtained by repeatedly changing the element size and calculating the resistance upon making setting so that the thermal resistance Rref and the thermal resistance R″cmp will be determined to be equivalent to each other when the difference between the thermal resistance Rref and the thermal resistance R″cmp is 0.1% or less in the process of step S169 of FIG. 15.”
3 Spec [0022];” [7] The program as described in [6], wherein the equation is expressed by log(Rth)=a+b*log(S)
where Rth is the thermal resistance, S is the heating area, and a and b are fitting parameters.”
4 Spec [0177]: “FIG. 19(B) is a table illustrating the result of obtaining the element size of the heating element based on the processing procedure of the proposed configuration generation unit according to the embodiment. FIG. 19(B) indicates the results obtained by repeatedly changing the element size and calculating the resistance upon making setting so that the thermal resistance Rref and the thermal resistance R″cmp will be determined to be equivalent to each other when the difference between the thermal resistance Rref and the thermal resistance R″cmp is 0.1% or less in the process of step S169 of FIG. 15.”
5 See Spec [0121]: “The comparative model may be a model in which the thickness and the material of one of the layers of the thermally conductive member have been changed. Alternatively, the comparative model may be a model in which at least the thickness or the material of two or more layers of the thermally conductive member has been changed. Further, the comparative model may be a model in which the layout of the thermally conductive member has been changed. Note that the layout of the thermally conductive member may be the order of the layers of the thermally conductive member. The change in the layout of the thermally conductive member may be the addition or the deletion of a layer in the thermally conductive member”
6 See Spec [0056]: “The proposed model according to the embodiment is a model in which the configuration (for example, the dimensions, the material, and the layout) of the heating element of the comparative model has been changed. That is, the proposal system according to the embodiment is a system that proposes the configuration for a heating element that can maintain the heat dissipation performance when the configuration of the thermally conductive member of the reference model is changed.”
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