DETAILED ACTION This is in response to the appli cation filed on June 2, 2023 in which claims 1 – 24 are presented for examination . Status of Claims Claims 1 – 24 are pending, of which claim s 1, 8, and 21 are in independent form. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statements (IDS) submitted on 7/11/2023 and 10/9/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Specification The disclosure is objected to because of the following informalities: Applicant’s [0004] states “In addition, the conventional system as subject to high bandwidth utilization.” The examiner recommends amending the specification at [0004] to state “In addition, the conventional system as is subject to high bandwidth utilization.” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 24 recites the limitation "the compute extension" in line 1. There is insufficient antecedent basis for this limitation in the claim. Note that “a read with compute extension or a write with compute extension” is found in claim 23. However, claim 24 is listed as depending from claim 21, which does not introduce a compute extension. Therefore, it is possible that claim 24 was meant to depend from claim 23. Claim Objections Claims 4 – 7 are objected to because of the following informalities: claim 4 states “ compute the aggregation operation on the attributes base on the first memory access to generate result data .” The examiner recommends amending claim 4 to state “ compute the aggregation operation on the attributes base based on the first memory access to generate result data .” Claims 5 – 7 inherit this objection based on their dependencies. Appropriate correction is required. Claim 12 is objected to because of the following informalities: claim 12 introduces the acronyms “ GenZ /CXL” and “DDR” is no further definition for these acronyms. The examiner suggests an amendment to define these acronyms, such as “ Compute E xpress L ink ( GenZ / CXL ) ” and “ double data rate ( DDR ) .” Appropriate correction is required. Claim 12 is objected to because of the following informalities: claim 12 does not end with a period. Appropriate correction is required. Claims 19 – 20 are objected to because of the following informalities: claim 19 states “ dete r mining, by a central core, a neural network stage and data associated with a graph node its neighbor nodes; writing, by the central core, the data associated with the graph node its neighbor nodes to a given memory unit when the neural network stage is a first stage or one of a first group of stages .” The examiner recommends amending claim 19 to state “ dete r mining, by a central core, a neural network stage and data associated with a graph node and its neighbor nodes; writing, by the central core, the data associated with the graph node and its neighbor nodes to a given memory unit when the neural network stage is a first stage or one of a first group of stages .” Claim 20 inherits this objection based on its dependencies. Appropriate correction is required. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4 – 18, and 21 – 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ‘ GNNear : Accelerating Full-Batch Training of Graph Neural Networks with Near-Memory Processing’ by Zhou et al. (hereinafter referred to as Zhou). Referring to claim 1 , Zhou discloses “ A neural network processing system ” ( Figure 5 GNNear system with Centralized Acceleration Engine (CAE) and NMP-enabled DIMM with Near-Memory Engines (NME) ) “ comprising: a central core ” ( Figure 5 CAE ) ; “ and one or more memory units coupled to the central core, wherein respective memory units include: one or more memory devices ” ( Figure 5 DIMMs include DRAMs ) ; “ and a controller coupled to the one or more memory devices ” ( Figure 5 NME is part of the buffer chip of DIMM ) “ and configured to perform aggregation operations on data stored in the one or more memory device of the respective memory unit offloaded from the central core ” ( Abstract teaches “we offload the memory-intensive Reduce operations to in-DIMM Near-Memory-Engines (NMEs).” As taught in section 2.2, “ The Reduce operations aggregate features/gradients along the edges of each destination vertex .” Further, Figure 5 and section 4.1 ‘Base Workflow’ section teaches “ For Reduce, CAE sends customized instructions through the memory interfaces to NMEs. NMEs decode the instructions and perform partial r eduction with the assigned source vertices locally .” Also section 4.3 teaches “ The Execution Unit (EU for short) in each NME is responsible for near-memory partial reduction computation of Reduce operations ” ) . As per claim 4 , Zhou discloses “ the controller is further configured to: receive a first memory access including an aggregation operation ” ( Figure 5 and section 4.1 ‘Base Workflow’ section teaches “ For Reduce, CAE sends customized instructions through the memory interfaces to NMEs. NMEs decode the instructions and perform partial r eduction with the assigned source vertices locally .” Also section 4.3 teaches “ The Execution Unit (EU for short) in each NME is responsible for near-memory partial reduction computation of Reduce operations ” ) ; access attributes in the respective one or more memory devices based on the first memory access; compute the aggregation operation on the attributes base [d] on the first memory access to generate result data ” ( Abstract teaches “we offload the memory-intensive Reduce operations to in-DIMM Near-Memory-Engines (NMEs).” Also section 4.3 teaches “ The Execution Unit (EU for short) in each NME is responsible for near-memory partial reduction computation of Reduce operations ” ) ; “ and output the result data based on the first memory accesses to the central core ” ( Section 4.1 “the partial results are read out by CAE.” Figure 7 output buffer of each NME. Figure 15 NMEs sending results to result FIFOs in CAE ) . As per claim 5 , Zhou discloses “ the central core is configured to: schedule the first memory access including the aggregation operation ” ( Section 4.2 CAE Architecture describes the controller of the CAE schedules the training. Section 5.2 ‘Window-based Scheduling’ section teaches “ We allow the CAE-side controller to issue instructions for interval i + 1 immediately after a DIMM finishes interval i , if interval i + 1 is within the Processing window ” and “ Once every DIMM's results of interval i are merged, CAE commits interval i and right-shifts the Processing window. By this means, we can schedule multiple intervals concurrently and mitigate the load-imbalance problems caused by graphs' irregularity ” ) ; “ send the first memory access including the aggregation operation to the controller ” ( Figure 5 and section 4.1 ‘Base Workflow’ section teaches “ For Reduce, CAE sends customized instructions through the memory interfaces to NMEs. NMEs decode the instructions and perform partial r eduction with the assigned source vertices locally ” ) ; “ and receive the result data based on the first memory accesses from the controller ” ( Section 4.1 “the partial results are read out by CAE.” Figure 7 output buffer of each NME. Figure 15 NMEs sending results to result FIFOs in CAE ) . As per claim 6 , Zhou discloses “ the central core is further configured to: compute a further aggregation operation on the result data received from the controller ” ( S ection 4.2 the CAE merges partial reduction results ) . As per claim 7 , Zhou discloses “ t he controller is further configured to: receive a second memory access request; access attributes in the respective one or more memory devices based on the second memory access; and output the attributes based on the second memory request to the central core ” ( Figure 5 and section 4.3 “ Apart from near-memory processing, if NME receives standard DDR commands from the CAE-side memory controller, it will bypass execution units and directly conducts Read/Write/ Precharge commands, etc. ” ) . Referring to claim 8 , Zhou discloses “ A near memory processing method ” ( Figure 5 DIMMs with Near-Memory Engine (NME) ) “ comprising: receiving, by a controller, a first memory access including an aggregation operation; accessing, by the controller, attributes based on the first memory access; computing, by the controller, the aggregation operation on the attributes based on the first memory access to generate result data ” ( Abstract teaches “we offload the memory-intensive Reduce operations to in-DIMM Near-Memory-Engines (NMEs).” As taught in section 2.2, “ The Reduce operations aggregate features/gradients along the edges of each destination vertex .” Further, Figure 5 and section 4.1 ‘Base Workflow’ section teaches “ For Reduce, CAE sends customized instructions through the memory interfaces to NMEs. NMEs decode the instructions and perform partial r eduction with the assigned source vertices locally .” Also section 4.3 teaches “ The Execution Unit (EU for short) in each NME is responsible for near-memory partial reduction computation of Reduce operations ” ) ; “ and outputting, from the controller, the result data based on the first memory accesses ” ( Section 4.1 “the partial results are read out by CAE.” Figure 7 output buffer of each NME. Figure 15 NMEs sending results to result FIFOs in CAE ) . As per claim 9 , Zhou discloses “ the aggregation operation comprises a graph neural network aggregation operation ” ( Abstract teaches GNN training and “we offload the memory-intensive Reduce operations to in-DIMM Near-Memory-Engines (NMEs).” Section 2.2, “ The Reduce operations aggregate features/gradients along the edges of each destination vertex ” ). As per claim 10 , Zhou discloses “ the memory access including the aggregation operation comprises a read with compute extension or a write with compute extension ” ( section 4.3 NME receives NMP instructions from CAE, decodes the instructions, and starts local execution. The controller also generates signals to access local DRAMs. Figures 10 and 11 show instructions with data being accessed and bits to specify an operation ). As per claim 11 , Zhou discloses “ the compute extension can include a data address, data count and data stride ” ( Figures 10 and 11 DIMM, Vector_size , index, bank, etc. ) . As per claim 12 , Zhou discloses “ the compute extension is embedded in a GenZ /CXL data package, or extended D D R command ” ( section 4.3 NME receives NMP instructions from CAE, decodes the instructions, and starts local execution. The controller also generates signals to access local DRAMs according to DDR ) . As per claim 13 , Zhou discloses “ a mode of the first memory access including the aggregation operation includes a complete compute mode or a partial compute mode ” ( section 2.3 Full-batch vs. Mini-batch Training ) . Note, claim 1 4 recites the corresponding limitations of claim 7 . Therefore, the r ejection of claim 7 applies to claim 1 4 . As per claim 15 , Zhou discloses “ the second memory access includes a read or write ” ( Figure 5 and section 4.3 “ Apart from near-memory processing, if NME receives standard DDR commands from the CAE-side memory controller, it will bypass execution units and directly conducts Read/Write/ Precharge commands, etc. ” ) . As per claim 16 , Zhou discloses “ a mode of the second memory access i ncludes a no compute mode ” ( Figure 5 and section 4.3 “ Apart from near-memory processing, if NME receives standard DDR commands from the CAE-side memory controller, it will bypass execution units and directly conducts Read/Write/ Precharge commands, etc. ” ) . Note, claim 1 7 recites the corresponding limitations of claim 5 . Therefore, the r ejection of claim 5 applies to claim 1 7 . Note, claim 1 8 recites the corresponding limitations of claim 6 . Therefore, the r ejection of claim 6 applies to claim 1 8 . Referring to claim 21 , Zhou discloses “ A controller ” ( Figure 5 Near-Memory Engine (NME) ) “ comprising: a plurality of computation units ” ( Figure 7 NME with multiple processing elements (PEs) ) ; “ and control logic configured to: receive a first memory access including an aggregation operation ” ( section 4.3 NME receives NMP instructions from CAE, decodes the instructions, and starts local execution including “near-memory partial reduction computation of Reduce operations.” As taught in section 2.2, “ The Reduce operations aggregate features/gradients along the edges of each destination vertex .” ) ; “ access attributes based on the first memory access; configure one or more of the plurality of computation units to compute the aggregation operation on the attributes based on the first memory access to generate result data ” ( Abstract teaches “we offload the memory-intensive Reduce operations to in-DIMM Near-Memory-Engines (NMEs).” Further, Figure 5 and section 4.1 ‘Base Workflow’ section teaches “ For Reduce, CAE sends customized instructions through the memory interfaces to NMEs. NMEs decode the instructions and perform partial r eduction with the assigned source vertices locally .” Also section 4.3 teaches “ The Execution Unit (EU for short) in each NME is responsible for near-memory partial reduction computation of Reduce operations ” ) ; “ and output the result data based on the first memory accesses ” ( Section 4.1 “the partial results are read out by CAE.” Figure 7 output buffer of each NME. Figure 15 NMEs sending results to result FIFOs in CAE ) . Note, claim 22 recites the corresponding limitations of claim 7 . Therefore, the r ejection of claim 7 applies to claim 22 . Note, claim 23 recites the corresponding limitations of claim 10 . Therefore, the r ejection of claim 10 applies to claim 23 . Note, claim 24 recites the corresponding limitations of claim 11 . Therefore, the r ejection of claim 11 applies to claim 24 . Allowable Subject Matter Claims 2, 3, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application 20210150323 teaches neural network processing and near-memory configuration enables performing matrix calculations without numerous off-chip data reads and/or writes . U.S. Patent Application 20230162024 teaches graph neural network processing with an aggregation phase using Ternary Content Addressable Memory (TCAM)-based training to greatly reduce data movement. U.S. Patent Application 20240005127 and Patent 12518130 teach operations that accelerate GNN memory access in a near-memory manne r. U.S. Patent Application 20250307180 teaches co-processing acceleration with an in-memory compute element to perform in-memory processing on graph data. Kazi Asifuzzaman et al., 'A survey on processing-in-memory techniques: Advances and challenges' describes Processing-in-memory (PIM) techniques . Zhe Zhou et al., ' GCNear : A Hybrid Architecture for Efficient GCN Training with Near-Memory Processing' teaches Graph Convolutional Networks (GCNs) and offloading reduce operations to near memory elements. Sungmin Yun et al., ‘ GraNDe : Near-Data Processing Architecture With Adaptive Matrix Mapping for Graph Convolutional Networks’ teaches Graph Convolutional Networks (GCNs) and accelerat ing memory-intensive aggregation operations by locating processing elements near the DRAM datapath . Machine Translation of WIPO Publication WO 201115589 A1 teaches in-memory processing including extended commands. Machine Translation of Chinese Patent Application CN 118761448 A teaches an in-memory calculation (CIM) architecture can effectively avoid frequent data transportation , and a common solution is to expand new instructions suitable for AI calculation based on the existing CPU instruction set . Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT STEVEN G SNYDER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1971 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT M-F 8:00am-4:30pm (flexible) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration t ool. To schedule an interview, a pplicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN G SNYDER/ Primary Examiner, Art Unit 2184