DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Miyata (US Pub. 2018/0308854; on IDS) in view of Miyata (NPL-U) and/or Asanuma et al. (NPL reference 3 on IDS filed 06/03/2023).
Regarding independent claim 1, Miyata teaches a nonvolatile memory device (Fig. 6; para. 0037) having a laminated structure part including a plurality of first insulating layers (the HfO2 layers except for the topmost one) and a plurality of second insulating layers (the SiO2 layers above the lowermost SiO2 layer) formed with different compositions and disposed alternately (Fig. 6; para. 0037), and an O-M1-O layer (para. 0037) of a 0.5 molecular layer to a 2.0 molecular layer (para. 0037 teaches a one (1.0) molecular layer which lies inside of and therefore anticipates the claimed range (MPEP 2131.03, I) formed by a chemical bond between a metal element M1 and oxygen (refer to para. 0026), and disposed on each joining interface between each of the plurality first insulating layers and a corresponding one of the plurality of second insulating layers (Fig. 6), the metal element M1 being an element other than elements constituting the plurality of first insulating layers and the plurality of second insulating layers (para. 0037, also refer to para. 0026), and
a structure, wherein a silicon semiconductor substrate (n Si) and a silicon oxide underlayer (lowest SiO2 film) laminated on a surface of the silicon semiconductor substrate are disposed and one of the plurality of first insulating layers of the laminated structure part is laminated on the silicon oxide underlayer (Fig. 6; para. 0037), wherein a bottom surface of the laminated structure part is a surface of the one of the plurality of first insulating layers that faces a surface of the silicon oxide underlayer (Fig. 6), wherein an outermost surface of the laminated structure part is a surface of an uppermost layer of the plurality of second insulating layers that faces a hafnium oxide metal electrode underlayer (topmost HfO2layer), and an O-M1-O layer, the hafnium oxide metal electrode underlayer, and a metal electrode are laminated on the outermost surface in this order (Fig. 6),
and information being stored by modulating an interface dipole induced in a vicinity of the O-M1-O layer due to external electrical stimulation (abstract; para. 0028),
wherein the plurality of first insulating layers are formed of hafnium oxide and the plurality of second insulating layers are formed of silicon oxide (para. 0037),
wherein each of the plurality of first insulating layers have a thickness of 2 nm or less (para. 0037 teaching 1nm or 0.6 nm which lie inside of and therefore anticipates the claimed range (MPEP 2131.03, I)),
wherein each of the plurality of second insulating layers have a thickness of 2 nm or less (para. 0037 teaching 1.2nm which lies inside of and therefore anticipates the claimed range (MPEP 2131.03, I)),
wherein a number of O-M1-O layers with a modulable interface dipole is six or more (para. 0037 teaching six which lies inside of and therefore anticipates the claimed range (MPEP 2131.03, I)),
and wherein a thickness of the hafnium oxide metal electrode underlayer is 2nm (para. 0037).
Miyata teaches, with respect to the embodiment of Fig. 6, wherein the first insulating layers and the metal electrode underlayer are formed of hafnium oxide instead of the aluminum oxide as claimed.
However, Miyata teaches, with reference to the first embodiment, that other oxides could be used instead, including aluminum oxide (para. 0026).
It would have been obvious to one of ordinary skill in the art at the time of filing to substitute the hafnium oxide of the embodiment of Figure 6 with aluminum oxide as suggested by para. 0026 with a reasonable expectation of success. It is considered obvious to choose from a finite number of identified, predictable solutions, with a reasonable expectation of success (MPEP 2143, I, E). Furthermore, it is considered obvious to select a known material based on its suitability for its intended purpose (MPEP 2144.07).
Miyata teaches wherein a thickness of the metal electrode underlayer 2nm (para. 0037) which lies outside the claimed range of 3.5 nm to 5 nm.
Miyata_2 teaches the thickness of the metal electrode underlayer (top HfO2) to be 3.5 nm (MOS and FET fabrication) and Asanuma teaches the thickness of the metal electrode underlayer (top HfO2) to be 4 nm (Section II); thus, providing evidence that the range disclosed by the prior art overlaps the claimed range (note that a range can be disclosed in multiple prior art references instead of a single reference (MPEP 2144.05, I); therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have selected the overlapping portion of the range for the thickness of the metal electrode underlayer because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (MPEP 2144.05, I).
Re claim 4, Miyata teaches wherein the metal element M1 is Ti (para. 0026).
Re claim 8, Miyata is silent with respect to wherein the silicon semiconductor substrate includes a semiconductor region of a first conductive type, and a source region and a drain region of a second conductivity type, the source region and the drain region being disposed to be distanced from each other in a state where the source region and the drain region are partially exposed from a surface of the silicon semiconductor substrate and strength or polarity of the interface dipole induced in the vicinity of the O-Mi-O layer is changed by an electrical signal applied to the metal electrode within the embodiment of Figure 6.
However, Miyata teaches these features within the embodiment of Figure 12. That is, Miyata teaches (Fig. 12; para. 0044) wherein a silicon semiconductor substrate includes a semiconductor region (21) of a first conductive type (p), and a source region and a drain region (22, 23) of a second conductivity type (n), the source region and the drain region being disposed to be distanced from each other in a state where the source region and the drain region are partially exposed from a surface of the silicon semiconductor substrate (Fig. 12; para. 0044) and strength or polarity of the interface dipole induced in the vicinity of the O-M1-O layer is changed by an electrical signal applied to the metal electrode (para. 0044).
It would have been obvious to one of ordinary skill in the art at the time of filing to substitute the substrate of the embodiment of Figure 6 with the substrate of the embodiment of Figure 12 to arrive at the claimed invention for the purpose of providing a three terminal transistor based memory device (para. 0044).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Miyata (US Pub. 2018/0308854; on IDS) in view of Miyata (NPL-U) and Asanuma et al. (NPL reference 3 on IDS filed 06/03/2023).
Re claim 9, the combination of Miyata teaches a manufacturing method for the non-volatile memory device according to claim 1, comprising:
a deposition step of depositing and forming by an electron beam (EB) evaporation method a first insulating layer, an O-M1-O layer and the metal electrode underlayer (obvious to be aluminum oxide as explained above)) (para. 0037), and
a post heating step of heating the laminated structure part at a temperature of 450°C (which lies inside of and therefore anticipated the claimed range of “250°C or more” (MPEP 2131.03, I)) after the deposition step (para. 0037).
Miyata teaches depositing by electron beam evaporation method instead of ALD method.
Asanuma teaches the same lamination structure can be made using ALD with a post heating step of 300°C (which lies inside of and therefore anticipated the claimed range of “250°C or more” (MPEP 2131.03, I)) (III. Results and Discussion, 1st paragraph).
It would have been obvious to one of ordinary skill in the art at the time of filing to substitute the EB deposition method and post heating temperature of Miyata for the ALD and post heating temperature of Asanuma to arrive at the claimed invention for the purpose of providing a fabrication method suitable for mass production (I. Introduction, 1st paragraph).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4, 8, and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/Examiner, Art Unit 2899
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