Prosecution Insights
Last updated: April 19, 2026
Application No. 18/265,905

SEMICONDUCTOR MODULE COMPRISING AT LEAST ONE SEMICONDUCTOR ELEMENT

Non-Final OA §112
Filed
Jun 07, 2023
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siemens Aktiengesellschaft
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
91%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allow Rate
478 granted / 678 resolved
+2.5% vs TC avg
Strong +20% interview lift
Without
With
+20.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
36 currently pending
Career history
714
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.0%
+7.0% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
22.9%
-17.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 678 resolved cases

Office Action

§112
DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 6/7/2023 is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor Module With Heat Sink Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 18, 20-22, and 24-36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 18, 22 and 32 all use the term “and/or”. Considering a claim may only describe one invention, it becomes unclear what exactly that invention would be (i.e. whether the invention includes both limitations preceding and following “and/or”, respectively, or whether the invention only includes one those limitations. Furthermore, pertaining to claim 18, the limitation “wherein the metallic heat sink is connected to the substrate metallization of the second substrate in a materially bonded manner” does not appear to further limit claim 17, which recites “said main body [of the metallic heat sink] having a circumferential contact surface around the fin to establish a material-bonded connection with a substrate metallization of the second substrate”. Claim 20 recites “the recess of the second substrate includes an edge metallization via which a material-bonded connection with the metallic heat sink is established”. This language is confusing, as the edge metallization does not facilitate material-bonded connection. Rather, it is one of two objects that is bonded. Claim 24 recites the same limitation at the end of the claim. Claims 28 and 29 recite the limitation “a semiconductor module”. However, this limitation is already recited in claims 17 and 24 on which they respectively depend. Without be preceded by “the” or “said”, it is not clear whether this is the same semiconductor module described in the independent claims. Claim 31 uses the terms “semiconductor module” and “semiconductor element” (see lines 2, 4, 7, 9 and 17). Although they are different terms, they appear to be describing the same feature. Considering the device claims (e.g. claim 17) describe the semiconductor element, the first and second substrates, and the metallic heat sink as being parts of a semiconductor module (see preamble – “A semiconductor module, comprising …”), it appears that instances of the term “semiconductor module” in claim 31 should instead be “semiconductor element”. If that is not the case, then the limitation “the semiconductor element” as recited in claims 31, 32, 33 would lack antecedent basis. Claim 36 also uses the terms “semiconductor module” and “semiconductor element”. Claim 34 recites the limitation “establishing a material-bonded connection to the metallic heat sink via an edge metallization of the recess of the second substrate”. First, it is not clear what is meant by the term “edge metallization of the recess”, as the recess as disclosed does not have an edge metallization. Further, it is not clear what is meant by “establishing a material-bonded connection … via an edge metallization”. As disclosed, the edge metallization does not facilitate material-bonded connection. Rather, it is one of two objects that is bonded. Allowable Subject Matter Claims 17, 19, and 23 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The claimed device has features including a finned heat sink residing in a recess of a substrate. Prior art such as Wu et al. (US 10,811,332), Molla et al. (US 10,141,182), Lamorey et al. (US 9,209,141) and Lamorey et al. (US 9,059,127) all disclose inventions having this feature. However, whether alone or in combination, the prior art does not teach each and every limitation of claim 17, including first and second substrates, where the semiconductor element has a first side in contact with the first substrate in a planar manner and a second side facing away from the first side and in contact with the heat sink in a planar manner, wherein the fin of the heat sink is arranged in the recess of the second substrate and the main body of the heat sink has a circumferential contact surface around the fin to establish a material-bonded connection with a substrate metallization of the second substrate, wherein the circumferential contact surface is arranged on a side of the main body facing away from the semiconductor element. Thus, such subject matter is allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Jun 07, 2023
Application Filed
Feb 19, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604725
INTERLEVEL DIELECTRIC STRUCTURE IN SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598977
FILL OF VIAS IN SINGLE AND DUAL DAMASCENE STRUCTURES USING SELF-ASSEMBLED MONOLAYER
2y 5m to grant Granted Apr 07, 2026
Patent 12575310
DISPLAY APPARATUS HAVING A REPAIR WIRING
2y 5m to grant Granted Mar 10, 2026
Patent 12568815
WIRINGS FOR SEMICONDUCTOR DEVICE ARRANGED AT DIFFERENT INTERVALS AND HAVING DIFFERENT WIDTHS
2y 5m to grant Granted Mar 03, 2026
Patent 12564025
Interconnect with Redeposited Metal Capping and Method Forming Same
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
91%
With Interview (+20.5%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 678 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month